KR102279278B1 - Display Device And Driving Method for the Same - Google Patents

Abstract

The present invention relates to a display device that reduces power consumption and prevents flicker at the same time by lowering a refresh rate depending on whether an input image is stopped or a gray level, and a method of driving the same. a display panel including a plurality of gate lines and data lines defining and a timing controller having a setting unit, a gate driver receiving the refresh rate information to control a period of a gate signal for each line, and a data driver receiving the refresh rate information and supplying an image signal to the data lines.

Description

Display device and driving method thereof {Display Device And Driving Method for the Same}

The present invention relates to a display device, and more particularly, to a display device that simultaneously reduces power consumption and prevents flicker by setting a refresh rate differently depending on whether an input image is stopped and a gray level, and a method of driving the same.

Recently, as we enter the information age in earnest, the field of display that visually expresses electrical information signals has developed rapidly, and in response to this, various flat display devices with excellent performance of thinness, light weight, and low power consumption have been developed. It has been developed and is rapidly replacing the existing cathode ray tube (CRT).

Specific examples of such a flat panel display device include a liquid crystal display (LCD), a plasma display panel device (PDP), a field emission display device (FED), an electroluminescent display device ( Electro Luminescence Display Device (ELD), etc., which in common use a flat panel display panel that implements an image as an essential component, and the flat panel display panel is a pair of flat panel display panels with a material layer having inherent light emitting or optical anisotropy interposed therebetween. It has a structure in which a transparent insulating substrate of

Meanwhile, the aforementioned flat panel display is driven at a specific frequency, such as 60Hz, for display. Recently, there has been a demand for reducing power consumption by varying the driving frequency for each frame according to the type of image.

However, since the pulse period for each gate line is long when driving at a low frequency, the discharge time between frames that are inverted with different polarities is long, the charge leakage value in the pixel is large, the residual DC value is large, and thus flicker on the screen is reduced. There is a phenomenon that occurs. In addition, since such a flicker is proportional to ΔVp, there is a problem in that the longer the discharge time, that is, the longer the period, the more pronounced the flicker phenomenon.

As described above, although low-frequency driving has the advantage of reducing power consumption, there is a problem in that it is difficult to apply the flicker phenomenon because it is difficult.

In addition, the method of adjusting the frequency for each frame requires that the image displayed on the screen is partly a moving image and partly a still image, and must be driven consistently at a high frequency. In this case, the timing controller and driver IC still drive high-speed at high frequency. This is required, and there is a problem of large power consumption.

The present invention has been devised to solve the above problems, and relates to a display device and a method of driving the same for reducing power consumption and preventing flicker at the same time by setting a refresh rate differently depending on whether an input image is stopped or a gray level it's about

In order to achieve the above object, a display device according to the present invention provides a display panel including a plurality of gate lines and data lines that cross each other to define pixels, and receive image data for a plurality of pixel rows from a system to display an image. A timing controller having a refresh rate setting unit for setting refresh rate information for each pixel row with respect to still/moving status and gradation level, a gate driver receiving the refresh rate information to control a period of a gate signal for each line, and the refresh rate information and a data driver for receiving and supplying an image signal to the data lines.

Here, the refresh rate setting unit includes a line memory for storing image data for each pixel row from the system, a static motion determining unit for classifying a still image and a moving image of the image data for each pixel row, and the image data for each pixel row, respectively. and first and second gray discriminators for discriminating gray levels for each image and moving picture.

The above-described method of driving a display device includes a first step of storing image data for each pixel row from a system, a second step of classifying a still image and a moving image of the image data for each pixel row, and the image for each pixel row. When the data is a still image, the gray level is determined, and when the gray level is higher than the first gray level, the timing signal is output at an intermediate refresh rate, and when the gray level is lower than the first gray level, the timing signal is output at a low refresh rate. Step 3, when the image data for each pixel row is a moving picture, determining a gray level, when the gray level is higher than the second gray level, at a high refresh rate, and when the gray level is lower than the second gray level, A fourth step comprising outputting a timing signal at an intermediate refresh rate, and transferring the timing signal for the image data for each pixel row obtained in the third and fourth steps to a gate driver and a data driver, and a fifth step of adjusting the refresh rate.

In the display device and driving method thereof of the present invention having the above characteristics, the refresh rate driven for each gate line (each pixel row connected thereto) is set differently so that a still image is spatially divided when a still image is in a part of the screen. Thus, only the necessary parts are driven at the high refresh rate timing and the remaining parts are driven at the low refresh rate timing, thereby dramatically reducing power consumption in the timing controller and data driver.

In addition, in order to prevent a flicker from occurring when a high gray level is expressed at a low refresh rate, the high gray level of the low refresh rate may increase the driving refresh rate to prevent the occurrence of flicker.

That is, it is possible to spatially drive a still image/video/partial video on one screen, thereby maximizing power consumption reduction and simultaneously preventing a flicker phenomenon.

1 is a block diagram showing a display device according to the present invention;
2 is a block diagram illustrating the timing controller of FIG. 1 and an interface thereof;
3 is a block diagram illustrating an internal configuration of a data driver connected to the timing controller of FIG. 2
4 is a block diagram illustrating an example of a refresh rate setting unit for each line of FIG.
5 is a flowchart illustrating a method of driving a display device according to the present invention;
6 is a photograph showing the driving of the display device of the present invention;
7 is a graph showing changes in Vp-p according to grayscale during 20Hz refresh driving and 60Hz refresh driving; FIG.

Hereinafter, a display device and a driving method thereof of the present invention will be described with reference to the accompanying drawings.

Hereinafter, a display device to be described will be representatively described with respect to a liquid crystal display device, but is not limited thereto, and other types of flat panel display devices such as an organic light emitting display device or a plasma display panel are not limited thereto. Device: PDP), field emission display device (FED), electrophoretic display device, etc. can be applied.

That is, the present invention sets the refresh rate for each pixel row (horizontal line), and the refresh rate can be varied according to the gray level of the inputted image for each pixel row and whether it is a still/video, which crosses each other to define the pixels. It is applicable to a structure including a plurality of gate lines and data lines and having a driving driver thereof.

1 is a block diagram illustrating a display device of the present invention, and FIG. 2 is a block diagram illustrating the timing controller of FIG. 1 and an interface thereof.

1 , the display device of the present invention includes a display unit DSP, a system 300 , a timing controller 22 , a data driver 24 , and a gate driver 30 .

The display unit DSP includes i*j (i, j is a natural number greater than 1) pixels PX, i data lines, and j gate lines GL1 to GLj in a kind of panel. do. Here, first to j-th gate signals are respectively applied to the first to j-th gate lines GL1 to GLj, and a data voltage is respectively applied to the first to i-th data lines DL1 to DLj. .

The display unit DSP may be a liquid crystal panel, an organic light emitting display panel, or an electrophoretic display panel.

The pixels PX are arranged in the display unit DSP in a matrix form. The pixels PX are divided into a red pixel R for displaying red, a green pixel G for displaying green, and a blue pixel B for displaying blue. In this case, the red, green, and blue pixels R, G, and B adjacent in the horizontal direction become unit pixels for displaying one unit image.

Here, when the display device of the present invention is a liquid crystal display device, the pixel may be composed of a thin film transistor, a pixel electrode, a common electrode, and liquid crystal.

The i pixels (hereinafter, n-th horizontal line pixels) arranged along the n-th horizontal line (n is any one of 1 to j) are individually provided to each of the first to i-th data lines DL1 to DLi. It is connected through a TFT (Thin Film Transistor) (not shown). In addition, these nth horizontal line pixels are commonly connected to the nth gate line through respective TFTs. Accordingly, the nth horizontal line pixels receive the nth gate signal in common. That is, all i pixels arranged on the same horizontal line receive the same gate signal, but pixels located on different horizontal lines receive different gate signals. For example, the red pixel R, the green pixel G, and the blue pixel B located on the first horizontal line HL1 all receive the first gate signal, while the red pixel R, the green pixel G, and the blue pixel B located on the second horizontal line HL2 receive the first gate signal. The red pixel (R), the green pixel (G), and the blue pixel (B) are supplied with the second gate signal having a timing different from these. That is, the rising timing of each gate signal is different.

Although the above-described j gate signals have the same gate on time, the low-level time width of the gate output enable signal GOE for each gate line applied from the timing controller 22 is applied. By adjusting, each refresh rate can be different. For example, the timing controller 22 divides the image data to be input for each horizontal line pixel into a low frequency, an intermediate frequency, and a high frequency according to whether a moving image/still image is present and a grayscale level, so that the refresh rate is different. In this case, if the frame is 60 Hz, the low frequency may be set to 1 Hz, the intermediate frequency to 20 to 30 Hz, and the high frequency to 60 Hz. In the case of a moving picture, first set above the intermediate frequency, compare it with a specific gradation level at which flicker can be identified, and set a high refresh rate if it is above a specific gradation level and set to an intermediate refresh rate if it is below a specific gradation level. Also, in the case of a still image, it is set to below the intermediate frequency, and compared with a specific gray level that can detect flicker again, if it is above a specific gray level, the intermediate refresh rate is used, and if it is below the specific gray level level, the low refresh rate is used. set Here, specific grayscale levels for a still image and a moving image may be the same or different. In this case, each intermediate frequency value may be different.

Meanwhile, the system 300 outputs the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal DCLK and the image data R/G/B through the interface circuit through the transmitter of the graphic controller. . The vertical/horizontal synchronization signal and clock signal output from the system 300 are supplied to the timing controller 22 . In addition, image data sequentially output from the system 300 is supplied to the timing controller 22 .

Specifically, as shown in FIG. 2 , the timing controller 22 receives an interface 210 to which image data and timing signals are input from the system 300 , and receives an input image for each pixel row from the interface 210 to stop/stop the image. A refresh rate setting unit 220 for each line that sets refresh rate information for each line with respect to whether a video is in motion and a gradation level, and a clock signal from the interface 210 and the refresh rate setting unit 220 for each line. and a timing signal generator 230 for outputting a gate output enable signal GOE and a source output enable signal SOE according to the rate information. The input image for each pixel row from the interface 210 outputs a digital image signal (R/G/B Data) and a polarity signal (POL) for each pixel row through the refresh rate setting unit 220 for each line. .

On the other hand, image data and timing signals are received directly from the system 300 and may generate signals for timing and driving of each gate driver 30 and data driver 24 through internal processing, but in general, several types of systems 2 , it may be preferable to provide an interface 210 at the input terminal, as shown in FIG. 2 , which receives a signal in a serial manner to be compatible with The interface 210 is a kind of LVDS (Low Voltage Differential Signaling) receiver, and an output terminal of the corresponding system 300 may further include an LVDS transmitter. The interface 210 may be an internal interface of another type instead of LVDS.

A horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, a clock DCLK, and image data Data are received from the system 300 through the interface 210 . The vertical synchronization signal Vsync indicates the time required to display the screen of one frame. The horizontal synchronization signal Hsync represents a time required to display one horizontal line of the screen, that is, one pixel row.

Accordingly, the horizontal synchronization signal includes as many pulses as the number of pixels included in one pixel row (horizontal line). The data enable signal DE indicates a period in which valid image data is located for each pixel row. In addition, the timing controller 22 rearranges the image data so that the image data of a predetermined bit supplied from the interface can be supplied to the data driver 24 . In addition, the timing controller 22 receives the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the clock signal DCLK from the interface to receive the data control signal DCS and the source output enable signal. A signal SOE, a gate output enable signal GOE, and a gate control signal GCS are generated and supplied to the data driver 24 and the gate driver 30 .

In general, in a method in which each pixel row is driven at the same refresh rate, each gate output enable signal GOE is applied in a shifted form with a pulse signal having the same pulse width to each gate line, but in the present invention In the display device of , the refresh rate can be varied according to the type of image and the gradation state, and the period of the gate output enable signal GOE of each gate line can be varied under the discrimination of the input image for each horizontal line. can That is, for example, gate lines are divided into blocks, and the gate control signal (GCS) is divided into a low refresh rate, an intermediate refresh rate, or a high refresh rate. ), a gate output enable signal GOE for each gate line may be supplied. For example, comparing the gate line to which the gate output enable signal is applied at the high refresh rate of 60 Hz frame and the same rate as the high refresh rate of 1 second, a total of 60 gate output enable signals (GOE) at the high refresh rate of 60 Hz are compared. ) is generated, but, in contrast, the first gate output enable signal is generated in the gate line to which the gate output enable signal GOE is applied at a low refresh rate of 1 Hz. Accordingly, the data of the pixel rows connected to each gate line is applied 60 times and 1 times, respectively, and spatial driving is possible for each region, and when the refresh rate is relatively low, the data from the timing controller 22 is Power consumption can be reduced by reducing the amount of data transmitted to the driver 24 and reducing the amount of processing in the data driver 24 . Here, the data application for each pixel row may be adjusted according to a change in a high level and a low level of the source output enable signal SOE in the timing controller 22 . For example, when the source output enable signal SOE is at a high level, data is supplied to the data lines, and when the source output enable signal SOE is at a low level, data is prevented from being supplied to the data lines. The source output enable signal SOE for each pixel row corresponds to the generation of the corresponding gate output enable signal GOE, and may appear shifted for a predetermined time.

3 is a block diagram illustrating an internal configuration of a data driver connected to the timing controller of FIG. 2 .

In the drawing, one data driver 24 is provided for each pixel row, but it may be divided into a plurality of data drive ICs and provided in the display panel.

As shown in FIG. 3 , the data control signal DCS supplied to the data driver 24 includes a source sampling clock signal SSC, a source output enable signal SOE, and a source start pulse signal. There are SSP: Source Start Pulse) and Polarity reverse signal (POL: Polarity reverse) signal.

In addition, the data driver 24 includes a shift register SR, a first latch unit LT1, a second latch unit LT2, a multiplexer MUX, and a digital-to-analog converter (DAC) and a buffer unit (BFU). includes

The shift register SR sequentially generates a sampling signal based on the source start pulse signal SSP and the source sampling signal SSC.

The source sampling clock signal SSC is used as a sampling clock for latching image data in the data driver 24 and is set according to the highest refresh rate among refresh rates applied to the pixel row.

The first latch unit LT1 sequentially samples the image data Data of one horizontal line according to the sampling signal from the shift register SR, and latches the sampled image data. The second latch unit LT2 simultaneously latches the image data sampled from the first latch unit LT1 in accordance with the rising edge of the source output enable signal SOE, and polling the source output enable signal SOE. Sampling image data latched in accordance with the edge timing is simultaneously output. The cycle of the source output enable signal SOE may be different for each line. That is, to the pixel rows driven at a low refresh rate, the source output enable signal SOE may be applied at a cycle of several times or tens of times to the pixel rows driven at a different high refresh rate.

The multiplexer MUX simultaneously receives the sampled image data from the second latch unit LT2 and rearranges output positions of the sampled image data according to the polarity inversion signal POL.

Meanwhile, the source output enable signal SOE transmits image data latched by the source sampling clock signal SSC to the display unit. The source start pulse signal SSP is a signal indicating the start of latching or sampling of image data during one horizontal period. If the gate output enable signal GOE is applied to a predetermined gate line at a low refresh rate, a plurality of horizontal periods The source output enable signal SOE may be applied to the high level level only once. The polarity inversion signal POL is a signal indicating the polarity of a data voltage (an analog signal for image data) to be supplied to a pixel for inversion driving of a display device, and for pixel rows having different refresh rates, The polarity inversion signal POL may be applied another number of times. That is, inversion of the polarity inversion signal POL occurs more in pixel rows having a high refresh rate than in pixel rows having a low refresh rate.

The digital-to-analog converter DAC converts the sampled image data provided from the multiplexer MUX into data voltages that are analog signals. A positive digital-to-analog converter and a negative digital-to-analog converter are included therein, and the input grayscale voltages (GMAs) of the corresponding polarity are converted into positive or negative data voltages.

In addition, the buffer unit BFU buffers the data voltages of the positive polarity and the data voltages of the negative polarity provided from the digital-to-analog converter DAC and outputs the buffered data voltages.

4 is a block diagram illustrating an embodiment of a refresh rate setting unit for each line of FIG. 2 , and FIG. 5 is a flowchart illustrating a method of driving a display device according to the present invention.

As shown in FIG. 4 , the refresh rate setting unit 220 for each line separates the line memory 221 for storing image data for each pixel row from the system 300 and a still image and a moving image of the image data for each pixel row. and a static motion determining unit 222 that determines the image data for each pixel row, and first and second gray determining units 224a and 224b for determining a gray level for each still image and each moving image, respectively.

Here, the information on the first gradation level, which is the criterion for determining the gray level of the still image, and the second gradation level, which is the criterion for judging the gray level of the still image, is provided in advance to the refresh rate setting unit in a lookup table (LUT), the first and second grayscale levels may be set as values at which flicker is identified by observing the flicker phenomenon for each frequency and grayscale level of the corresponding display panel model in advance.

A method of driving the display device of the present invention using the refresh rate setting unit 220 for each line is as follows.

That is, as shown in 5, first, image data for each pixel row is stored from the system (100S).

Next, a still image and a moving image of the image data for each pixel row are divided (110S).

When the image data for each pixel row is a still image, a gray level is determined ( 120S). At this time, when the grayscale level is higher than the first grayscale level, the timing signals GOE and SOE are output at the intermediate refresh rate (122S). If the gray level of the corresponding image data is lower than the first gray level, the timing signals GOE and SOE are output at a low refresh rate (125S).

When the image data for each pixel row is a moving image, a gray level is determined (130S).

At this time, when the grayscale level is higher than the second grayscale level, the timing signals GOE and SOE are output at a high refresh rate (132S). If the gray level of the corresponding image data is lower than the second gray level, a timing signal is output at an intermediate refresh rate (135S).

Then, the timing signals GOE and SOE for the image data for each pixel row obtained in the above-described moving/still image determination and gray level determination are transmitted to the gate driver 30 and the data driver 24, and the gate line Adjust the refresh rate for each (pixel row).

Here, the high refresh rate is the maximum frequency for each frame of the moving picture of the corresponding display panel, and may be, for example, 60 Hz or a multiple thereof. The low refresh rate corresponds to a still image and a low grayscale level in the corresponding display panel, and may be, for example, 1 Hz.

As described above, the intermediate refresh rate may be set to be the same as the low gray level of the moving image and the high gray level of the still image, or may be set differently. The intermediate refresh rate may be about 10 Hz to 50 Hz, and may be set differently depending on need therebetween, and may be the lowest grayscale level at which flicker is identified in the lookup table of the corresponding model.

A screen to which the above-described method of driving a display device of the present invention is applied will be described with reference to FIG. 6 .

6 is a photograph illustrating driving of the display device of the present invention.

As shown in FIG. 6 , in one screen, a fixed background, such as the sky or a motionless rock, may be treated as a still image. However, in the high grayscale level expressed brightly like the sky, the ΔVp value is large due to the large pixel charge leakage in the section where the image signal is inverted when driving at low frequency, and thus flickering phenomenon may occur. , rather than a low refresh rate such as 1 Hz, the refresh rate was raised to 20-30 Hz, which is a level at which flicker cannot be identified.

On the other hand, in the area at the bottom of the area with a background close to black, such as a rock, the expressed gradation level is low, and the change in ΔV in the section where the image signal is inverted is small, so no flicker phenomenon was observed even when driven at a low frequency such as 1Hz .

In addition, in the area where the penguin's movement appears, high-speed driving, such as 60 Hz, is performed to facilitate expression of the movement.

On the other hand, the refresh rate setting unit determines that, when the image data of the pixel row is a mixture of moving images and still images, the refresh rate is set according to the moving image, and, for the gradation level, the high gradation level and the low gradation level are mixed. In this case, the refresh rate is set according to the high gradation level. That is, when there is a moving picture of a penguin in the center of the screen of FIG. 6 and a part with a building with a bright background, a refresh rate of 60 Hz is set to sufficiently express the moving picture.

7 is a graph showing changes in Vp-p according to gray levels when a 20 Hz refresh rate is driven and when a 60 Hz refresh rate is driven.

When RGB(0, 0, 0) to RGB(255, 255, 255) is expressed in 32 gray scale, RGB(0, 0, 0) is a low gray scale that displays black. , and RGB(255, 255, 255) corresponds to a high gray level displaying white.

As shown in Fig. 7, when the refresh rate of 60 Hz of relatively high frequency, the change range of Vp-p (ΔVp) between frames is not large, but at the refresh rate of 20 Hz, when the refresh rate is low, the gray level goes to a high gradation, Since the Vp-p change width is large, it is expected that the pixel charge leakage between frames will be large, and thus it can be expected that the flicker phenomenon is easily identified. Accordingly, in the driving method of the display device of the present invention, a low frequency is not set for a still image, the gradation level is determined, and when a high gradation level is required to be expressed, flicker is not identified for the pixel row. It is characterized in that the refresh rate is increased.

That is, in the display device and the driving method thereof of the present invention, the refresh rate driven for each gate line (each pixel row connected thereto) is set differently, and when a still image is in a part of the screen, it is spatially divided and only the necessary part is used. Power consumption in the timing controller and the data driver can be dramatically reduced by driving at the timing of the high refresh rate and driving the rest at the timing of the low refresh rate.

In addition, in order to prevent a flicker from occurring when a high gray level is expressed at a low refresh rate, the high gray level of the low refresh rate may increase the driving refresh rate to prevent the occurrence of flicker.

That is, it is possible to spatially drive a still image/video/partial video on one screen, thereby maximizing power consumption reduction and simultaneously preventing a flicker phenomenon.

In some cases, in the timing diagram of FIG. 5 , the still image is set to be below the intermediate frequency, but when the flicker of the still image is severe at a high gray level, the driving refresh rate may be further increased to a high refresh rate.

Also, in the above example, the low refresh rate is described as 1 Hz and the high refresh rate is 60 Hz as the example, but the present invention is not limited thereto, and the range may be adjusted. The point applied in the present invention is that the driving refresh rate can be varied for each line (horizontal pixel row) rather than having a specific frequency, and the adjustment is made according to whether the input image is a moving image/still image and the grayscale level. to be classified as such.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those of ordinary skill in the art.

22: timing controller 24: data driver
30: gate driver 210: interface
220: refresh rate setting unit for each line 230: timing signal generating unit
221: line memory 222: affect determination unit
224a: first gray level determining unit 224b: second gray level determining unit
300: system 100: display unit

Claims (9)

a display panel including a plurality of gate lines and data lines crossing each other to define pixels;
a timing controller having a refresh rate setting unit that receives image data for each pixel row from the system and sets refresh rate information for each pixel row with respect to whether the image is still/moving and whether the image is still/moving;
a gate driver receiving the refresh rate information and controlling a period of a gate signal for each line; and
and a data driver receiving the refresh rate information and supplying an image signal to the data lines;
The refresh rate setting unit,
a first gradation level of a flicker identification criterion of a still image and a second gradation level of a flicker identification criterion of a moving image;
After determining whether the image data for each pixel row is a still image or a moving image,
In the case of a still image, the gray level of the image data per pixel row is compared with the first gradation level, and in the case of a moving image, the gray level of the image data per pixel row is compared with the second gradation level, and the refresh rate for each pixel row is A display device for distinguishing information. The method of claim 1,
The refresh rate setting unit,
a line memory for storing the image data for each pixel row from the system;
an affect determining unit for classifying a still image and a moving image of the image data for each pixel row; and
and a first and second gray discriminator for discriminating a gray level of each still image and each moving image in the image data for each pixel row, respectively. 3. The method of claim 2,
and the first and second gray discrimination units output timing signals having different refresh rates for each pixel row. 4. The method of claim 3,
wherein the timing signal includes a gate output enable signal and a source output enable signal, and the gate output enable signal and the source output enable signal are transmitted to a gate driver and a data driver, respectively. 4. The method of claim 3,
wherein the first gray determination unit outputs a timing signal of a first intermediate refresh rate when the gray level of the still image is higher than the first gray level, and a timing signal of a low refresh rate when the gray level of the still image is lower than the first gray level. display device. 6. The method of claim 5,
The second gray determining unit outputs a timing signal of a high refresh rate when the gray level of the moving picture is higher than the second gray level level and a second intermediate refresh rate when the gray level is lower than the second gray level level. 7. The method of claim 6,
and a lookup table having information on the first grayscale level and the second grayscale level in the refresh rate setting unit of the timing controller. A method of driving a display device including a plurality of gate lines and data lines crossing each other to define pixels, the method comprising:
a first step of storing image data for each pixel row from the system;
a second step of classifying a still image and a moving image of the image data for each pixel row;
When the image data for each pixel row is a still image, a gray level is determined, and when the gray level is higher than the first gray level level of the flicker identification criterion of the still image, the first intermediate refresh rate is higher than the first gray level level. a third step of outputting a timing signal at a low refresh rate when the gradation level is low;
When the image data for each pixel row is a moving picture, a gray level is determined, and when the gray level is higher than the second gray level level of the flicker identification standard of the video, the gray level is lower than the second gray level level at a high refresh rate a fourth step including outputting the timing signal at the second intermediate refresh rate when and
and a fifth step of controlling the refresh rate for each gate line by transferring the timing signal for the image data for each pixel row obtained in the third and fourth steps to a gate driver and a data driver. How to drive the device.
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