KR20180002966A - Display Device - Google Patents

Abstract

According to the present invention, a display device comprises a display panel, a timing controller, and a data driving unit. In the display panel, a pixel is positioned at a region where a data line and a gate line cross each other. The timing controller generates an over driving (OD) image data on the basis of a variation of input image data in a gray scale range of 0 to k represented by the number of input data bits. The data driving unit generates a data voltage by converting the OD image data into a gamma voltage. The data driving unit includes: a first gamma voltage generating unit for generating a gamma voltage in a gray scale range of 0 to k (k is a natural number); a second gamma voltage generating unit for generating a gamma voltage lower than a gray scale of 0; and a second gamma voltage generating unit for generating a gamma voltage in a gray scale range of (k + j) (k is a natural number). A response speed can be enhanced.

Description

[0001]

The present invention relates to a display device for overdriving driving.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) ).

Among them, a liquid crystal display device of an active matrix driving system displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, and the like, and is rapidly applied to a television to quickly replace a cathode ray tube. Pixels of a liquid crystal display include thin-film transistors that are crossed with a data line and a gate line and are connected to the intersections. The thin film transistor supplies the data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to the gate pulse from the gate line.

The liquid crystal cell is rotated by an electric field generated according to the voltage difference between the pixel electrode and the common voltage Vcom applied to the common electrode to control the light flux passing through the polarizer. Therefore, the response speed of the liquid crystal display device is proportional to the rate at which the data voltage to be written from the data line is charged to the pixel electrode. When the response speed of the liquid crystal display device is slow, there are problems such as afterimage of the display image and motion blur. Therefore, techniques for improving the response speed of the liquid crystal display device have been proposed.

For example, an over driving method is known as a method for improving a response speed of a liquid crystal display device. Overdriving driving can improve the response speed by modulating the video data, but there is a disadvantage that it can not be performed on the entire range of input video data.

The present invention is intended to provide a display device capable of improving the response speed.

A display device according to the present invention includes a display panel, a timing controller, and a data driver. In the display panel, a pixel is located in an area where the data line and the gate line cross each other. The timing controller generates the audio image data (OD image data) based on the amount of change of the input image data in the range of 0 to k gradation expressed by the number of input data bits. The data driver converts the audi image data into a gamma voltage to generate a data voltage. The data driver includes a first gamma voltage generator for generating a gamma voltage in a range of 0 to k (k is a natural number) gradation, a second gamma voltage generator for generating a gamma voltage lower than 0 gradation, and (k + j) And a second gamma voltage generator for generating a gamma voltage in a gradation range.

According to the present invention, overdriving driving can be applied to all the gradation areas of input image data, thereby greatly improving the response speed of the liquid crystal display device.

In particular, it is possible to improve the distortion of the display of the black image due to the delay of the data voltage in the low gradation region.

1 is a view showing a display device according to the present invention.
2 is a diagram showing an audio generating unit according to the present invention.
FIG. 3 is a view showing an embodiment of the look-up table shown in FIG. 2. FIG.
4 is a diagram showing a configuration of a data driver according to the present invention.
5 is a view showing the gamma voltage compensator shown in FIG.
6 is a diagram showing an embodiment of the gamma voltage outputted by the gamma voltage compensating unit.
7 and 8 are diagrams for explaining overdriving driving.
9 is a view for explaining a driving method according to a comparative example.
Fig. 10 is a view for explaining low grayscale overdriving driving. Fig.
11 is a diagram for explaining a low gray scale driving method according to a comparative example.
12 to 15 are diagrams for explaining a display device to which low-gradation over-driving is applied.
16 is a view for explaining the principle of setting the compensation value of the look-up table differently.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is a view showing a display device according to the present invention.

1, the display device of the present invention includes a display panel 100, a timing controller 110, a level shifter 130, a shift register 140, a data driver 150, and a reference voltage generator 160 .

The display panel 100 includes a pixel array in which pixels arranged in a matrix are formed, and displays gradations based on the input image data. The pixel array includes a TFT array formed on the lower substrate, a color filter array formed on the upper substrate, and liquid crystal cells (Clc) formed between the lower substrate and the upper substrate. The TFT array is provided with a data line DL, a gate line GL which intersects the data line DL, TFTs formed at intersections of the data line DL and the gate line GL, pixel electrodes 1 ), A storage capacitor (Cst), and the like are formed. In the color filter array, a color filter array including a black matrix and a color filter is formed. The common electrode 2 may be formed on the lower substrate or the upper substrate. The liquid crystal cells Clc are driven by the electric field between the pixel electrode 1 to which the data voltage is supplied and the common electrode 2 to which the common voltage Vcom is supplied. On the upper substrate and the lower substrate of the display panel 100, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed at the interface with the liquid crystal layer. Between the upper substrate and the lower substrate of the display panel 100, a spacer for maintaining a cell gap of the liquid crystal layer is disposed.

The timing controller 110 receives input image data RGB from an external host and receives a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE, a main clock CLK, As shown in FIG. The timing controller 110 generates a data timing control signal DDC for controlling the operation timing of the data driver 150 using the timing signals Vsync, Hsync, DE and CLK and the operation timings of the gate drivers 130 and 140 And generates a gate timing control signal GDC for controlling.

The OD generator 200 of the timing controller 110 generates OD image data OD_Data for over driving. The OD generator 200 compares the i-th field data field i-1 with the i th field data field i and outputs the audio data according to the difference of the input video data to be compared. (OD_Data). The [i-1] field data means input image data (RGB) of the previous field, and the i-th field data means input image data (RGB) of the current field.

One field may correspond to one horizontal line (HL) in the display panel 100. For example, the [i-1] field indicates input image data RGB of pixels belonging to the [i-1] th horizontal line HL [i-1] in the display panel 100, (RGB) of pixels belonging to the i-th horizontal line HL [i] in the display panel 100. [

One field may be one frame of input image data (RGB). For example, the [i-1] field indicates the input image data (RGB) of the [i-1] frame and the i-th field indicates the input image data (RGB) of the i-th frame.

In addition, one field may be input image data (RGB) of pixels belonging to one horizontal line HL in the display panel 100. For example, the [i-1] field means input image data (RGB) of the [i-1] th horizontal line and the i-th field means input image data (RGB) of the i-th horizontal line.

FIG. 2 is a diagram showing the configuration of the OD generator 200, and FIG. 3 is a diagram showing an embodiment of the lookup table shown in FIG.

2 and 3, the OD generator 200 includes a field memory 11, a lookup table 12, and a selector 13.

The field memory 11 stores the [i-1] th field data Field [i-1]. The lookup table 12 stores OD image data OD_Data which are respectively matched to the i-th field data Field [i-1] and the i th field data Field [i]. The selector 13 extracts the OD image data OD_Data matching the i-th field data Field [i-1] and the ith field data Field [i] and outputs the OD image data OD_Data to the data driver 150 to provide.

3, the OD generator 200 generates the i-th field data Field [i-1] and the i-th field data Field [i] And outputs the i-th field data (Field [i]) as OD image data (OD_Data).

The OD generating unit 200 generates the OD image data OD_Data (i-1) to which the compensation value is added when the i-th field data Field [i] ). 3, when the [i-1] field data Field [i-1] is "0" and the i-th field data Field [i] Unit 200 adds the compensation value " 14 " to the i-th field data Field [i] to generate OD image data OD_Data. In particular, when the i-th field data Field [i] is greater than the [i-1] th field data field [i-1] The compensation value is added. As a result, the OD image data OD_Data may be generated to have high gradation OD image data OD_Data exceeding the range of the input image data RGB. In the present specification, although the range of the high gradation OD image data (OD_Data) is described mainly from the example of "256" to "260", the size and the number of the high gradation OD image data (OD_Data) .

The data driver 150, which will be described later, includes a high gray level gamma voltage generator for generating a high gray level gamma voltage corresponding to the high gray level OD image data OD_Data.

The OD generator 200 subtracts the compensation value when the ith field data Field [i] is smaller than the [i-1] field data Field [i-1] ). 3, when the [i-1] field data field [i-1] is 64 and the i-th field data Field [i] The unit 200 generates the OD image data OD_Data by subtracting the compensating buffer 6 from the i-th field data Field [i]. In particular, when the i-th field data Field [i] is smaller than the [i-1] th field data field [i-1] The compensation value is subtracted. As a result, the OD image data OD_Data may be generated with low gradation OD image data OD_Data exceeding the range of the input image data RGB. The data driver 150, which will be described later, includes a low gray level gamma voltage generating unit for generating a low gray level gamma voltage corresponding to the low gray level OD image data OD_Data.

Although the low gradation OD image data (OD_Data) is described herein with reference to the embodiments of " 261 " and " 262 ", the size and the number of the low gradation OD image data (OD_Data) .

The OD image data OD_Data may be composed of a number of bits larger than the number of data bits of the input image data RGB to represent the high gray level OD image data OD_Data and the low gray level OD image data OD_Data. As in the embodiment, when the input image data (RGB) is 8 bits, the maximum size of the OD image data OD_Data may be set to be less than a value that can be expressed by 9 bits.

The gate drivers 130 and 140 sequentially output gate pulses that operate the transistors of the pixels P included in the display panel 100 in response to a gate timing control signal GDC supplied from the timing controller 110. [ The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. The gate shift register 140 may be implemented in a gate-in-panel (GIP) configuration including a combination of thin film transistors in the display panel 100.

The level shifter 130 receives the start pulse ST, the clock signal CLK, and the like from the timing controller 110. Further, the level shifter 130 is supplied with driving voltages such as a gate high voltage VGH and a gate low voltage VGL. The level shifter 130 receives the start pulse VST and the start pulse VST swinging between the gate high voltage VGH and the gate low voltage VGL in response to the start pulse VST and the clock signal CLK input from the timing controller 110, ) And the gate clock. The gate clocks output from the level shifter 130 are sequentially shifted in phase and transferred to the gate shift register 140 formed on the display panel 100.

The shift register 140 includes a plurality of stages that are connected in a dependent manner. The shift register 140 shifts the start pulse VST input from the level shifter 130 according to the gate clock to sequentially supply gate pulses to the gate lines GL.

The data driver 150 converts the OD image data OD_Data into a positive or negative analog data voltage in response to a data timing control signal from the timing controller 110. The data driver 150 supplies the data voltage Vdata to the data lines DL of the display panel 100 in synchronization with the gate pulse.

The reference voltage generator 160 outputs the reference voltages RV based on the voltages supplied from the outside. The reference voltages RV output from the reference voltage generator 160 are supplied to the resistor string of the data driver 150.

FIG. 4 is a diagram illustrating a configuration of a data driver according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating the gamma voltage generator shown in FIG. 6 is a diagram showing the voltage level of the gamma voltage outputted from the data driver. In FIG. 6, the positive (+) gamma voltage means a voltage higher than the common voltage Vcom, and the negative (-) gamma voltage means a voltage lower than the common voltage Vcom.

4 to 6, the data driver 150 includes a register unit 151, a first latch 152, a second latch 153, a digital-to-analog converter (hereinafter referred to as a DAC ) 157 and an output unit 157. [

The register unit 151 outputs a sampling signal using a source start pulse SSP and a source sampling clock SSC provided from the timing controller 110. [

The first latch 152 samples and latches the OD image data OD_Data according to the clocks sequentially supplied from the register unit 151 and simultaneously outputs the latched OD image data OD_Data. The second latch 153 latches the OD image data OD_Data provided from the first latch 152 and simultaneously outputs the latched OD image data OD_Data in response to the source output enable signal SOE.

And converts the OD image data OD_Data input from the second latch unit 153 into a gamma voltage gamma.

The output unit 157 amplifies the analog type gamma voltage gamma output from the DAC 155 during the low logic period of the source output enable signal SOE to generate the data voltage Vdata, And provides the data voltage Vdata to the data lines DL.

5, the DAC 155 includes a real tone gamma voltage generator GMA1, a high tone gamma voltage generator GMA2, and a low tone gamma voltage generator GMA3.

The resistor string 154 includes a first resistor string RS1 to a third resistor string RS3 that are connected in series with each other. Switch elements ST for receiving 9-bit OD image data OD_Data are connected in series between nodes n1 to n263 and an output terminal Vout of the resistor strings RS1, RS2 and RS3. Both ends of the resistor string 154 are connected to the low potential voltage (GND) terminal and the high potential reference voltage (Vref) terminal.

The input terminals of the DAC 155 are connected to nine control signal lines B1, B1_b, B2, B2_b, B3, B3_b, B4, B4_b, and B5 for applying a turn-on voltage in accordance with the logic signal of the OD image data OD_Data , B5_b, B6, B6_b, B7, B7_b, B8, B8_b, B9, B9_b). The first control signal line B1 applies a turn-on voltage when the first bit of the OD image data OD_Data is high logic and the first bar control signal line B1_b supplies the turn-on voltage when the first bit of the audio image data And applies a turn-on voltage when it is a logic low. The control signal lines (B1, B1_b, B2, B2_b, B3, B3_b, B4, B4_b, B5, B5_b, B6, B6_b, B7, B7_b, B8, B8_b, B9, B9_b) On voltage in accordance with the high logic or low logic of each bit of the bit line.

The first through ninth selection units SEL1, SEL2, SEL3, SEL4, SEL5, SEL6, SEL7, SEL8, and SEL9 are disposed between one node n and the output terminal Vout.

Each of the selectors SEL includes a switch element ST connected to the j-th control signal line Bj or j-th bar control signal line Bj_b, where j is a natural number of 9 or less. As a result, the j-th selection unit SELj determines the switch element ST to be turned on according to the logic signal of the j-th bit of the OD image data OD_Data.

With this structure, the 9-bit OD image data OD_Data turns on nine switch elements ST connected in series to each other so as to connect one node n and the output terminal Vout. For example, when the OD image data OD_Data is "000000000 ", the switch elements connecting the first node n1 and the output terminal Vout in series are turned on. As a result, the DAC 155 outputs a "0G" gamma voltage gamma that is divided at the first node n1. Alternatively, when the OD image data OD_Data is "100000100", the switch elements ST connecting the 262nd node n261 and the output terminal Vout in series are turned on. As a result, the DAC 155 outputs the gamma voltage gamma of "260G " divided at the 261st node n261.

The DAC 155 may further include an OP amp that receives and amplifies the voltage of the output terminal Vout.

In this way, the high gray-scale gamma voltage generating section GMA2 and the low gray-scale gamma voltage generating section GMA3 are controlled by a voltage (voltage) divided by each node n of the first resistor string RS1 to the third resistor string RS3 .

The thread gradation gamma voltage generator GMA1 converts the OD image data OD_Data belonging to the range of "0" to "255" into the gamma voltage gamma. For example, the thread gradation gamma voltage generating section GMA1 generates "0G" when the OD image data OD_Data is "0" and generates "255G" when the OD image data OD_Data is "255" do. "0G" is a gamma voltage for expressing the lowest gradation of input image data (RGB), and "255G" is a gamma voltage for expressing the highest gradation of input image data (RGB).

The high gray-scale gamma voltage generator GMA2 converts the high gray-scale OD image data OD_Data into a gamma voltage. For example, the high gray-scale gamma voltage generator GMA2 generates "256G" when the OD image data OD_Data is "256" and generates "260G" when the OD image data OD_Data is "260" do. Each of the high gamma gamma voltages has a voltage level higher than the 256th gamma voltage gamma.

The low-gradation gamma voltage generating section GMA3 generates low-gradation gamma voltages respectively corresponding to the low gradation OD image data OD_Data. The low-gradation gamma voltage generator GMA3 generates a gamma voltage of the opposite polarity when the OD image data OD_Data is low-gradation OD image data OD_Data. For example, the low-gradation gamma voltage generator GMA3 generates a negative "0G" when the OD image data OD_Data is "261 ". Similarly, although not shown in the drawing, the low-gradation gamma voltage generating section GMA3 generates negative "1G" when the OD image data OD_Data is "262 ".

7 and 8 are views for explaining overdriving driving according to an embodiment of the present invention.

7 is a diagram showing a data voltage charged into a pixel when i-th field data Field [i-1] changes from "0" to i-th field data Field [i] to be. 7 is a graph showing a voltage charged in a pixel to which a data voltage corresponding to "192G" is applied, and a graph in Fig. 7 is a graph showing a voltage charged in a pixel to which a data voltage corresponding to & FIG.

When the data driver 150 applies the data voltage Vdata corresponding to the input video data "192" without overdriving driving, the voltage corresponding to 192 G is charged to the pixel P . On the other hand, according to the over-driving driving method, the OD generator 200 generates the OD image data OD_Data having the value of 211 on the basis of the look-up table 12, Lt; / RTI > As a result, the data charging speed is improved, and the gray scale display corresponding to " 192G "

8 is a diagram showing overdriving driving when the [i-1] field data Field [i-1] changes from "0" to the ith field data Field [i] to "255". 8 is a graph showing a voltage charged in a pixel to which a data voltage corresponding to " 255G "is applied, and a graph showing a voltage charged in a pixel to which a data voltage corresponding to " 260G " FIG.

When the [i-1] field data field [i-1] changes from "0" to the i-th field data field [i] to "255", the OD generator 200 of the present invention changes the look- Based on the table 12, OD image data OD_Data having a value of " 260 ". The data driver 150 generates a gamma voltage of " 260G " corresponding to the OD image data OD_Data of " 260 ". Since the data driver 150 can generate the gamma voltage corresponding to the high gradation OD image data OD_Data that is out of the size of the input image data RGB, the data driver 150 can perform the over driving operation for the high gradation image data.

This will be described with reference to the comparative example shown in FIG. In the conventional overdriving driving, the size of the maximum audio image data does not exceed the range of the input image data (RGB). This is because the maximum value of the gamma voltage output from the DAC of the data driver corresponds to the " 255 " gradation. As a result, in the comparative example, even when the input video data (RGB) is changed to the maximum gradation value "255" in the low gradation, the data voltage corresponding to the "255" value can not be output. As a result, overdriving was not possible at high gradations.

 On the other hand, the OD generator 200 according to the present invention generates OD image data OD_Data that deviates from the input image data RGB. Since the data driver 150 can generate the gamma voltage having a higher voltage than the gamma voltage corresponding to the maximum gradation value of the input image data RGB, the overdriving effect can be obtained even in the high gradation region.

10 is a diagram showing overdriving driving in a low gradation region. 10 is a graph showing a data voltage output from the data driver 150 using a gamma voltage of 262G, and a graph of (2) shows a voltage change of a pixel to which a data voltage as shown in Fig.

10, the overdriving driving is performed when the i-th field data Field [i-1] changes from "255" to the i-th field data Field [i] The following is an example.

The OD generator 200 outputs the OD image data OD_Data as the value 262 based on the lookup table 12 when the field data is changed from "255" to "0". The DAC 155 of the data driver 150 outputs the negative polarity " 0G " as the gamma voltage corresponding to the OD image data OD_Data of the " 262 " value. As a result, the data driver 150 can quickly discharge the voltage charged in the pixel so that the voltage of the pixel can fall to a voltage level corresponding to the gray level of "0G" in one horizontal period (1H).

Fig. 11 shows a comparative example in comparison with Fig. 10, which shows a change in voltage when overdriving driving is not performed at a low gray level. In FIG. 11, a graph (a) is a diagram showing a data voltage output from the data driver 150 using a gamma voltage of 0G, and a graph (2) shows a voltage change Fig. As shown in Fig. 11, according to the general driving, since the voltage of the pixel changes slowly due to the delay phenomenon, the gradation corresponding to " 0G " can not be displayed in one horizontal period (1H). As a result, the pixels can not display a black image in a specific pattern, and gray color may be displayed.

On the other hand, according to the present invention, even when the gradation value changes from a high gradation to a low gradation as shown in FIG. 10, the gradation change of the pixel can be accelerated.

12 to 15 are diagrams for explaining the effect of the low gradation overdriving according to the present invention. Figs. 12 and 14 show video display of (k-1) th (k is a natural number) frame and kth frame, respectively.

Figure 12 shows a pixel array comprising red pixels, green pixels, blue pixels and white pixels. In the display panel shown in Figs. 12 and 14, the data lines alternately apply the data voltages to the pixels arranged in the adjacent columns.

FIG. 12 shows a state in which each pixel displays a high gray scale, and FIG. 13 shows the timing of a data voltage output from the second and third data lines DL2 and DL3 to display the gray scale shown in FIG. 12 Fig.

Fig. 14 shows a state in which the red pixel maintains a high gradation while the blue pixel, the green pixel, and the white pixel display an image with a low gradation in the state as shown in Fig. Fig. 15 is a diagram showing timings of data voltages output from the second and third data lines DL2 and DL3 in order to display the image shown in Fig.

As shown in Figs. 12 to 14, the first pixel P1 displays a white color in the (k-1) th frame and displays black in the kth frame. As shown in FIGS. 12 and 13, the first pixel P1 receives a high gray scale voltage of negative polarity from the third data line DL3 in the (k-1) th frame. As shown in FIGS. 14 and 15, the first pixel P1 receives a positive (+) low gradation voltage from the third data line DL3 in the kth frame. Unless the overdriving driving according to the present invention is applied, the first pixel must be supplied with a negative (-) voltage in the kth frame. The present invention outputs the data voltage based on the low gradation gamma voltage to the first pixel P1 which changes from the high gradation voltage to the low gradation voltage so that the first pixel P1 can display the black image in a short time .

As described above, the display apparatus according to the present invention generates OD image data (OD_Data) by adding or subtracting a compensation value to input image data (RGB). The compensation value may be set to a different value for each horizontal line to compensate for the delay due to the length of the data line.

16 is a schematic diagram showing that the same data voltage is delayed for each horizontal line. FIG. 16 shows an embodiment in which the data voltage output from the data driver 150 is applied to the nth horizontal line HL [n] via the first horizontal line 1HL. As shown in FIG. 16, the delay of the data voltage becomes greater as the horizontal line HL located at the rear end from the data driver 150 is.

Accordingly, the present invention generates OD image data OD_Data by adding or subtracting a larger compensation value to the horizontal lines HL located at the rear end.

For example, when the maximum compensation value is Cmax, the compensation value Ci of the i-th horizontal line can be generated based on the following Equation (1).

[Equation 1]

(Cmax-255)Ci = (i / m)

(Cmax-255)

Here, m denotes the total number of horizontal lines, and 255 denotes the maximum gradation value of the input image data.

The OD image data OD_Data may be generated by adding or subtracting the compensation value generated based on the equation (1) to the i-th field data Field [i]. As a result, the lookup table 12 can be generated by the number of horizontal lines HL.

As a result, the OD generator 200 of the present invention can generate the OD image data OD_Data compensating for the delay of the data line DL, so that the gradation between the lines is unbalanced due to the delay of the data line DL It is possible to improve the phenomenon that the voltage is approximately charged in the pixel.

In the present specification, the OD generation unit 200 has been described focusing on an embodiment in which OD image data (RGB) is generated by comparing input image data RGB in units of frames. However, as already mentioned, the field memory 11 can store input image data RGB on a line-by-line basis. The OD generator 200 may compare input image data RGB on a line-by-line basis and generate OD image data OD_Data. When the OD generator 200 generates the OD image data OD_Data on a line-by-line basis, the delay of the data voltage Vdata between the lines can be improved.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
150: Data driver 130, 140: Gate driver
160: Reference voltage generator 200: OD generator
13: selector

Claims (8)

A display panel in which a pixel is located in an area where a data line and a gate line intersect;
A timing controller for generating audi image data (OD image data) based on a variation amount of the input image data in a range of 0 to k gradation represented by the number of input data bits; And
And a data driver for converting the audio data into a gamma voltage to generate a data voltage,
The data driver may include:
A first gamma voltage generator for generating a gamma voltage in a range of 0 to k (k is a natural number) gradation range;
a second gamma voltage generator for generating a gamma voltage in a range of (k + j) (where j is a natural number) gradation range; And
And a third gamma voltage generator for generating a gamma voltage lower than the 0-th gray-scale. The method according to claim 1,
The timing controller
A field memory for storing image data of a previous field;
A lookup table that stores in advance the audio data in which the compensation value is added or subtracted based on the change amount of the current field input image data in comparison with the input image data of the previous field; And
And a selector for receiving the current field input image data and selecting and outputting the corresponding audio image data. 3. The method of claim 2,
The field memory of the look-
Wherein the display panel stores the input image data in a line unit or the input image data in a frame period unit. 3. The method of claim 2,
The audio-
Wherein the data voltage written to the pixels generates the audio image data in which a larger compensation value is added or subtracted, as the position is farther from the data driver. The method according to claim 1,
The audio-
And generates the (N + 1) -bit audio data when the input image data is N bits. 6. The method of claim 5,
The data driver includes a resistor string having first to (k + j) resistors connected in series to each other, wherein the number of resistors included in the resistor string is "

&Quot;
The first gamma voltage generator outputs the " 0G " to " kG " gamma voltages respectively divided from the nodes between the first resistor and the k resistors,
The second gamma voltage generator generates gamma voltages ranging from "(k + 1) G" to "(k + j) G" gamma voltages each divided from the nodes between the (k + A display device for outputting a voltage. The method according to claim 6,
Wherein the data driver includes a resistance string composed of the first resistor through (k + 1) (1 is a natural number greater than k) connected in series, and the number of resistors included in the resistor string is "

&Quot;
The third gamma voltage generator
Outputting a voltage divided from nodes between the (k + j + 1) th resistors to the (k + 1) th resistors as a low gradation gamma voltage,
Wherein the low-gradation gamma voltage is set to a negative gamma voltage of the " 0G " gamma voltage that generates the first gamma voltage. 8. The method of claim 7,
The data driver
And a selector for forming a current path connecting each of the nodes of the resistor string and an output terminal of the gamma voltage,
Wherein the selection unit corresponding to each of the nodes includes (N + 1) switch elements responding to high logic or low logic of each of the (N + 1) bits of the audio image data.

Images