KR102570416B1 - DAC and Source IC having the Same and Display Device having the Same - Google Patents

Abstract

The display device of the present invention includes a display panel, a data mapping unit and a data driving unit. The display panel includes pixels positioned in an area where a data line and a gate line intersect. The data mapping unit receives image data, expands the number of bits of the image data, and generates gamma image data having the extended number of bits. The data driver converts gamma image data into gamma voltages to generate data voltages, and outputs the data voltages to data lines. The data driver includes an operational amplifier, a parallel resistor, a feedback resistor, and switch elements. An operational amplifier amplifies the input voltage. The parallel resistance unit consists of a plurality of resistors connected in parallel between the inverting input terminal and the high potential voltage input terminal of the operational amplifier. A feedback resistor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier. The switch elements include switch elements that select a resistance value connected to the inverting input terminal of the operational amplifier in response to gamma image data.

Description

Digital analog change unit and data drive unit and display device including the same {DAC and Source IC having the Same and Display Device having the Same}

The present invention relates to a digital-to-analog converter and a data driver and display device including the same.

Flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Organic Light Emitting Diode Device (OLED). ), etc.

Such a display device includes a display panel for displaying an image, and a driving circuit for supplying signals and power to the display panel. The driving circuit includes a gate driver for supplying a gate voltage to each pixel region of the display panel and a data voltage for supplying It includes a data driver.

The data driver receives digital image data, generates an analog data voltage, and outputs it to the data line. The digital-to-analog conversion unit that converts image data into data voltage includes a resistance string and a plurality of transistors that determine a voltage value by selecting each node of the resistance strings. Since the digital-to-analog conversion unit requires a large number of resistors and transistors, it occupies an area equivalent to half of the data driver unit.

The present invention relates to a digital-to-analog conversion unit capable of reducing resistance and switching elements, and a data driver and display device including the same.

The display device of the present invention includes a display panel, a data mapping unit and a data driving unit. The display panel includes pixels positioned in an area where a data line and a gate line intersect. The data mapping unit receives image data, expands the number of bits of the image data, and generates gamma image data having the extended number of bits. The data driver converts gamma image data into gamma voltages to generate data voltages, and outputs the data voltages to data lines. The data driver includes an operational amplifier, a parallel resistor, a feedback resistor, and switch elements. An operational amplifier amplifies the input voltage. The parallel resistance unit consists of a plurality of resistors connected in parallel between the inverting input terminal and the high potential voltage input terminal of the operational amplifier. A feedback resistor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier. The switch elements include switch elements that select a resistance value connected to the inverting input terminal of the operational amplifier in response to gamma image data.

Since the digital-to-analog conversion unit of the present invention removes the resistance string and generates data voltage using only switch elements corresponding to the number of bits of received data, the number of resistors and transistors can be greatly reduced. As a result, the size of the data driver including the digital-to-analog converter can be reduced.

In addition, since the digital-to-analog conversion unit does not require a gamma reference voltage applied to each node of the resistance string, a circuit required to generate the gamma reference voltage can be eliminated, and signal wiring for supplying the gamma reference voltage is not required. I never do that. As a result, the size of the entire driving circuit can be reduced, and the array structure in which signal wires are disposed can be simplified.

In addition, since the present invention expands the number of bits of image data and generates a data voltage based on this, a nonlinear gamma characteristic curve can be expressed.

1 is a view showing a display device according to the present invention.
2 is a diagram illustrating a lookup table of a data mapping unit.
3 is a diagram explaining a method of matching gamma image data in a lookup table.
4 is a diagram showing the configuration of a data driver according to the present invention.
FIG. 5 is a diagram illustrating the digital-to-analog converter shown in FIG. 4 .
6 is a diagram showing an example of gamma image data.
7 is a diagram illustrating a digital-to-analog conversion unit according to a comparative example.
8 and 9 are diagrams illustrating a data driver according to a comparative example.
10 is a diagram illustrating a data driver according to another embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In this specification, embodiments of the invention are described focusing on a liquid crystal display device, but the present invention can be applied to other display devices such as an organic light emitting diode display device.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1 , the display device of the present invention includes a display panel 100, a timing controller 110, a level shifter 130, a shift register 140, a data driver 150, a reference voltage generator 160, and the like. includes

The display panel 100 includes a pixel array in which pixels arranged in a matrix form are formed to display gray levels based on input image data. The pixel array includes a TFT array formed on the lower substrate, a color filter array formed on the upper substrate, and liquid crystal cells Clc formed between the lower substrate and the upper substrate. The TFT array includes a data line DL, a gate line GL crossing the data line DL, TFTs formed at each intersection of the data line DL and the gate line GL, and a pixel electrode 1 connected to the TFT. ), a storage capacitor Cst, and the like are formed. A color filter array including a black matrix and color filters is formed in the color filter array. The common electrode 2 may be formed on a lower substrate or an upper substrate. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 supplied with the data voltage and the common electrode 2 supplied with the common voltage Vcom. Polarizers having optical axes orthogonal to each other are attached to the upper substrate and the lower substrate of the display panel 100, and an alignment layer for setting a pretilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer. A spacer is disposed between the upper substrate and the lower substrate of the display panel 100 to maintain a cell gap of the liquid crystal layer.

The timing controller 110 receives video data (RGB) from an external host and transmits a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (CLK). Receives a timing signal. The timing controller 110 controls the data timing control signal DDC for controlling the operation timing of the data driver 150 and the operation timing of the gate drivers 130 and 140 using the timing signals Vsync, Hsync, DE, and CLK. A gate timing control signal (GDC) for controlling is generated.

The data mapping unit 200 of the timing controller 110 extends the number of bits of image data (RGB) received from the host and converts them into gamma image data. In general, image data (RGB) received from the host is 8-bit digital data for expressing 256 gray levels. The data mapping unit 200 extends the number of bits of the image data RGB to 8 bits or more, for example, 10 bits. To this end, the data mapping unit 200 includes a lookup table (LUT) including 10-bit gamma image data (GDATA).

The lookup table (LUT) stores 10-bit gamma image data (GDATA) corresponding to each of the 8-bit image data (RGB). The data mapping unit 200 outputs 10-bit gamma image data (GDATA) according to the input image data (RGB).

The 8-bit image data (RGB) is for expressing 256 levels of gradation. Since human vision responds nonlinearly to brightness, it is desirable to set the size of grayscale between stages to change nonlinearly.

The data driver 150, which will be described later, generates a gamma voltage proportional to the gamma image data GDATA. Accordingly, when 256 levels of gray levels are expressed based on 8-bit image data (RGB), the gamma voltage is linearly expressed because the gray level difference between each level is the same. That is, it is impossible to express the luminance corresponding to the 2.2 gamma curve ideal for the viewer's visibility.

The data mapping unit 200 of the present invention selects 256 gamma image data (GDATA) within 10 bits, that is, 1024 levels, to express 256 levels of grayscale. The minimum value of the gamma image data (GDATA) is “0000000000” and the maximum value is “1111111111”. A difference in the size of the gamma image data GDATA is proportional to the size of the grayscale value. Intervals between a total of 256 first gamma image data (GDATA) to 255th gamma image data (GDATA) are not constant. Accordingly, the gray level difference between each gamma image data GDATA is different.

A method of mapping 256 pieces of gamma image data (GDATA) corresponding to 256 pieces of image data (RGB) in the number of 1024 cases by the data mapping unit 200 according to the present invention is as follows.

3 is a diagram illustrating a method of selecting gamma image data (GDATA) from 10-bit data.

Referring to FIG. 3 , a first graph L1 is a diagram illustrating a luminance change for 10-bit data. When the luminance is proportional to the data, the gamma voltage is expressed linearly as shown in the first graph L1. A second graph L2 represents a non-linear gamma curve based on human visual perception characteristics.

Since the viewer reacts sensitively to small luminance differences in the low grayscale area A1, the difference between the gamma image data GDATA is set small in the low grayscale area A11. For example, the gamma image data (GDATA) of 0G is set to “0000000000” and the gamma image data (GDATA) of 1G is set to “0000000001” so that the difference between the gamma image data (GDATA) of one step becomes “1”. .

Since the viewer is relatively insensitive to the luminance difference in the high gradation area A2, the difference between the gamma image data GDATA is set large in the high gradation area A2. For example, if the gamma image data (GDATA) of 126G is set to “0010000000” and the gamma image data (GDATA) of 127G is set to “0010000011”, the difference between the gamma image data (GDATA) of one step is “3”. Let it be.

In this way, the data mapping unit 200 according to the present invention extends the number of bits of the image data RGB, and among the data with the increased number of cases, the gamma image data GDATA corresponding to the number of bits of the image data RGB. print out As a result, even if the gamma voltage VGamma proportional to the size of the gamma image data GDATA is generated, a nonlinear gamma curve for expressing 256 gray levels can be implemented. In addition, although this specification focuses on an embodiment in which 8-bit video data is expanded to 10 bits, it is also possible to use an embodiment in which video data is expanded to 9 bits or 10 bits or more.

The gate drivers 130 and 140 sequentially output gate pulses for operating the transistors of the pixels P included in the display panel 100 in response to the gate timing control signal GDC provided from the timing controller 110. The gate drivers 130 and 140 include a level shifter 130 and a shift register 140 . The gate shift register 140 may be implemented in the form of a gate-in-panel (Gate II Paiel, hereinafter referred to as GIP) formed of a combination of thin film transistors in the display panel 100 .

The level shifter 130 receives a start pulse ST, a clock signal CLK, and the like from the timing controller 110 . In addition, the level shifter 130 is supplied with driving voltages such as a gate high voltage (VGH) and a gate low voltage (VGL). The level shifter 130 has a start pulse VST swinging between a gate high voltage VGH and a gate low voltage VGL in response to a start pulse VST and a clock signal CLK input from the timing controller 110. ) and gate clock output. The phase of the gate clock output from the level shifter 130 is sequentially shifted and transmitted to the gate shift register 140 formed in the display panel 100 .

The shift register 140 includes a number of cascadingly connected stages. The shift register 140 shifts the start pulse VST input from the level shifter 130 according to the gate clock and sequentially supplies the gate pulses to the gate lines GL.

The data driver 150 converts the gamma image data GDATA into a positive or negative analog data voltage in response to a data timing control signal from the timing controller 110 . The data driver 150 supplies the data voltage Vdata to the data lines DL of the display panel 100 in synchronization with the gate pulse.

4 is a diagram showing the configuration of a data driver according to an embodiment of the present invention, and FIG. 5 is a diagram showing the digital-to-analog converter shown in FIG. 4 .

4 and 5, the data driver 150 includes a register unit 151, a first latch 152, a second latch 153, a digital-to-analog converter (hereinafter referred to as DAC). ) 157 and an output unit 157.

The register unit 151 outputs a sampling signal using a source start pulse (SSP) and a source sampling clock (SSC) provided from the timing controller 110 .

The first latch 152 samples and latches the gamma image data GDATA according to the clock sequentially supplied from the register unit 151, and simultaneously outputs the latched gamma image data GDATA. The second latch 153 latches the gamma image data GDATA provided from the first latch 152 and simultaneously outputs the latched gamma image data GDATA in response to the source output enable signal SOE.

The digital-to-analog conversion unit 155 (hereinafter referred to as DAC) converts the gamma image data GDATA input from the second latch unit 153 into a data voltage Vdata.

The output unit 157 amplifies the analog data voltage Vdata output from the DAC 155 and provides it to the data lines DL during the low logic period of the source output enable signal SOE. .

As shown in FIG. 5 , the DAC 155 includes a variable resistance unit 250 and an operational amplifier 255 .

The operational amplifier 255 amplifies the input voltage, and for this, a feedback resistor Rf is connected between the inverting input terminal (-) of the operational amplifier 255 and the output terminal of the operational amplifier.

Both ends of the variable resistance unit 250 are connected to a low potential voltage (GND) terminal and a high potential reference voltage (Vref) terminal.

The variable resistance unit 250 includes a parallel resistance unit 251 and a switch unit 253 positioned between the first node n1 and the second node n2. The parallel resistor unit 251 includes a plurality of resistors Rf, R1, R2, R3...R10 connected in parallel with each other. The first node n1 is connected to the high potential voltage VDD, and the second node n2 is connected to the inverting input terminal (-) of the operational amplifier 255.

The first to tenth switch elements T1 to T10 each operate according to a 10-bit logic signal of the gamma image data GDATA.

6 is a diagram illustrating each bit data of gamma image data GDATA.

Referring to FIG. 6 , the first switch element T1 is turned on when the first bit data b1 is a high logic level, and the second switch element T2 is turned on when the second bit data b2 is a high logic level. turns on when Similarly, the ith (i is a natural number less than or equal to 10) switch element Ti is turned on when the ith bit data bi is a high logic level.

As a result, the first switch element T1 forms a current path between the first node n1 and the second node n2 via the first resistor R1 when the first bit bi is a high logic level. do. The second switch element T2 forms a current path between the first node n1 and the second node n2 via the second resistor R2 when the second bit b2 has a high logic level. Similarly, when the 10th bit b10 of the i-th switch element Ti has a high logic level, a current path is formed between the first node n1 and the second node n2 via the 10th resistor R10.

A current path between the first node n1 and the second node n2 is selected by the switch elements T1 to T10, and the parallel resistors between the first node n1 and the second node n2 The total resistance value is determined.

The operational amplifier 255 receives the high potential voltage VDD, which is voltage dropped by the resistance value of the variable resistance unit 250 of the first node n1, through an inverting input terminal (-), amplifies it, and amplifies it to a gamma voltage ( VGamma) is output.

A relational expression of the gamma voltage VGamma output from the operational amplifier 255 according to the resistance value of the variable resistor unit 250 is as shown in [Equation 1] below.

[Equation 1]

VDDVgamma = VDD+VR

VDD

In [Equation 1], VR means a variable resistance value of the variable resistance unit 250. Accordingly, the variable resistance value VR varies depending on the switch elements T selected by the gamma image data GDATA.

For example, when all of the first to tenth switch elements T1 to T10 are turned on, the variable resistance value VR becomes "Rf/R1+Rf/R2+...+Rf/R10", and the first switch When only the element T1 is turned on, the variable resistance value VR becomes “Rf/R1”.

Since the gamma image data GDATA is set to 256 in total, the number of combinations of switch element units 253 turned on by the gamma image data GDATA is 256 in total. As a result, the gamma voltage (VGamma) has a total of 256 steps.

The DAC 155 according to the present invention does not use a resistor string and outputs a gamma voltage VGamma according to the variable resistance value of the variable resistor unit 250 . As a result, the DAC 155 can reduce the number of resistors required for the resistor string and reduce the number of transistors for distributing the voltage of the resistor string.

This will be explained in preparation for a comparative example.

7 is a diagram illustrating a DAC of a data driver according to a comparative example.

The data driver according to the comparison example includes a resistor string RS and a plurality of transistors Tsw. The transistors Tsw are turned on according to a high logic signal or a low logic signal of the image data, respectively, and select a current path connecting the resistance string TS and the op amp. The resistance string RS according to the comparative example requires 256 resistors to express 255G of 8 bits. In addition, the transistors Tsw require a total of 510 transistors Tsw in order to receive 8-bit image data RGB and select a current path.

In contrast, since the variable resistance unit 250 of the DAC 155 according to the present invention is composed of the reference resistance Rf and the number of resistors corresponding to the number of bits of the gamma image data GDATA, a 10-bit gamma image Based on the data (GDATA), only 11 resistors are required. In addition, since the DAC 155 according to the present invention requires only the switch elements T1 to T10 corresponding to the number of bits in order to select the variable resistance value VR of the variable resistance unit 250, 10 It requires two switch elements. That is, since the number of resistors and the number of transistors of the DAC 155 according to the present invention can be significantly reduced, the overall size of the data driver can be greatly reduced and manufacturing costs can be reduced.

The display device according to the present invention generates a gamma voltage (VGamma) based on gamma image data (GDATA) generated by the data mapping unit 200 . That is, in the comparison example shown in FIG. 7, the gamma reference voltage (GMA) must be applied to a specific node in the resistor string (RS), and the gamma reference voltage generator (GMA-IC) for generating the gamma reference voltage (GMA) need On the other hand, since the DAC according to the present invention does not require a gamma reference voltage generator (GMA-IC), the size of the circuit can be reduced. In addition, since a wiring for connecting the gamma reference voltage generator (GMA-IC) and the DAC can be eliminated, the array structure of the display panel 100 can be simplified.

In particular, since the process of setting the gamma voltage (VGamma) for each R, G, and B color is very simple, it is easy to apply the independent gamma method. A comparative example and the data driving unit of the display device to which the DAC of the present invention is applied are as follows.

8 is a diagram illustrating a data driver according to a first comparison example, and FIG. 9 is a diagram illustrating a data driver according to a second comparison example.

Referring to FIG. 8 , the data driver unit according to the first comparison example “P-DAC1” and “P-DAC2” outputs positive (+) data voltages and “P-DAC2” outputs negative (-) data voltages. N-DAC1" and "N-DAC2".

The R video data of the latch unit LAT is supplied to "P-DAC1" or "N-DAC1" by the first multiplexer MUX1. The G video data of the latch unit LAT is supplied to "N-DAC1" or "P-DAC2" by the first multiplexer MUX1, and the B video data of the latch unit LAT is supplied to the first multiplexer MUX1. supplied as "P-DAC2" or "N-DAC2" by

Each of the data voltages generated by "P-DAC1", "N-DAC1", "P-DAC2" and "N-DAC2" are stored in the first to third buffers BUF1 to BUF3 by the second multiplexer MUX2. applied to any one of

In the first comparison example, the number of DACs can be reduced by generating a positive (+) data voltage and a negative (-) data voltage by sharing a DAC between adjacent channels. However, in the first comparison example, the gamma reference voltage generation unit and the gamma reference voltage for applying the gamma reference voltage (GMA) to each of "P-DAC1", "N-DAC1", "P-DAC2" and "N-DAC2" A voltage line (GMA_L) is required.

Referring to FIG. 9 , a second comparison example shows a data driver for using an independent gamma method. The data driver according to the second comparison example "P-DAC1", "P-DAC2", and "P-DAC3" outputting positive (+) data voltages and "P-DAC3" outputting negative (-) data voltages. N-DAC1", "N-DAC2" and "N-DAC3".

The R video data of the latch unit LAT is supplied to "P-DAC1" or "N-DAC1" by the first multiplexer MUX1. The G video data of the latch unit LAT is supplied to "P-DAC2" or "N-DAC2" by the first multiplexer MUX1, and the B video data of the latch unit LAT is supplied to the first multiplexer MUX1. supplied as “P-DAC3” or “N-DAC3” by

Each of the data voltages generated in "P-DAC1 to 3" and "N-DAC1 to 3" is applied to any one of the first to third buffers BUF1 to BUF3 by the second multiplexer MUX2.

Independent gamma is known as a method of setting different gamma values for each color in order to correct R, G, and B colors. In order to use the independent gamma method, since the gamma reference voltages (R GMA, G GMA, B GMA) are different for each R, G, and B color, A gamma reference voltage generator must be added separately. In addition, gamma reference voltage lines (GMA_L1, GMA_L2, GMA_L3) are required to apply the respective gamma reference voltages (R GMA, G GMA, B GMA).

In addition, since the gamma reference voltage is different for each color in the independent gamma method, a DAC must be separated for each channel. Therefore, in the independent gamma method, a structure in which DACs of adjacent channels are shared cannot be used as shown in FIG. 8 .

10 is a diagram showing a data mapping unit and a data driving unit according to the present invention.

Referring to FIG. 10 , the data mapping unit 200 includes a first lookup table R-LUT for generating R gamma image data GDATA and a second lookup table for generating G gamma image data GDATA ( G-LUT) and a third lookup table (B-LUT) for generating B gamma image data (GDATA). The first to third lookup tables (R-LUT, G-LUT, B-LUT) set the gradation size of the gamma image data (GDATA) differently for each color, so that the same effect as the independent gamma method can be obtained. .

Each gamma image data GDATA is transferred to the latch unit LAT similar to that described in FIG. 4 .

The R gamma image data GDATA of the latch unit LAT is supplied to "P-DAC1" or "N-DAC1" by the first multiplexer MUX1. The G gamma image data GDATA of the latch unit LAT is supplied to “N-DAC1” or “P-DAC2” by the first multiplexer MUX1, and the B gamma image data GDATA of the latch unit LAT is supplied to "P-DAC2" or "N-DAC2" by the first multiplexer (MUX1).

"P-DAC1" generates positive R gamma voltage based on R gamma image data. "N-DAC1" generates negative R gamma voltage based on R gamma image data or generates negative G gamma voltage based on G gamma image data. "P-DAC2" generates positive G gamma voltage based on G gamma image data or generates positive B gamma voltage based on B gamma image data. "N-DAC2" generates negative B gamma voltage based on B gamma image data. Each of the gamma voltages generated by “P-DAC1”, “N-DAC1”, “P-DAC2” and “N-DAC2” is transferred to the first to third buffers BUF1 to BUF3 by the second multiplexer MUX2. applied to any one of

As such, since the present invention does not require the gamma reference voltage to generate the gamma voltage, the size of the overall driving circuit can be reduced by eliminating the circuit for generating the gamma reference voltage. In addition, the gamma reference voltage line shown in FIGS. 8 and 9 can be reduced.

In addition, since the present invention does not use a gamma reference voltage, as shown in FIG. 8, the number of DACs can be reduced by sharing “N-DAC1” and “P-DAC2” between adjacent channels.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: timing controller
130: level shifter 140: shift register
150: data driving unit 200: data mapping unit

Claims (14)

a display panel in which a pixel is located in an area where a data line and a gate line intersect;
a data mapping unit that receives image data, expands the number of bits of the image data, and generates R gamma image data, G gamma image data, and B gamma image data having the extended number of bits; and
a digital-to-analog conversion unit converting gamma image data into gamma voltages to generate data voltages, and a data driver outputting the data voltages to the data lines;
The digital-to-analog converter
a first P-DAC generating a positive R gamma voltage based on the R gamma image data;
a first N-DAC generating a negative R gamma voltage based on the R gamma image data or a negative G gamma voltage based on the G gamma image data;
a second P-DAC generating a positive polarity G gamma voltage based on the G gamma image data or generating a positive polarity B gamma voltage based on the B gamma image data;
a second N-DAC generating a negative B gamma voltage based on the B gamma image data;
Each of the first P-DAC, the first N-DAC, the second P-DAC, and the second N-DAC,
an operational amplifier that amplifies the input voltage;
a parallel resistance unit comprising a plurality of resistors connected in parallel between an inverting input terminal and a high potential voltage input terminal of the operational amplifier;
a feedback resistor connected between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier; and
and switch elements configured to select a resistance value connected to an inverting input terminal of the operational amplifier in response to the gamma image data. According to claim 1,
The data mapping unit
Receiving the image data of n (n is a natural number) bit, and having ^{(n + k) bits matching the image data among 2 (n + k)} (k is a natural number) (n + k) bit data A display device generating the gamma image data by extending the number of bits of the image data using a lookup table storing 2 ⁿ pieces of data. According to claim 2,
The parallel resistor unit includes a reference resistor and first to (n+k)th resistors. According to claim 3,
The switch elements are
And first to (n + k)th switch elements disposed between the high potential voltage input terminal and the inverting input terminal of the operational amplifier,
The jth (j is a natural number less than or equal to 'n+k') switch element is connected in series with the jth (j is a natural number less than or equal to 'n+k') resistor. According to claim 4,
The j-th switch element is switched according to the logical value of the j-th bit of the gamma image data. According to claim 2,
Sizes of the gamma image data are not set to be the same, and the digital-to-analog converter outputs the gamma voltage proportional to the size of the gamma image data, so that the gamma voltage is expressed as a nonlinear characteristic curve. According to claim 2,
The lookup table is
a first lookup table matching the R image data with the R gamma image data;
a second lookup table matching G image data with the G gamma image data; and
A display device comprising a third lookup table matching B image data with the B gamma image data. delete a latch unit that receives, samples, and latches n-bit R gamma image data, G gamma image data, and B gamma image data;
a digital-to-analog conversion unit generating an analog data voltage based on the R gamma image data, the G gamma image data, and the B gamma image data received from the latch unit; and
A buffer unit for amplifying and outputting the data voltage;
The digital-to-analog converter
a first P-DAC generating a positive R gamma voltage based on the R gamma image data;
a first N-DAC generating a negative R gamma voltage based on the R gamma image data or a negative G gamma voltage based on the G gamma image data;
a second P-DAC generating a positive polarity G gamma voltage based on the G gamma image data or a positive polarity B gamma voltage based on the B gamma image data;
a second N-DAC generating a negative B gamma voltage based on the B gamma image data;
Each of the first P-DAC, the first N-DAC, the second P-DAC, and the second N-DAC,
an operational amplifier that amplifies the input voltage;
a parallel resistance unit comprising a plurality of resistors connected in parallel between an inverting input terminal and a high potential voltage input terminal of the operational amplifier;
a feedback resistor connected between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier; and
and switch elements configured to select a resistance value connected to an inverting input terminal of the operational amplifier in response to the gamma image data. According to claim 9,
The parallel resistance unit includes a reference resistance and first to (n + k)th resistances,
The switch elements include first to nth switch elements disposed between a high potential voltage input terminal and an inverting input terminal of the operational amplifier, and the jth (j is a natural number less than or equal to n) switch element is the jth (j is n natural number below) Data driver connected in series with the resistor. According to claim 10,
wherein the j switch element is switched according to a logic value of a j-th bit of the image data. A digital-to-analog conversion unit for generating an analog data voltage based on R gamma image data, G gamma image data, and B gamma image data, comprising:
The digital-to-analog converter
a first P-DAC generating a positive R gamma voltage based on the R gamma image data;
a first N-DAC generating a negative R gamma voltage based on the R gamma image data or a negative G gamma voltage based on the G gamma image data;
a second P-DAC generating a positive polarity G gamma voltage based on the G gamma image data or a positive polarity B gamma voltage based on the B gamma image data;
a second N-DAC generating a negative B gamma voltage based on the B gamma image data;
Each of the first P-DAC, the first N-DAC, the second P-DAC, and the second N-DAC,
an operational amplifier that amplifies the input voltage;
a parallel resistance unit comprising a plurality of resistors connected in parallel between an inverting input terminal and a high potential voltage input terminal of the operational amplifier;
a feedback resistor connected between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier; and
A digital-to-analog conversion unit including switch elements that select a resistance value connected to an inverting input terminal of the operational amplifier in response to the gamma image data. According to claim 12,
The parallel resistance unit includes a reference resistance and first to (n + k)th resistances,
The switch elements include first to nth switch elements disposed between a high potential voltage input terminal and an inverting input terminal of the operational amplifier, and the jth (j is a natural number less than or equal to n) switch element is the jth (j is n The following natural number) Digital-to-analog converter connected in series with a resistor. According to claim 13,
The j switch element is a digital-to-analog conversion unit that is switched according to the logic value of the j-th bit of the data.

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