KR101211253B1 - Variable Gamma Reference Voltage Circuit and Liquid Crystal Display Using The Same - Google Patents

Abstract

The present invention relates to a gamma reference voltage variable circuit to improve the response speed of the liquid crystal.

The gamma reference voltage variable circuit includes: a voltage divider circuit connected between a high potential voltage source and a low potential voltage source to divide a high potential voltage and a low potential voltage to generate a plurality of gamma reference voltages through a plurality of output nodes; And a switch circuit connected between neighboring output nodes to vary the gamma reference voltages in response to a control signal.

Description

Variable Gamma Reference Voltage Circuit and Liquid Crystal Display Using The Same}

1 is a waveform diagram showing a change in luminance according to data in a conventional liquid crystal display.

2 is a waveform diagram showing an example of a luminance change caused by data modulation in the high speed driving method.

3 is a view showing a change in response characteristics of the liquid crystal by the high speed driving method.

4 is a diagram illustrating an example of a high speed drive device.

5 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

6 and 7 are circuit diagrams showing in detail the first embodiment of the gamma reference voltage variable circuit shown in FIG.

8 and 9 are circuit diagrams illustrating the first embodiment of the gamma reference voltage variable circuit shown in FIG. 5 in detail.

Description of the Related Art

32: data bus 33a, 33b: frame memory

34: Lookup Table 51: Timing Controller

52: gamma reference voltage variable circuit 53: data driver

54 gate driver 55 data line

56 gate line 57 liquid crystal display panel

The present invention relates to a gamma reference voltage variable circuit to improve the response speed of the liquid crystal. In addition, the present invention relates to a liquid crystal display device using the gamma reference voltage variable circuit to improve the response speed of the liquid crystal and reduce the amount of heat generated by the circuit with a minimum circuit configuration.

The liquid crystal display adjusts the light transmittance of liquid crystal cells according to a video signal to display an image.

Among the liquid crystal display devices, an active matrix type liquid crystal display device in which switching elements are formed for each liquid crystal cell is advantageous in implementing a moving picture because active control of the switching elements is possible. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used.

As can be seen in Equations 1 and 2, the liquid crystal display has a disadvantage in that the response speed is slow due to the inherent viscosity and elasticity of the liquid crystal.

(gamma)는 액정분자의 회전점도(rotational viscosity)를 각각 의미한다. Here,? R denotes a rising time when a voltage is applied to the liquid crystal, Va denotes an applied voltage, VF denotes a freeness transition voltage at which the liquid crystal molecules start tilting, d denotes a liquid crystal The cell gap of the cell is defined as

(gamma) means the rotational viscosity of the liquid crystal molecule, respectively.

Here, τf denotes a falling time at which the liquid crystal is restored to its original value due to the elastic restoring force after the voltage applied to the liquid crystal is turned off, and K denotes the elastic modulus inherent to the liquid crystal.

The liquid crystal response speed of the TN mode (Twisted Nematic mode), which has been the most commonly used liquid crystal display device, can vary depending on the physical properties of the liquid crystal material and the cell gap. 20-30 ms. The response speed of the liquid crystal is longer than one frame period (NTSC: 16.67ms). For this reason, as shown in FIG. 1, since the voltage charged in the liquid crystal cell reaches the next voltage, the motion blurring phenomenon occurs in which the screen is blurred in the video.

Referring to FIG. 1, in the conventional LCD, when the data VD changes from one level to another level due to a slow response speed, the corresponding display luminance BL does not reach the desired luminance, and thus the desired color and luminance. Will not be represented. As a result, the motion blurring phenomenon appears in the moving image, and the image quality is deteriorated due to the decrease in the contrast ratio.

In order to solve the slow response speed of the liquid crystal display, U.S. Patent No. 5,495,265 and PCT International Publication No. WO 99/05567 use a lookup table to modulate the data depending on whether or not the data is changed (hereinafter, 'high speed driving'). Has been proposed. This high speed driving method modulates data on the same principle as in FIGS. 2 and 3.

을 크게 하게 된다. 따라서, 고속 구동방법을 이용하는 액정표시장치는 액정의 늦은 응답속도를 데이터값의 변조로 보상하여 동영상에서 모션 블러링 현상을 완화시킨다. 2 and 3, the high speed driving method modulates the input data VD into preset modulation data MVD and applies the modulation data MVD to the liquid crystal cell to obtain a desired luminance MBL. This high-speed driving method uses Equation 1 based on whether or not the data changes so as to obtain a desired luminance corresponding to the luminance value of the input data within one frame period.

. Accordingly, the liquid crystal display using the high speed driving method compensates for the late response speed of the liquid crystal by modulating the data value, thereby alleviating the motion blur phenomenon in the video.

In other words, the high speed driving method compares data between the previous frame and the current frame and modulates the data of the current frame with preset modulation data if there is a change between the data. The high speed drive device in which the high speed drive method is implemented may be implemented as shown in FIG. 4.

Referring to FIG. 4, the high speed drive device includes first and second frame memories 33a for storing data from the data bus 32, and a lookup table 34 for modulating the data.

The first and second frame memories 33a and 33b alternately store data in units of frames in accordance with the pixel clock, and alternately output stored data to the modulator 34 to store previous frame data, that is, n-1 th frame data ( Fn-1) is supplied.

The lookup table 34 compares the n th frame data Fn from the data input bus 33 with the n-1 th frame data Fn-1 from the first and second frame memories 33a and 33b. Modulation data shown in Table 1 is selected as the modulation data MRGB corresponding to the comparison result. Modulated data MRGB is stored in read-only memory (ROM) in lookup table 34.

division 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 2 3 4 5 6 7 9 10 12 13 14 15 15 15 15 One 0 One 3 4 5 6 7 8 10 12 13 14 15 15 15 15 2 0 0 2 4 5 6 7 8 10 12 13 14 15 15 15 15 3 0 0 One 3 5 6 7 8 10 11 13 14 15 15 15 15 4 0 0 One 3 4 6 7 8 9 11 12 13 14 15 15 15 5 0 0 One 2 3 5 7 8 9 11 12 13 14 15 15 15 6 0 0 One 2 3 4 6 8 9 10 12 13 14 15 15 15 7 0 0 One 2 3 4 5 7 9 10 11 13 14 15 15 15 8 0 0 One 2 3 4 5 6 8 10 11 12 14 15 15 15 9 0 0 One 2 3 4 5 6 7 9 11 12 13 14 15 15 10 0 0 One 2 3 4 5 6 7 8 10 12 13 14 15 15 11 0 0 One 2 3 4 5 6 7 8 9 11 13 14 15 15 12 0 0 One 2 3 4 5 6 7 8 9 10 12 14 15 15 13 0 0 One 2 3 3 4 5 6 7 8 10 11 13 15 15 14 0 0 One 2 3 3 4 5 6 7 8 9 11 12 14 15 15 0 0 0 One 2 3 3 4 5 6 7 8 9 11 13 15

In Table 1, the leftmost column is data of the previous frame Fn-1, and the uppermost row is data of the current frame Fn.

During the nth frame period, the nth frame data Fn is stored in the first frame memory 33a and supplied to the lookup table 34 at the same pixel clock as indicated by the solid line. At the same time, the second frame memory 33b supplies the n−1 th frame data Fn−1 to the lookup table 34 during the n th frame period.

In contrast, during the n + 1 th frame period, the current n + 1 th frame data Fn + 1 is stored in the second frame memory 33b at the same time as the dotted pixel clock, and the lookup table 34 Is supplied. At the same time, the first frame memory 33b supplies the nth frame data Fn to the lookup table 34 during the n + 1th frame period.

As described above, the high speed driving device supplies data to the two frame memories 33a and 33b, the memory and memory control circuit of the lookup table, and the lookup table 34 and modulates the modulation data from the lookup table 34 as shown in FIG. It includes a timing controller (or ASIC) designed to be supplied to the liquid crystal display device, which improves the response speed of the liquid crystal display device, but makes the driving circuit of the liquid crystal display device more complicated, increases the amount of heat generated in the circuit, and It is a major factor that increases the manufacturing cost of the device.

Accordingly, an object of the present invention is to provide a gamma reference voltage variable circuit for improving the response speed of liquid crystals.

Another object of the present invention is to provide a liquid crystal display device using the gamma reference voltage variable circuit to improve the response speed of the liquid crystal and reduce the amount of heat generated by the circuit with a minimum circuit configuration.

In order to achieve the above object, the gamma reference voltage variable circuit according to the first embodiment of the present invention is connected between a high potential voltage source and a low potential voltage source to divide a high potential voltage and a low potential voltage to a plurality of output nodes. A voltage divider circuit for generating gamma reference voltages of; And a switch circuit connected between neighboring output nodes to vary the gamma reference voltages in response to a control signal.

The control signal is generated for a period of 1/2 horizontal period or less.

The output nodes include positive output nodes generating gamma reference voltages higher than a predetermined common voltage; And negative output nodes generating gamma reference voltages lower than the common voltage.

The switch circuit includes a plurality of first switch elements for selecting a positive gamma reference voltage from any one of the neighboring positive output nodes in response to the control signal of a high logic voltage; A plurality of second switch elements for selecting a positive gamma reference voltage from another one of the neighboring positive output nodes in response to the control signal of a low logic voltage; A plurality of third switch elements for selecting a negative gamma reference voltage from any one of the neighboring negative output nodes in response to the control signal of the high logic voltage; And a plurality of fourth switch elements configured to select a negative gamma reference voltage from another one of the neighboring negative output nodes in response to the low logic voltage control signal.

The gamma reference voltage variable circuit according to the second embodiment of the present invention is connected between the first high potential voltage source and the first low potential voltage source to divide the first high potential voltage and the first low potential voltage to provide a plurality of first output nodes. A first voltage divider circuit generating a plurality of first gamma reference voltages through the first voltage divider; A second divided voltage connected between the second high potential voltage source and the second low potential voltage source to divide the second high potential voltage and the second low potential voltage to generate a plurality of second gamma reference voltages through the plurality of second output nodes; Circuits; Any one of the first gamma reference voltages and the second gamma reference voltages is connected between the first output nodes of the first voltage divider circuit and the second output nodes of the second voltage divider circuit in response to a control signal. And a switch circuit for selecting.

The first output nodes include first positive output nodes generating first positive gamma reference voltages higher than a predetermined common voltage; And first negative output nodes generating first negative gamma reference voltages lower than the common voltage.

The second output nodes comprise: second positive output nodes generating second positive gamma reference voltages lower than the first positive gamma reference voltages and higher than the common voltage; And second negative output nodes generating second negative gamma reference voltages higher than the first negative gamma reference voltages and lower than the common voltage.

The switch circuit includes a plurality of first switch elements configured to select a positive gamma reference voltage from any one of the first positive output node and the second positive output node in response to the control signal having a high logic voltage. ; A plurality of second switch elements for selecting a positive gamma reference voltage from another of the first positive output node and the second positive output node in response to the control signal of a low logic voltage; A plurality of third switch elements configured to select a negative gamma reference voltage from any one of the first negative output node and the second negative output node in response to the control signal of the high logic voltage; And a plurality of fourth switch elements for selecting a negative gamma reference voltage from the other of the second negative output node and the second negative output node in response to the control signal having a low logic voltage.

A liquid crystal display device according to a first embodiment of the present invention comprises: a liquid crystal display panel in which data lines and gate lines intersect and a plurality of liquid crystal cells are disposed; A voltage divider circuit connected between a high potential voltage source and a low potential voltage source to divide a high potential voltage and a low potential voltage to generate a plurality of gamma reference voltages through a plurality of output nodes, and connected to and controlled between the neighboring output nodes. A gamma reference voltage variable circuit including a switch circuit for varying the gamma reference voltages in response to a signal; A data driver converting digital video data into an analog pixel voltage using the gamma reference voltages from the gamma reference voltage variable circuit and supplying the analog pixel voltages to the data lines; A gate driver supplying scan pulses to the gate lines; The digital video data is supplied to the data driver to generate the control signal and timing control signals required for the drivers.

A liquid crystal display device according to a second embodiment of the present invention includes a liquid crystal display panel in which data lines and gate lines intersect and a plurality of liquid crystal cells are disposed; A first divided voltage connected between the first high potential voltage source and the first low potential voltage source to divide the first high potential voltage and the first low potential voltage to generate a plurality of first gamma reference voltages through the plurality of first output nodes; A circuit connected between the second high potential voltage source and the second low potential voltage source to divide the second high potential voltage and the second low potential voltage to generate a plurality of second gamma reference voltages through the plurality of second output nodes. A second voltage divider circuit is connected between the first output nodes of the first voltage divider circuit and the second output nodes of the second voltage divider circuit so as to respond to a control signal, the first gamma reference voltages and the second gamma. A gamma reference voltage variable circuit including a switch circuit for selecting any one of the reference voltages; A data driver converting digital video data into an analog pixel voltage using the gamma reference voltages from the gamma reference voltage variable circuit and supplying the analog pixel voltages to the data lines; A gate driver for supplying scan pulses to the gate lines; And a timing controller configured to supply the digital video data to the data driver and generate the control signal and timing control signals required by the drivers.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 12.

Referring to FIG. 5, in the liquid crystal display according to the exemplary embodiment of the present invention, a liquid crystal display panel in which a data line 55 and a gate line 56 cross each other and a TFT for driving the liquid crystal cell Clc is formed at an intersection thereof. And the variable gamma reference voltages GMA1 to GMAn to the data driver 53, the gate driver 54, the timing controller 51, and the data driver 53 for driving the liquid crystal display panel 57. Is provided with a gamma reference voltage variable circuit (52).

In the liquid crystal display panel 57, liquid crystal is injected between two glass substrates, and the data lines 55 and the gate lines 56 are orthogonal to each other on the lower glass substrate. The TFT formed at the intersection of the data lines 55 and the gate lines 56 causes the liquid crystal cell Clc to supply data from the data lines 55 in response to a scan pulse from the gate line 56. do. For this purpose, the gate electrode of the TFT is connected to the gate line 56 and the source electrode is connected to the data line 55. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 57 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line 56 or may be formed between the liquid crystal cell Clc and a separate common line.

The timing controller 51 controls the gate control signal GDC and the data driver 53 to control the gate driver 54 using the vertical / horizontal synchronization signals V and H and the pixel clock CLK. The data control signal DDC and the high speed drive control signal ODC for controlling the gamma reference voltage variable circuit 52 are generated. The data control signal (DDC) includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL). do. The gate control signal GDC includes a gate shift clock (GSC), a gate output signal (GOE), a gate start pulse (GSP), and the like. The high speed drive control signal (ODC) is generated in synchronization with the gate pulse or the scan pulse for approximately 1/2 horizontal period. The high speed drive control signal (ODC) may be generated as a separate clock generated for a period of 1/2 horizontal period or less in synchronization with the gate pulse or scan pulse, or generated as a conventional clock such as a gate shift clock (GSC). Can be.

이 커진다. 따라서, 가변 감마기준전압들(GMA1~GMAn)에 의해 액정셀(Clc)의 응답특성이 향상된다. The gamma reference voltage variable circuit 52 increases the voltage of the positive gamma reference voltages for a period of 1/2 horizontal period or less in response to the high speed drive control signal (ODC), while lowering the voltage of the negative gamma reference voltages. Variable gamma reference voltages GMA1 to GMAn are generated. The variable gamma reference voltages GMA1 to GMAn increase the positive voltage applied to the liquid crystal cell Clc, whereas the negative gamma voltage applied to the liquid crystal cell Clc is lowered.

Will grow. Therefore, the response characteristic of the liquid crystal cell Clc is improved by the variable gamma reference voltages GMA1 to GMAn.

The data driver 53 stores the shift register, a register for temporarily storing the digital video data RGB from the timing controller 51, and the data for each line in response to a clock signal from the shift register. A latch for outputting data at the same time, a digital-to-analog converter for selecting analog positive / negative gamma compensation voltages obtained by the variable gamma reference voltages GMA1 to GMAn corresponding to digital data values from the latch, and positive. And a multiplexer for selecting the data line 55 to which the polarity / negative gamma compensation voltage is supplied, and an output buffer connected between the multiplexer and the data line 55. The data driver 53 receives the digital video data RGB and converts the digital video data RGB into analog positive / negative gamma compensation voltages obtained by the variable gamma reference voltages GMA1 to GMAn. The analog positive / negative gamma compensation voltage is supplied as the pixel voltage to the data lines 55 of the liquid crystal display panel 57 under the control of the timing controller 51.

The gate driver 54 shifts the shift register which sequentially generates scan pulses in response to the gate control signal GDC from the timing controller 51, and the swing width of the scan pulses to a level suitable for driving the liquid crystal cell Clc. Level shifter, output buffer, and so on. The gate driver 54 turns on the TFTs connected to the gate line 56 by supplying scan pulses to the gate line 56 so that the pixel voltage of the data, that is, the analog gamma compensation voltage, is supplied. The liquid crystal cells Clc of one horizontal line to be selected are selected. Data generated from the data driver 53 is supplied to the liquid crystal cells Clc of one horizontal line selected by being synchronized with the scan pulse.

6 and 7 are circuit diagrams showing a first embodiment of the gamma reference voltage variable circuit 52.

6 and 7, the gamma reference voltage variable circuit 52 includes voltage divider resistors R1 to R13 connected in series between a high potential common voltage source VDD and a low potential common voltage source VSS, and an output node. Switch elements nT1 to pT6 connected to the fields n1 to n12. The low potential common voltage VSS is 0V or a predetermined base voltage GND.

The divided resistors R1 to R13 may include the first divided resistor groups R1 to R6 for generating the positively variable gamma reference voltages GMA1 to GMA3 and the negative variable variable gamma reference voltages GMA4 to GMA6. It is divided into 2nd voltage division resistance group R7-R12.

The first divided resistor groups R1 to R6 divide the high potential common voltage VDD and the voltages of the sixth output node n6, so that 2n-1 (where n is a positive integer) second positive output nodes ( A gamma reference voltage for positive fast driving higher than the common voltage Vcom is generated through n1, n3, and n5, and higher than the common voltage Vcom through the 2nth positive output nodes n2, n4, and n6. Generates a positive normal gamma reference voltage.

The second voltage divider groups R7 to R12 divide the voltage of the seventh output node n7 and the low potential common voltage VSS to divide the 2n-1 (where n is a positive integer) second negative output node ( Generate negative normal gamma reference voltage lower than common voltage Vcom through n7, n9, n11 and negative polarity lower than common voltage Vcom through 2nth positive output nodes n8, n10, n12. Generates gamma reference voltage for high speed drive.

The switch elements nT1 to pT6 are connected between neighboring positive output nodes n1 to n6 to select the first switch group nT1 to pT3 to select the positive gamma reference voltages according to the fast drive control signal ODC. ) And a second switch group nT4 to pT6 connected between neighboring negative output nodes n7 to n12 to select the negative gamma reference voltages according to the high speed drive control signal ODC.

The first switch group nT1 to pT3 is used for positive fast driving from the 2n-1th positive output nodes n1, n3 and n5 in response to the high speed drive control signal ODC (H). First to third n-type MOS-FETs (nT1, nT2, nT3) for outputting the gamma reference voltage as the positive gamma reference voltages GMA1, GMA2, and GMA3, and a high-speed driving control signal (ODC) having a low logic voltage. L-1), the first to third outputting the positive normal gamma reference voltages from the 2n-th positive output nodes n2, n4, n6 as the positive gamma reference voltages GMA1, GMA2, and GMA3. p type MOS-FETs (pT1, pT2, pT3). Gate terminals of the first to third n-type MOS-FETs (nT1, nT2, nT3) are connected to the high-speed drive control signal input terminals, and sources of the first to third n-type MOS-FETs (nT1, nT2, nT3). The terminal is connected to the 2n-1 < th > positive polarity output nodes n1, n3, n5. Gate terminals of the first to third p-type MOS-FETs pT1, pT2 and pT3 are connected to the high-speed drive control signal input terminals, and sources of the first to third p-type MOS-FETs pT1, pT2 and pT3. The terminal is connected to the 2n-th positive output nodes n2, n4, n6. The drain terminals of the first to third n-type MOS-FETs (nT1, nT2, nT3) and the drain terminals of the first to third p-type MOS-FETs (pT1, pT2, and pT3) are positive gamma reference voltage output terminals. (GMA1, GMA2, GMA3).

The second switch group nT4 to pT6 have a negative normal gamma reference from the 2n−1 th negative output nodes n7, n9 and n11 in response to the high speed drive control signal ODC (L) having a low logic voltage. Fourth to sixth p-type MOS-FETs (pT4, pT5, and pT6) outputting the voltage as the negative gamma reference voltages GMA4, GMA5, and GMA6, and a high-speed high-speed drive control signal (ODC (H)). Fourth to sixth outputting the negative fast gamma reference voltages from the 2n th negative output nodes n8, n10 and n12 as the negative gamma reference voltages GMA4, GMA5 and GMA6 in response to n type MOS-FETs (nT4, nT5, nT6). Gate terminals of the fourth to sixth p-type MOS-FETs pT4, pT5, and pT6 are connected to the high-speed drive control signal input terminals, and sources of the fourth to sixth p-type MOS-FETs pT4, pT5 and pT6. The terminal is connected to the 2n-1 < th > negative polarity output nodes n7, n9, n11. Gate terminals of the fourth to sixth n-type MOS-FETs (nT4, nT5, nT6) are connected to the high-speed drive control signal input terminals, and sources of the fourth to sixth n-type MOS-FETs (nT4, nT4, nT6). The terminal is connected to the 2nth negative output nodes n8, n10, n12. The drain terminals of the fourth to sixth p-type MOS-FETs (pT4, pT5, and pT6) and the drain terminals of the fourth to sixth n-type MOS-FETs (nT4, nT5, and nT6) are connected to the negative gamma reference voltage output terminal. (GMA4, GMA5, GMA6).

The operation of the gamma reference voltage variable circuit 52 according to the first embodiment of the present invention will be described below.

When the high speed driving control signal (ODC) is generated at the high logic voltage (H) for a period of about 1/2 horizontal period or less in synchronization with the scan pulse or the gate pulse, the first to sixth n-type MOS-FETs nT1 to nT6 is turned on, while first to sixth p-type MOS-FETs pT1 to pT6 are turned off. Then, as shown in FIG. 6, the gamma reference voltages GMA1 (H), GMA2 (H), and GMA3 (H) for positive fast driving are higher than the positive normal gamma reference voltages through the positive gamma reference voltage output terminals. The data driver 53 is supplied with the negative gamma reference voltage output terminals to be relatively low (higher in absolute value) than the negative normal gamma reference voltages. ), GMA5 (L) and GMA6 (L) are supplied to the data driver 53.

When the fast driving control signal ODC is generated with the low logic voltage L, the first to sixth n-type MOS-FETs nT1 to nT6 are turned off while the first to sixth p-type MOS- are turned off. FETs pT1 to pT6 are turned on. Then, the positive normal gamma reference voltages GMA1 (L), GMA2 (L), and GMA3 (L) are supplied to the data driver 53 through the positive gamma reference voltage output terminals as shown in FIG. The negative normal gamma reference voltages GMA4 (H), GMA5 (H), and GMA6 (H) are supplied to the data driver 53 through the reference voltage output terminals.

8 and 9 are circuit diagrams showing a second embodiment of the gamma reference voltage variable circuit 52.

8 and 9, the gamma reference voltage variable circuit 52 includes a first gamma reference voltage variable circuit 62 for generating a high-speed driving gamma reference voltage, and a second gamma reference voltage for generating a normal driving gamma reference voltage. The output voltage of the first gamma reference voltage variable circuit 62 and the output voltage of the second gamma reference voltage variable circuit 64 are selected in response to the gamma reference voltage variable circuit 64 and the high-speed drive control signal ODC. The switch elements nT1 to pT6 are provided.

The first gamma reference voltage variable circuit 62 divides the high potential common voltage VDD-ODC and the low potential common voltage VSS into a plurality of resistors R21 to R27 to output nodes n21 ˜. n26) generates gamma reference voltages for high-speed driving.

The divided resistors R21 to R27 of the first gamma reference voltage variable circuit 62 include the first divided resistor groups R21 to R23 for generating the gamma reference voltages for the positive fast driving, and the gamma reference voltage for the negative fast driving. The second divided resistance group (R25 ~ R27) for generating them.

The first voltage divider groups R21 to R23 divide the voltages of the high-speed driving high potential common voltage VDD-ODC and the twenty-third output node n23 to generate the twenty-first, 22, and 23 output nodes n21, n22, and n23. ) Generates gamma reference voltages for positive fast drive.

The second voltage divider resistors R25 to R27 divide the voltage of the 24th output node n24 and the low potential common voltage VSS to be negatively connected through the 24th, 25th, and 26th output nodes n24, n25, and n26. Generates gamma reference voltages for polarity fast drive.

The second gamma reference voltage variable circuit 64 is configured to be substantially the same as the conventional gamma reference voltage generation circuit and operates similarly to the prior art. That is, the second gamma reference voltage variable circuit 64 divides the normal driving high potential common voltage VDD-normal and the low potential common voltage VSS into a plurality of resistors R31 to R37 to output nodes ( n31 to n36) generate gamma reference voltages for normal driving.

The divided resistors R31 to R37 of the second gamma reference voltage variable circuit 64 may include the third divided resistor groups R31 to R33 for generating the gamma reference voltages for the positive normal driving, and the gamma reference voltage for the negative normal driving. It is divided into a fourth divided resistance group (R35 ~ R37) for generating them.

The third voltage divider groups R31 to R33 divide the voltages of the high driving common voltage VDD-normal and the 33rd output node n33 by the normal driving voltages 31, 32, and 33 output nodes n31, n32, and n33. ) Generates gamma reference voltages for positive normal driving.

The fourth divided resistor groups R35 to R37 divide the voltage of the thirty-fourth output node n44 and the low potential common voltage VSS to be negative through the thirty-fourth, thirty-sixth, and thirty-fourth output nodes n34, n35, and n36. Generate gamma reference voltages for polarity normal driving.

The switch elements nT1 to pT6 are the first gamma reference voltage in response to the high logic high speed drive control signal ODC (H) generated during a period of 1/2 horizontal period or less in synchronization with a scan pulse or a gate pulse. While the high-speed driving gamma reference voltages output from the variable circuit 62 are selected as the gamma reference voltage supplied to the data driver 53, the high-speed driving gamma reference voltages are selected in response to the high-speed driving control signal ODC (L) of low logic voltage. 2 Gamma Reference Voltage The gamma reference voltages for the normal driving output from the variable circuit 64 are selected as the gamma reference voltage supplied to the data driver 53.

The switch elements nT1 to pT6 are divided into a first switch group nT1 to pT3 for selecting the positive gamma reference voltages and a second switch group nT4 to pT6 for selecting the negative gamma reference voltages.

The first switch group nT1 to pT3 are used for positive high speed driving from the 21st, 22nd and 23rd output nodes n21, n22, and n23 in response to the high speed drive control signal ODC (H). First to third n-type MOS-FETs (nT1, nT2, nT3) for outputting the gamma reference voltage as the positive gamma reference voltages GMA1, GMA2, and GMA3, and a high-speed driving control signal (ODC) having a low logic voltage. L1) to first to output positive normal gamma reference voltages from the 31st, 32, and 33 output nodes n31, n32, and n34 as positive gamma reference voltages GMA1, GMA2, and GMA3. Third p-type MOS-FETs pT1, pT2, and pT3. Gate terminals of the first to third n-type MOS-FETs (nT1, nT2, nT3) are connected to the high-speed drive control signal input terminals, and sources of the first to third n-type MOS-FETs (nT1, nT2, nT3). The terminal is connected to the twenty-first, twenty-second, and twenty-third output nodes n21, n22, n23. Gate terminals of the first to third p-type MOS-FETs pT1, pT2 and pT3 are connected to the high-speed drive control signal input terminals, and sources of the first to third p-type MOS-FETs pT1, pT2 and pT3. The terminal is connected to the 31st, 32, and 33 output nodes n31, n32, n33. The drain terminals of the first to third n-type MOS-FETs (nT1, nT2, nT3) and the drain terminals of the first to third p-type MOS-FETs (pT1, pT2, and pT3) are positive gamma reference voltage output terminals. To GMA1, GMA2, and GMA3.

The second switch group nT4 to pT6 are used for negative normal driving from the 34th, 35th, and 36th output nodes n34, n35, and n36 in response to the high-speed drive control signal ODC (L) of low logic voltage. Fourth to sixth p-type MOS-FETs (pT4, pT5, and pT6) outputting the gamma reference voltage as the negative gamma reference voltages GMA4, GMA5, and GMA6, and a high-speed high-speed drive control signal (ODC) H)) outputting the negative fast driving gamma reference voltages from the 24th, 25th, and 26th output nodes n24, n25, and n26 as the negative gamma reference voltages GMA4, GMA5, and GMA6. Fourth to sixth n-type MOS-FETs (nT4, nT5, nT6). Gate terminals of the fourth to sixth p-type MOS-FETs pT4, pT5, and pT6 are connected to the high-speed drive control signal input terminals, and sources of the fourth to sixth p-type MOS-FETs pT4, pT5 and pT6. The terminal is connected to the 34th, 35th, 36th output nodes n34, n35, n36. Gate terminals of the fourth to sixth n-type MOS-FETs (nT4, nT5, nT6) are connected to the high-speed drive control signal input terminals, and sources of the fourth to sixth n-type MOS-FETs (nT4, nT4, nT6). The terminal is connected to the 24th, 25th, 26th output nodes n24, n25, n26. The drain terminals of the fourth to sixth p-type MOS-FETs (pT4, pT5, and pT6) and the drain terminals of the fourth to sixth n-type MOS-FETs (nT4, nT5, and nT6) are connected to the negative gamma reference voltage output terminal. (GMA4, GMA5, GMA6).

The operation of the gamma reference voltage variable circuit 52 according to the second embodiment of the present invention will be described below.

When the high speed driving control signal (ODC) is generated at the high logic voltage (H) for a period of about 1/2 horizontal period or less in synchronization with the scan pulse or the gate pulse, the first to sixth n-type MOS-FETs nT1 to nT6 is turned on, while first to sixth p-type MOS-FETs pT1 to pT6 are turned off. Then, as shown in FIG. 8, the gamma reference voltages GMA1 (H), GMA2 (H), and GMA3 (H) for positive fast driving are higher than the positive normal gamma reference voltages through the positive gamma reference voltage output terminals. The data driver 53 is supplied with the negative gamma reference voltage output terminals to be relatively low (higher in absolute value) than the negative normal gamma reference voltages. ), GMA5 (L) and GMA6 (L) are supplied to the data driver 53.

When the fast driving control signal ODC is generated with the low logic voltage L, the first to sixth n-type MOS-FETs nT1 to nT6 are turned off while the first to sixth p-type MOS- are turned off. FETs pT1 to pT6 are turned on. Then, as shown in FIG. 9, the positive normal gamma reference voltages GMA1 (L), GMA2 (L), and GMA3 (L) are supplied to the data driver 53 through the positive gamma reference voltage output terminals, and the negative gamma The negative normal gamma reference voltages GMA4 (H), GMA5 (H), and GMA6 (H) are supplied to the data driver 53 through the reference voltage output terminals.

As described above, the gamma reference voltage variable circuit according to the present invention increases the absolute value of the pixel voltage applied to the liquid crystal cell by adding a switch element or a resistor to the voltage divider circuit that generates the gamma reference voltage. You can speed it up.

The liquid crystal display according to the present invention utilizes the gamma reference voltage variable circuit to remove a plurality of memories, memory control circuits, etc. required for the existing high speed driving circuit, thereby simplifying the circuit and reducing the amount of heat generated by the high speed driving circuit. Depending on the furnace, it is possible to increase the response speed of the liquid crystal without increasing the necessary circuit, thereby improving the display quality in the moving picture.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (16)

A voltage divider circuit connected between the high potential voltage source and the low potential voltage source to divide the high potential voltage and the low potential voltage to generate a plurality of gamma reference voltages through the plurality of output nodes; A switch circuit connected between neighboring output nodes to vary the gamma reference voltages in response to a control signal; And the output nodes include positive output nodes generating gamma reference voltages higher than a predetermined common voltage and negative output nodes generating gamma reference voltages lower than the common voltage. The method of claim 1, The control signal is, A gamma reference voltage variable circuit, characterized in that it is generated for a period less than 1/2 horizontal period. delete The method of claim 1, The switch circuit, A plurality of first switch elements for selecting a positive gamma reference voltage from any one of the neighboring positive output nodes in response to the control signal of a high logic voltage; A plurality of second switch elements for selecting a positive gamma reference voltage from another one of the neighboring positive output nodes in response to the control signal of a low logic voltage; A plurality of third switch elements for selecting a negative gamma reference voltage from any one of the neighboring negative output nodes in response to the control signal of the high logic voltage; And a plurality of fourth switch elements for selecting a negative gamma reference voltage from another one of the neighboring negative output nodes in response to the control signal of the low logic voltage. A first divided voltage connected between the first high potential voltage source and the first low potential voltage source to divide the first high potential voltage and the first low potential voltage to generate a plurality of first gamma reference voltages through the plurality of first output nodes; Circuits; A second divided voltage connected between the second high potential voltage source and the second low potential voltage source to divide the second high potential voltage and the second low potential voltage to generate a plurality of second gamma reference voltages through the plurality of second output nodes; Circuits; Any one of the first gamma reference voltages and the second gamma reference voltages is connected between the first output nodes of the first voltage divider circuit and the second output nodes of the second voltage divider circuit in response to a control signal. And a switch circuit for selecting The first output nodes may include first positive output nodes generating first positive gamma reference voltages higher than a predetermined common voltage and first negative outputs generating first negative gamma reference voltages lower than the common voltage. A gamma reference variable circuit comprising nodes. 6. The method of claim 5, The control signal is, A gamma reference voltage variable circuit, characterized in that it is generated for a period less than 1/2 horizontal period. 6. The method of claim 5, The second output nodes, Second positive output nodes generating second positive gamma reference voltages lower than the first positive gamma reference voltages and higher than the common voltage; And a second negative output node generating second negative gamma reference voltages higher than the first negative gamma reference voltages and lower than the common voltage. The method of claim 7, wherein The switch circuit, A plurality of first switch elements for selecting a positive gamma reference voltage from any one of the first positive output node and the second positive output node in response to the control signal of a high logic voltage; A plurality of second switch elements for selecting a positive gamma reference voltage from another of the first positive output node and the second positive output node in response to the control signal of a low logic voltage; A plurality of third switch elements configured to select a negative gamma reference voltage from any one of the first negative output node and the second negative output node in response to the control signal of the high logic voltage; And a plurality of fourth switch elements for selecting a negative gamma reference voltage from the other of the second negative output node and the second negative output node in response to the control signal having a low logic voltage. Gamma reference voltage variable circuit. A liquid crystal display panel in which data lines and gate lines intersect and a plurality of liquid crystal cells are disposed; A voltage divider circuit connected between a high potential voltage source and a low potential voltage source to divide a high potential voltage and a low potential voltage to generate a plurality of gamma reference voltages through a plurality of output nodes, and connected to and controlled between the neighboring output nodes. A gamma reference voltage variable circuit including a switch circuit for varying the gamma reference voltages in response to a signal; A data driver converting digital video data into an analog pixel voltage using the gamma reference voltages from the gamma reference voltage variable circuit and supplying the analog pixel voltages to the data lines; A gate driver supplying scan pulses to the gate lines; A timing controller for supplying the digital video data to the data driver and generating the control signal and timing control signals required for the drivers; And the output nodes include positive output nodes generating gamma reference voltages higher than a predetermined common voltage and negative output nodes generating gamma reference voltages lower than the common voltage. The method of claim 9, The control signal is, A liquid crystal display device, wherein the liquid crystal display is generated for a period of 1/2 or less horizontal period. delete The method of claim 9, The switch circuit, A plurality of first switch elements for selecting a positive gamma reference voltage from any one of the neighboring positive output nodes in response to the control signal of a high logic voltage; A plurality of second switch elements for selecting a positive gamma reference voltage from another one of the neighboring positive output nodes in response to the control signal of a low logic voltage; A plurality of third switch elements for selecting a negative gamma reference voltage from any one of the neighboring negative output nodes in response to the control signal of the high logic voltage; And a plurality of fourth switch elements for selecting a negative gamma reference voltage from another one of the neighboring negative output nodes in response to the low logic voltage control signal. A liquid crystal display panel in which data lines and gate lines intersect and a plurality of liquid crystal cells are disposed; A first divided voltage connected between the first high potential voltage source and the first low potential voltage source to divide the first high potential voltage and the first low potential voltage to generate a plurality of first gamma reference voltages through the plurality of first output nodes; A circuit connected between the second high potential voltage source and the second low potential voltage source to divide the second high potential voltage and the second low potential voltage to generate a plurality of second gamma reference voltages through the plurality of second output nodes. A second voltage divider circuit is connected between the first output nodes of the first voltage divider circuit and the second output nodes of the second voltage divider circuit so as to respond to a control signal, the first gamma reference voltages and the second gamma. A gamma reference voltage variable circuit including a switch circuit for selecting any one of the reference voltages; A data driver converting digital video data into an analog pixel voltage using the gamma reference voltages from the gamma reference voltage variable circuit and supplying the analog pixel voltages to the data lines; A gate driver supplying scan pulses to the gate lines; A timing controller for supplying the digital video data to the data driver and generating the control signal and timing control signals required for the drivers; The first output nodes may include first positive output nodes generating first positive gamma reference voltages higher than a predetermined common voltage and first negative outputs generating first negative gamma reference voltages lower than the common voltage. Liquid crystal display comprising a node. The method of claim 13, The control signal is, A liquid crystal display device, wherein the liquid crystal display is generated for a period of 1/2 or less horizontal period. The method of claim 13, The second output nodes, Second positive output nodes generating second positive gamma reference voltages lower than the first positive gamma reference voltages and higher than the common voltage; And second negative output nodes generating second negative gamma reference voltages higher than the first negative gamma reference voltages and lower than the common voltage. 16. The method of claim 15, The switch circuit, A plurality of first switch elements for selecting a positive gamma reference voltage from any one of the first positive output node and the second positive output node in response to the control signal of a high logic voltage; A plurality of second switch elements for selecting a positive gamma reference voltage from another of the first positive output node and the second positive output node in response to the control signal of a low logic voltage; A plurality of third switch elements configured to select a negative gamma reference voltage from any one of the first negative output node and the second negative output node in response to the control signal of the high logic voltage; And a plurality of fourth switch elements for selecting a negative gamma reference voltage from the other of the second negative output node and the second negative output node in response to the control signal having a low logic voltage. Liquid crystal display device.

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