KR20090073465A - Liquid crystal display deive and metohd for diving the same - Google Patents

Abstract

A liquid crystal display device and a method for driving the same are provided to respectively supply a real image data signal and a black data signal to each pixel, thereby increasing charging time of each gate line. Each pixel cell comprises a liquid crystal cell(401), the first switching device and the second switching device. The liquid crystal cell displays an image. The first switching device supplies data to the liquid crystal cell through switching according to a gate line from gate lines(GL1~GLn). The second switching device supplies an AC common voltage from an AC(Alternating Current) common line according to a scan signal from scan lines(SL1~SLn).

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEIVE AND METOHD FOR DIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a display device and a driving method thereof capable of sufficiently securing a gate line charging time even in an impulsive driving state.

In general, a liquid crystal display device (LCD) is a device for displaying an image by selectively transmitting the light generated from the light source at the rear surface of each pixel of the LCD panel at the front surface by acting as a kind of optical switch. That is, the conventional cathode ray tube (CRT) controls the brightness by adjusting the intensity of the electron beam to be scanned, whereas the LCD controls the brightness of the screen by controlling the intensity of light generated from the light source.

With the development of technology, not only the technology of displaying still images but also the technology of displaying moving images is in the spotlight.

However, it is difficult to realize a moving picture in a liquid crystal display device used for various display media because the response speed of the liquid crystal is slower than that of one frame period. If it is not held and then a new voltage is applied in the next frame, motion blur occurs on the screen.

That is, the CRT (Cathod Ray Tube) is driven in the impulse method, while the liquid crystal display is driven in the Hold (Hold) method, the screen is dragged when the video is implemented.

In order to eliminate the screen drag phenomenon in the liquid crystal display, an impulsive driving method for inputting data in a part of a frame and black data in another part, such as a CRT, has been proposed.

Hereinafter, a conventional impulsive driving method will be described with reference to the accompanying drawings.

1 is a view for explaining a conventional impulsive driving method.

As shown in FIG. 1, the gate driving circuit included in the conventional liquid crystal display device sequentially outputs scan pulses Vout1 to Voutn + 5 and sequentially supplies them to the gate lines.

The gate driving circuit outputs first to n + 3 scan pulses Vout1 to Voutn + 3 from a first period T1 to an n + 3th period Tn + 3 to output first to n + 3 gates. Print sequentially on the line. Accordingly, the pixel cells connected to the first through n + 3 gate lines receive real image data signals from the data driving circuit to display an image.

Thereafter, in the n + 4 period Tn + 4, the gate driving circuit simultaneously outputs the first to fourth scan pulses Vout1 to Voutn + 4 to simultaneously drive the first to fourth gate lines. Then, the pixel cells connected to the first to fourth gate lines receive the black data signal from the data driving circuit.

However, according to such a conventional driving method, the charging time of the gate line is inevitably reduced. That is, in the conventional impulsive method, since the time for inserting the black data signal must be secured, the driving speed of each gate line should be relatively fast. In other words, the driving time of each gate line is inevitably shortened. As a result, a problem occurs that the gate line becomes difficult to be charged to a sufficient voltage. This becomes a more serious problem, especially in a high resolution model liquid crystal display device. That is, a liquid crystal display device having a higher resolution model requires more gate lines and therefore requires a shorter gate line driving time. When the black data is inserted in this way, the gate line driving time is inevitably shorter.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and each gate is operated by impulsive driving by supplying the real image data signal and the black data signal at the same time using the gate signal and the scan signal output in different periods. It is an object of the present invention to provide a display device and a driving method thereof capable of sufficiently securing a line charging time.

According to an aspect of the present invention, there is provided a liquid crystal display device including pixel cells formed in each pixel region defined by a plurality of gate lines and a plurality of data lines crossing each other; Each pixel cell includes: a liquid crystal cell for displaying an image; A first switching device for switching data from the data line and supplying the data to the liquid crystal cell according to a gate signal from a gate line; And a second switching device for supplying an AC common voltage in the form of AC from the AC common line to the liquid crystal cell in response to a scan signal from the scan line.

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object, a liquid crystal comprising a plurality of pixel cells formed for each pixel region defined by a plurality of gate lines and a plurality of data lines that cross each other A method of driving a display device, comprising: switching data from the data line according to a gate signal from a gate line and supplying the data to a liquid crystal cell in the pixel cell; And switching the AC common voltage in the form of AC from the AC common line according to the scan signal from the scan line and supplying the same to the liquid crystal cell.

As described above, the display device and the driving method thereof according to the present invention have the following effects.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a gate driver for supplying a gate signal, a scan driver for supplying a scan signal, a data driver for supplying a real image data signal to a data line according to the gate signal, and a scan signal for the scan signal. Accordingly, the AC power supply unit for supplying the AC common voltage to the AC common line.

That is, the display device of the present invention can supply the real image data signal and the black data signal to each pixel by using the gate line and the scan line, thereby increasing the charging time of each gate line.

Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a display device according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram for describing a waveform of an AC common voltage Com_ac from an AC power supply unit of FIG. 2.

As shown in FIG. 2, a display device according to an exemplary embodiment of the present invention may include a liquid crystal panel 200 for displaying an image and driving gate lines GL1 to GLn of the liquid crystal panel 200. Data in the gate driver GD, the scan driver SD for driving the scan lines SL1 to SLn of the liquid crystal panel 200, and the data lines DL1 to DLm of the liquid crystal panel 200. And a data driver DD for supplying a signal, and an AC power generator 255 for supplying an AC common voltage COM_ac to an AC common line ACL of the liquid crystal panel 200.

In the display unit of the liquid crystal panel 200, a plurality of pixel cells PXL for displaying a unit image are arranged in a matrix form, and each of the pixel cells PXL includes gate lines GL1 to GLn and scan lines SL1. To SLn), a DC common line (DCL), and an AC common line (ACL).

The pixel cells PXL for one horizontal line arranged along one row direction are commonly connected to one gate line and commonly connected to one scan line. Further, the pixel cells PXL for one horizontal line arranged along one row direction are individually connected to the respective data lines DL1 to DLm.

The number of gate lines GL1 to GLn and the number of scan lines SL1 to SLn are the same.

Pixel cells PXL for one vertical line arranged along one column direction are commonly connected to one data line. Further, the pixel cells PXL for one vertical line arranged along one column direction are individually connected to the respective gate lines GL1 to GLn.

All of the pixel cells PXL included in the liquid crystal panel 200 are commonly connected to one DC common line DCL and are commonly connected to one AC common line ACL. The DC common line DCL transmits a DC common voltage Com_dc, and the AC common line ACL transmits an AC common voltage Com_ac.

Although not shown in the drawing, one side of the DC common lines DCL are connected to each other to receive a DC common voltage Com_dc from a DC power generator.

The AC power generator 255 supplies the AC common voltage Com_ac to the AC common line ACL. As illustrated in FIG. 3, the AC common voltage Com_ac is a high potential voltage HV every period. ) And the low potential voltage LV are alternately represented, and the DC common voltage Com_dc is maintained at a constant voltage. The AC common voltage Com_ac and the DC common voltage Com_dc will be described in detail later.

The AC power generator 255 and the DC power generator may be embedded in the gate driver GD.

Each pixel cell PXL displays a real image by the data signal from the data line, and displays a black image by the AC common voltage Com_ac from the AC common voltage Com_ac line.

The gate lines GL1 to GLn are sequentially driven by receiving the gate signals GS1 to GSn from the gate driver GD. That is, the gate driver GD sequentially supplies the gate signals GS1 to GSn from the uppermost first gate line GL1 to the lowermost nth gate line GLn and supplies the gate lines GS. GL1 to GLn) are driven in sequence.

Each time one gate line is driven, the data driver DD charges the data signal to all the data lines DL_L. Accordingly, when any gate line is driven, the pixel cells PXL for one horizontal line connected to the gate line are supplied with data signals from the data line DL_L to which they are connected to display an image.

The scan lines SL1 to SLn are sequentially driven by receiving scan signals SS1 to SSn from the scan driver SD. That is, the scan driver SD sequentially supplies scan signals SS1 to SSn from the uppermost first scan line SL1 to the lowermost nth scan line SLn and supplies the scan lines SS1 to SSn. SL1 to SLn are sequentially driven.

When the scan line is driven, the pixel cells PXL for one horizontal line connected to the driven scan line are supplied with an AC common voltage Com_ac from an AC common line ACL to display a black image.

In order to reduce the size of the display device, the gate driver GD and the scan driver SD may be built in the liquid crystal panel 200.

Herein, the structure of each pixel cell PXL is as follows.

As shown in FIG. 2, the pixel cell PXL includes a liquid crystal cell 401 for displaying an image and a switching unit 402 for driving the liquid crystal cell 401. The switching unit 402 includes a first switching device Tr1 for supplying a data signal to the liquid crystal cell 401, and a second switching device for supplying an AC common voltage Com_ac to the liquid crystal cell 401. (Tr2).

The liquid crystal cell 401 includes a pixel electrode and a common electrode Vcom facing each other, and a liquid crystal layer formed between the pixel electrode and the common electrode Vcom. The liquid crystal layer exhibits different transmittances depending on the magnitude of the vertical electric field formed between the pixel electrode PE and the common electrode Vcom. The display device has two substrates facing each other. The common electrode Vcom is formed on the front surface of the upper substrate, and the pixel electrode PE is formed on the lower substrate.

The liquid crystal cell 401 configured as described above includes a liquid crystal capacitor Clc for receiving and storing the data signal and a storage capacitor Cst for stably maintaining the data signal stored in the liquid crystal capacitor Clc. .

The liquid crystal capacitor Clc includes a pixel electrode, a common electrode Vcom, and a liquid crystal layer positioned between the pixel electrode and the common electrode Vcom. That is, the pixel electrode corresponds to the first electrode of the liquid crystal capacitor Clc, and the common electrode Vcom corresponds to the second electrode of the liquid crystal capacitor Clc, and the common with the pixel electrode. The liquid crystal layer formed between the electrodes Vcom corresponds to the dielectric of the liquid crystal capacitor Clc.

The storage capacitor Cst is formed where the DC common line DCL and the pixel electrode overlap. That is, the DC common line DCL corresponds to the first electrode of the storage capacitor Cst, and the pixel electrode corresponds to the second electrode of the storage capacitor Cst, and the DC common line The insulating film formed between the DCL) and the pixel electrode corresponds to the dielectric of the storage capacitor Cst.

The first switching device Tr1 is turned on in response to the scan signal from the gate line, and supplies the data signal from the data line to the pixel electrode at turn-on. To this end, a gate electrode of the first switching element Tr1 is connected to the gate line, a drain electrode is connected to the data line, and a source electrode is connected to the pixel electrode.

The second switching device Tr2 is turned on in response to a scan signal from the scan line, and supplies the AC common voltage Com_ac from the AC common line ACL to the pixel electrode PE at turn-on. To this end, the gate electrode GE of the second switching element Tr2 is connected to the scan line, the drain electrode is connected to the AC common line ACL, and the source electrode is connected to the pixel electrode. .

When the second switching device Tr2 is turned on, an AC common voltage Com_ac is supplied to the pixel electrode, and a maximum vertical electric field is generated between the pixel electrode and the common electrode. Therefore, the transmittance of the liquid crystal layer is almost zero. Accordingly, the pixel cell PXL displays a black image (TN liquid crystal display device in normally white mode).

As shown in FIG. 3, the AC common voltage Com_ac alternates between a high potential voltage HV and a low potential voltage VV. The high potential voltage HV is set to have the same voltage as the data signal of the positive highest gray scale for displaying the black color, and the low potential voltage LV is the negative highest gray scale for displaying the black color. Is set to have the same voltage as the data signal.

The AC common voltage Com_ac may be inverted every 1H horizontal time in which one horizontal line of pixel cells PXL is driven, and the pixel cells PXL of all horizontal lines are driven. It may be reversed every frame period.

Meanwhile, as shown in FIG. 3, the DC common voltage Com_dc is a DC voltage having an intermediate value of the AC common voltage Com_ac, and is applied to the storage capacitor Cst and the common electrode of the pixel cell PXL. Supplied.

Here, the DC common voltage Com_dc supplied to the common electrode is a reference voltage for indicating the potential of the data signal supplied to the pixel cell PXL. That is, the smaller the difference between the data signal and the DC common voltage Com_dc supplied to the common electrode Vcom, that is, the data signal has a value closer to the DC common voltage Com_dc, the pixel cell PXL. ) Represents a bright color close to the white color. On the other hand, as the difference between the data signal and the DC common voltage Com_dc supplied to the common electrode Vcom increases, that is, the data signal has a value farther from the DC common voltage Com_dc, the pixel cell PXL. Represents a dark color close to black. In other words, the pixel cells PXL are driven in a normally white mode.

The pixel cell PXL is black due to the AC common voltage Com_ac, which will be described in more detail as follows.

The first switching device Tr1 is turned on by the gate signal, and the data signal from the data line is supplied to the pixel electrode through the turned-on first switching device Tr1. Then, the pixel voltage corresponding to the difference between the data signal supplied to the pixel electrode and the DC common voltage Com_dc of the common electrode Vcom is stored in the liquid crystal capacitor Clc, and the pixel voltage is stored in the storage capacitor It is maintained stably by Cst).

Next, after the first switching device Tr1 is turned off, if the second switching device Tr2 is turned on by a scan signal, an AC common line is provided through the turned-on second switching device Tr2. AC common voltage Com_ac from ACL is supplied to the pixel electrode. The pixel voltage corresponding to the difference between the AC common voltage Com_ac supplied to the pixel electrode and the DC common voltage Com_dc of the common electrode Vcom is stored in the liquid crystal capacitor Clc. It is held stably by the capacitor Cst.

In this case, the high potential voltage HV of the AC common voltage Com_ac is the same as the positive highest gray level data signal, and the low potential voltage LV of the AC common voltage Com_ac is equal to the negative highest gray level data signal. Since the AC common voltage Com_ac has the same value, the pixel cell PXL always displays a black image when the AC common voltage Com_ac is supplied to the pixel electrode. Specifically, when the AC common voltage Com_ac having the high potential voltage HV is supplied to the pixel electrode, the pixel cell PXL displays a black image corresponding to the positive highest grayscale data signal, and the pixel electrode. When the AC common voltage Com_ac having the low potential voltage LV is supplied to the pixel cell PXL, the pixel cell PXL displays a black image corresponding to the negative highest grayscale data signal.

In this case, the AC common voltage Com_ac is inverted every frame period so that one pixel cell PXL is maintained at a pixel voltage having a different polarity every frame period, thereby displaying the black image. In this case, deterioration of the pixel cells PXL is prevented.

In the liquid crystal display having the pixel cell PXL having such a structure, the gate line and the scan line corresponding to each other, for example, the first gate line GL1 and the first scan line SL1 are driven at different times. Accordingly, each pixel cell PXL displays a real image once and then a black image. In detail, each of the pixel cells PXL alternately displays a real image and a black image.

For this operation, the gate driver GD operates before the scan driver SD based on one frame. That is, when it is assumed that the number of gate lines and the number of scan lines are equal to n, the gate driver GD first performs the first gate line GL1, the second gate line GL2, and the third gate line ( GL3), ... drive the n-th gate line GLn.

In this case, the scan driver SD starts to drive the first scan line SL1 at a time when any one of the gate lines GL1 to GLn (except the first gate line GL1) is driven. .

For example, the scan driver SD starts to drive the first scan line SL1 at a timing at which the p-th gate line (p is a natural number of 2 or more) is driven. Accordingly, the p-th gate line and the first scan line SL1 are simultaneously driven. Therefore, when the pixel cells PXL for one horizontal line connected to the p-th gate line receive a data signal, the pixel cells PXL for one horizontal line connected to the first scan line SL1. (The pixel cells PXL have already been supplied with a data signal to display an image.) Will display a black image.

That is, when the p-th gate line is referred to as the reference gate line, the scan driver SD starts to sequentially drive the scan lines SL1 to SLn at a time point when the reference gate line is driven.

As a result, from the time when the reference gate line is driven, the pixel cells PXL positioned above the reference gate line start displaying a black image, and the pixel cells PXL positioned below the reference gate line display the real image. Start marking. In other words, the pixel cell PXL positioned above the reference gate line and the pixel cell PXL positioned below the reference gate line start to be driven at the same time from the time when the reference gate line is driven.

Accordingly, the reference gate line (ie, the p gate line) and the first scan line SL1 are simultaneously driven, and then the p + 1 gate line and the second scan line SL2 are simultaneously driven, and then the p The +2 gate line and the third gate line are driven simultaneously. That is, the k-th gate line and the k-p + 1 scan line are driven simultaneously (k is a natural number larger than p and smaller than n).

Alternatively, several gate lines may be sequentially driven from the reference gate line, and the scan lines corresponding to the number of gate lines driven in the gate lines (in the driving period thereof) may be simultaneously driven.

That is, if the gate driver GD drives the reference gate line (that is, the p-th gate line) in the p period, and then drives the p + 1 gate line in the p + 1 period, the scan driver SD simultaneously drives the first scan line SL1 and the second scan line SL2 in the p period. In this case, the scan driver SD does not output a scan signal in the p + 1 period.

That is, the gate driver GD drives the corresponding gate line in each period, and the scan driver SD operates only in the p + 2i period and does not operate in the p + (2i + 1) period (i is 0). Natural numbers, including). In this case, the scan driver SD simultaneously drives as many scan lines as multiples of i in the p + 2i period. Since the multiple of i is 2, the scan driver SD drives two scan lines simultaneously.

Alternatively, the scan driver SD may simultaneously drive as many scan lines as a multiple of the i in the p + (2i + 1) period and may not operate during the p + 2i period. have.

For such driving, the gate driver GD and the scan driver SD may have the following structure.

4 is a diagram illustrating a detailed configuration of the gate driver GD and the scan driver SD of FIG. 2, and FIG. 5 illustrates various clock pulses supplied to the gate driver GD and the scan driver SD of FIG. 4. A timing diagram of scan pulses output from the gate driver GD and the scan driver SD is shown.

Here, since the driving of all the pixel cells PXL is the same, the operation of the pixel cells PXL arranged along any one pixel column will be described.

First, the gate driver GD will be described.

The gate driver GD includes n stages ST1_L to STn_L and one dummy stage STn + 1_L connected to each other. Here, each of the stages ST1_L to STn + 1_L outputs one gate signal GS1 to GSn in one frame, and in this case, the gate signals GS1 to L from the first stage ST1_L to the dummy stage STn_L. GSn) is output. In this case, the gate signals GS1 to GSn output from the stages ST1_L to STn_L except the dummy stages STn + 1_L are sequentially formed on the gate lines GL1 to GLn of the liquid crystal panel 200. The gate lines GL1 through GLn are sequentially driven.

The entire stages ST1_L to STn + 1_L of the gate driver GD configured as described above are the first to fourth clock pulses CLK1 having a sequential phase difference with the first voltage VDD and the second voltage VSS. To one of the clock pulses of CLK4). Here, the first voltage VDD means a positive voltage source, and the second voltage VSS means a ground voltage.

Meanwhile, the first stage ST1_L located at the uppermost side of the stages ST1_L to STn + 1_L has a first start in addition to the first voltage VDD, the second voltage VSS, and the two clock pulses. The pulse Vst1 is supplied.

The operation of the gate driver GD configured as described above will be described in detail as follows.

First, when the first start pulse Vst1 from a timing controller (not shown) is supplied to the first stage ST1_L, the first stage ST1_L is enabled in response to the first start pulse Vst1. do.

Subsequently, the enabled first stage ST1_L receives the first clock pulse CLK1 from the timing controller, outputs a first gate signal GS1, and supplies it to the first gate line GL1. Then, the first pixel cell PXL1 connected to the first gate line GL1 is driven. That is, the first switching device TR1 provided in the first pixel cell PXL1 is turned on. Then, the first pixel cell PXL1 receives a data signal from the first data line DL1 to display a real image.

Here, the first gate signal GS1 output from the first stage ST1_L is supplied to the second stage ST2_L to enable the second stage ST2_L. The enabled second stage ST2_L receives the second clock pulse CLK2 from the timing controller, outputs a second gate signal GS2, and supplies it to the second gate line GL2. Then, the second pixel cell PXL2 connected to the second gate line GL2 is driven. That is, the first switching device Tr1 included in the second pixel cell PXL2 is turned on. Then, the second pixel cell PXL2 receives a data signal from the first data line DL1 to display a real image.

Here, the second gate signal GS2 output from the second stage ST2_L is supplied to the third stage ST3_L to enable the third stage ST3_L. The enabled third stage ST3_L receives the third clock pulse CLK3 from the timing controller, outputs a third gate signal GS3, and supplies it to the third gate line GL3. Then, the third pixel cell PXL3 connected to the third gate line GL3 is driven. That is, the first switching device Tr1 provided in the third pixel cell PXL3 is turned on. Then, the third pixel cell PXL3 receives a data signal from the first data line DL1 to display a real image.

In addition, the second gate signal GS2 output from the second stage ST2_L is supplied to the first stage ST1_L to disable the first stage ST1_L. The disabled first stage ST1_L supplies the low potential voltage source VSS to the first gate line GL1 to inactivate (discharge) the first gate line GL1. Accordingly, the first pixel cell PXL1 connected to the first gate line GL1 holds a real image.

That is, the h th stage (h is a natural number) is enabled in response to the gate signal from the h-1st stage and is disabled in response to the gate signal from the h + 1th stage.

In this manner, the fourth to nth gate signals GS4 to GSn are sequentially output to the remaining fourth to nth stages ST4_L to STn_L and sequentially applied to the corresponding gate lines. As a result, each gate line GL1_L through GLn_L is sequentially driven by the sequentially output first through nth gate signals GS1 through GSn.

Next, the scan driver SD will be described in detail.

The scan driver SD includes n stages ST1_R to STn_R and one dummy stage STn + 1_R connected to each other. Here, each of the stages ST1_R to STn + 1_R outputs one scan signal SS1 to SSn in one frame, and in this case, the scan signals (from the first stage ST1_R to the dummy stage STn + 1_R) are sequentially applied. SS1 to SSn) are output. In this case, scan signals SS1 to SSn output from the stages ST1_R to STn_R except for the dummy stage STn + 1_R may be sequentially applied to the scan lines SL1 to SLn of the liquid crystal panel 200. The scan lines SL1 through SLn are sequentially scanned.

The entire stages ST1_R to STn + 1_R of the scan driver SD configured as described above have the first to fourth clock pulses CLK1 having a sequential phase difference with the first voltage VDD and the second voltage VSS. To one of the clock pulses of CLK4). Here, the first voltage VDD means a positive voltage source, and the second voltage VSS means a ground voltage.

Meanwhile, the first stage ST1_R positioned at the uppermost side of the stages ST1_R to STn + 1_R may have a second start in addition to the first voltage VDD, the second voltage VSS, and the two clock pulses. The pulse Vst2 is supplied.

The operation of the scan driver SD configured as described above will be described in detail as follows.

First, when the second start pulse Vst2 from a timing controller (not shown) is supplied to the first stage ST1_R, the first stage ST1_R is enabled in response to the second start pulse Vst2. do.

Subsequently, the enabled first stage ST1_R receives the first clock pulse CLK1 from the timing controller, outputs a first scan signal SS1, and supplies it to the first scan line SL1. Then, the first pixel cell PXL1 connected to the first scan line SL1 is driven. That is, the second switching device TR2 provided in the first pixel cell PXL1 is turned on. Then, the first pixel cell PXL1 receives the AC common voltage Com_ac from the AC common line ACL to display a black image.

Here, the first scan signal SS1 output from the first stage ST1_R is supplied to the second stage ST2_R to enable the second stage ST2_R. The enabled second stage ST2_R receives the second clock pulse CLK2 from the timing controller, outputs a second scan signal SS2, and supplies it to the second scan line SL2. Then, the second pixel cell PXL2 connected to the second scan line SL2 is driven. That is, the second switching device Tr2 provided in the second pixel cell PXL2 is turned on. Then, the second pixel cell PXL2 receives the AC common voltage Com_ac from the AC common line ACL to display a black image.

Here, the second scan signal SS2 output from the second stage ST2_R is supplied to the third stage ST3_R to enable the third stage ST3_R. The enabled third stage ST3_R receives the third clock pulse CLK3 from the timing controller, outputs a third scan signal SS3, and supplies it to the third scan line SL3. Then, the third pixel cell PXL3 connected to the third scan line SL3 is driven. That is, the second switching device TR2 provided in the third pixel cell PXL3 is turned on. Then, the third pixel cell PXL3 receives the AC common voltage Com_ac from the AC common line ACL to display a black image.

In addition, the second scan signal SS2 output from the second stage ST2_R is supplied to the first stage ST1_R to disable the first stage ST1_R. The disabled first stage ST1_R supplies a second voltage VSS to the first scan line SL1 to inactivate (discharge) the first scan line SL1. Accordingly, the first pixel cell PXL1 connected to the first scan line SL1 retains a black image.

That is, the h-th stage (h is a natural number) is enabled in response to the scan signal from the h-1st stage and is disabled in response to the scan signal from the h + 1th stage.

In this manner, the fourth to nth scan signals SS4 to SSn are sequentially output to the remaining fourth to nth stages ST4_R to STn_R and sequentially applied to the corresponding scan lines. As a result, each scan line SL1 to SLn is sequentially scanned by the sequentially output first to nth scan signals SS1 to SSn.

Here, as shown in FIG. 5, the first start pulse Vst1 and the second start pulse Vst2 are output once in one frame. At this time, the first start pulse Vst1 and the second start pulse Vst2 are output. ) Have different output points. That is, the first start pulse Vst1 is output before the second start pulse Vst2. Accordingly, the gate driver GD operates before the scan driver SD.

For example, as shown in FIG. 5, if the first start pulse Vst1 is output in the start period T0 and the second start pulse Vst2 is output in the twelfth period T12, the gate The driver GD is enabled in the start period T0, and the scan driver SD is enabled in the twelfth period T12.

In other words, a first stage ST1_L provided in the gate driver GD is enabled in the start period T0, and a first stage provided in the scan driver SD in the twelfth period T12. (ST1_R) is enabled.

Accordingly, the gate signals GS1 to GS13 are sequentially supplied from the first stage ST1_L to the thirteenth stage ST13_L included in the gate driver GD from the first period T1 to the thirteenth period T13. It outputs and sequentially drives from the first gate line GL1 to the thirteenth gate line GL13.

The thirteenth gate line GL13_L is the reference gate line described above, and the first scan line SL1 is driven when the thirteenth gate line GL13_L is driven. That is, in the thirteenth period T13, the thirteenth gate line GL13 and the first scan line SL1 are simultaneously driven. In detail, the thirteenth stage ST13_L of the gate driver GD outputs a thirteenth gate signal GL13 to the thirteenth gate line GL13 in the thirteenth period T13, and supplies the thirteenth gate line GL13 to the thirteenth period. The first stage ST1_R of the scan driver SD outputs the first scan signal SS1 to the first scan line SL1 at T13.

Accordingly, in the thirteenth period T13, the thirteenth pixel cell PXL13 connected to the thirteenth gate line GL13 receives a data signal from the first data line DL1 to display a real image. The first pixel cell PXL1 connected to the first scan line SL1 receives the AC common voltage Com_ac from the AC common line ACL to display a black image.

After the thirteenth period T13, the pixel cells PXL positioned above the reference gate line (ie, the thirteenth gate line GL13_L) display a black image, and the pixel cells positioned below the reference gate line PXL) starts to display the real picture.

That is, in the fourteenth period T14, the fourteenth pixel cell PXL14 connected to the fourteenth gate line GL14 displays a real image, and the second pixel cell PXL2 connected to the second scan line SL2. This black image is displayed.

After a period of time, all of the pixel cells PXL positioned below the reference gate line also display a black image. In this case, the pixel cells PXL positioned above the reference gate line may have a first gate line GL1. ), The real image is displayed in order from the pixel cell PXL1 connected to the < RTI ID = 0.0 > In other words, this process is repeated cyclically.

As described above, the scan driver SD may simultaneously drive two or more second gate lines. If this is explained in more detail as follows.

FIG. 6 is a diagram illustrating another detailed configuration of the gate driver GD and the scan driver SD of FIG. 2, and FIG. 7 shows various clock pulses supplied to the gate driver GD and the scan driver SD of FIG. 6. And a timing diagram of gate signals output from the gate driver GD and the scan driver SD.

Since the structure and operation of the gate driver GD are the same as those described with reference to FIG. 4, description thereof will be omitted.

As illustrated in FIG. 6, the scan driver SD includes n stages ST1_R to STn_R and one dummy stage STn + 1_R connected to each other. In this case, the scan driver SD drives the scan lines SL1 through SLn into a plurality of line groups lg1 through lg (n / 2), and the scan driver SD performs the stages ST1_R through The STn_Rs are driven by being divided into a plurality of stage groups sg1 to sg (n / 2).

That is, each line group lg1 to lg (n / 2) includes a plurality of scan lines, and each stage group sg1 to sg (n / 2) includes a plurality of stages.

The number of the line groups lg1 to lg (n / 2) and the number of the stage groups sg1 to sg (n / 2) are equal to each other, and the number of scan lines included in any line group, and The number of stages included in the corresponding stage group is the same.

The scan driver SD provided in the present invention may drive at least two scan lines. For convenience of description, the scan driver SD will be described as an example of simultaneously driving two scan lines.

In this case, each line group lg1 to lg (n / 2) includes two scan lines, and each stage group sg1 to sg (n / 2) includes two stages. That is, in order to simultaneously drive f scan lines (f is a natural number), each line group lg1 to lg (n / 2) includes f scan lines, and each stage group sg1 to sg (n / 2). )) Includes f stages.

Here, one side of the scan lines included in the same line group are connected to each other.

This connected portion is connected only to any one of the stages in the corresponding stage group. Specifically, as shown in FIG. 6, stages ST1_R, ST3_R, ..., STn-1_R located above each of the stage groups sg1 to sg (n / 2) are connected between the scan lines. Connected to the part.

Alternatively, the stages ST2_R, ST4_R, ..., STn_R located under each of the stage groups sg1 to sg (n / 2) may be connected to the connection portions between the scan lines.

The operation of the scan driver SD configured as described above is as follows.

First, when the second start pulse Vst2 from a timing controller (not shown) is supplied to the first stage ST1_R, the first stage ST1_R is enabled in response to the second start pulse Vst2. do.

Subsequently, the enabled first stage ST1_R receives the first clock pulse CLK1 from the timing controller and outputs a first scan signal SS1, which is then used to scan the first scan line SL1 and the second scan. Supply to line SL2. Then, the first pixel cell PXL1 connected to the first scan line SL1 and the second pixel cell PXL2 connected to the second scan line SL2 are simultaneously driven. That is, the second switching device TR2 provided in the first pixel cell PXL1 and the second switching device Tr2 provided in the second pixel cell PXL2 are turned on. Then, the first pixel cell PXL1 and the second pixel cell PXL2 are supplied with an AC common voltage Com_ac from an AC common line ACL to perform a black image.

Here, the first scan signal SS1 output from the first stage ST1_R is supplied to the second stage ST2_R to enable the second stage ST2_R. The enabled second stage ST2_R receives the second clock pulse CLK2 from the timing controller and outputs a second scan signal SS2. In this case, the second scan signal SS2 output from the second stage ST2_R is not supplied to any scan line, but is only supplied to the first stage ST1_R to disable the first stage ST1_R.

Here, the second scan signal SS2 output from the second stage ST2_R is supplied to the third stage ST3_R to enable the third stage ST3_R. The enabled third stage ST3_R receives the third clock pulse CLK3 from the timing controller and outputs a third scan signal SS3, which is then output to the third scan line SL3 and the fourth scan line SL3. SL4). Then, the third pixel cell PXL3 connected to the third scan line SL3 and the fourth pixel cell PXL4 connected to the third scan line SL3 are simultaneously driven. That is, the second switching device Tr2 provided in the third pixel cell PXL3 and the second switching device Tr2 provided in the fourth pixel cell PXL4 are turned on. Then, the third pixel cell PXL3 and the fourth pixel cell PXL4 receive the AC common voltage Com_ac from the AC common line ACL to display a black image.

In this manner, each of the remaining radix stages (ST1_R, ST3_R, ..., STn-1_R) sequentially outputs the scan signals SS1, SS3, ..., SSn-1 so as to scan the two scan lines. Apply simultaneously. As a result, two scan lines are sequentially scanned by the simultaneously output scan signal.

Here, as shown in FIG. 7, the first start pulse Vst1 and the second start pulse Vst2 are output once in one frame, wherein the first start pulse Vst1 and the second start pulse Vst2 are output. ) Have different output points. That is, the first start pulse Vst1 is output before the second start pulse Vst2. Accordingly, the gate driver GD operates before the scan driver SD.

For example, as shown in FIG. 7, if the first start pulse Vst1 is output in the start period T0 and the second start pulse Vst2 is output in the twelfth period T12. The gate driver GD is enabled in the start period T0, and the scan driver SD is enabled in a twelfth period T12.

In other words, a first stage ST1_L provided in the gate driver GD is enabled in the start period T0, and a first stage provided in the scan driver SD in the twelfth period T12. (ST1_R) is enabled.

Accordingly, the gate signals GS1 to GS13 are sequentially supplied from the first stage ST1_L to the thirteenth stage ST13_L included in the gate driver GD from the first period T1 to the thirteenth period T13. It outputs and sequentially drives from the first gate line GL1 to the thirteenth gate line GL13.

The thirteenth gate line GL13 is the reference gate line described above, and the first scan line SL1 and the second scan line SL2 are driven when the thirteenth gate line GL13 is driven. That is, in the thirteenth period T13, the thirteenth gate line GL13, the first scan line SL1, and the second scan line SL2 are simultaneously driven. In detail, the thirteenth stage ST13_L of the gate driver GD outputs a thirteenth gate signal GS13 to the thirteenth gate line GL13 in the thirteenth period T13, and supplies the thirteenth gate line GL13 to the thirteenth period. The first stage ST1_R of the scan driver SD outputs the first scan signal SS1 to the first scan line SL1 and the second scan line SL2 at T13.

Accordingly, in the thirteenth period T13, the thirteenth pixel cell PXL13 connected to the thirteenth gate line GL13 receives a data signal from the first data line DL1 to display a real image. The first pixel cell PXL1 connected to the first scan line SL1 receives the AC common voltage Com_ac from the AC common line ACL to display a black image.

Next, in the fourteenth period T14, the fourteenth stage ST14_L included in the gate driver GD outputs the fourteenth gate signal GS14 and supplies it to the fourteenth gate line GL14. Accordingly, the fourteenth pixel cell PXL14 connected to the fourteenth gate line GL14 receives a data signal from the first data line DL1 to display a real image. However, in the fourteenth period T14, the scan driver SD does not output a scan signal.

That is, during the radix period, the radix stages ST1_R, ST3_R, ..., STn-1_R output scan signals SS1, SS3, ... SSn-1 to drive two adjacent scan lines, and In the even-numbered period, the even-numbered stages ST2_R, ST4_R, ..., STn_R output scan signals SS2_R, SS4_R, ... SSn_R, and supply them to the stage located at the front end thereof to disable the stage. In other words, the even-numbered stages ST2_R, ST4_R, ... STn_R output scan signals SS2, SS2, ..., SSn, but do not supply them to the scan line.

After the fourteenth period T14, the pixel cells PXL positioned above the reference gate line (that is, the thirteenth gate line GL13) display a black image, and the pixel cells positioned below the reference gate line PXL) starts to display the real picture.

After a period of time, all of the pixel cells PXL positioned below the reference gate line also display a black image, and the pixel cells PXL positioned above the reference gate line sequentially display a real image. Done. In other words, this process is repeated cyclically.

The scan driver SD may drive two or more scan lines simultaneously in a manner different from that described above. If this is explained in more detail as follows.

FIG. 8 is a diagram illustrating another detailed configuration of the gate driver GD and the scan driver SD of FIG. 2.

As illustrated in FIG. 8, the scan driver SD includes n / 2 stages ST1_R to ST (n / 2) _R and one dummy stage STn + 1_R connected to each other. In this case, the scan driver SD drives the scan lines SL1 through SLn into a plurality of line groups lg1 through lg (n / 2).

That is, each line group lg1 to lg (n / 2) includes a plurality of scan lines.

The number of line groups lg1 to lg (n / 2) and the number of stages ST1_R to ST (n / 2) are equal to each other.

The scan driver SD provided in the present invention may drive at least two scan lines. For convenience of description, the scan driver SD will be described as an example of simultaneously driving two scan lines.

In this case, each line group lg1 to lg (n / 2) includes two scan lines. That is, in order to simultaneously drive f scan lines (f is a natural number), each line group lg1 to lg (n / 2) includes f scan lines.

Here, one side of the scan lines included in the same line group are connected to each other. This connected portion is then connected to the corresponding stage.

Each of the stages ST1_R to STn + 1_R is supplied with two clock pulses among the first to fourth clock pulses CLK1 to CLK4 having a sequential phase difference. In particular, two clock pulse widths between adjacent stages are provided. Clock pulses are supplied. For example, as illustrated in FIG. 7, the first clock pulse CLK1 is supplied to the first stage ST1_R, and the third clock pulse CLK3 is supplied to the second stage ST2_R. Although not shown, the third stage ST3_R is supplied with a first clock pulse CLK1 having a phase difference by two clock pulses from the third clock pulse CLK3 supplied to the second stage ST2_R. That is, the first clock pulse CLK1 is supplied to the odd stage ST1_R, ST3_R, ..., ST (n / 2) -1, ST (n / 2) + 1_R, and the even-numbered stage ST2_R, The third clock pulse CLK3 is supplied to ST4_R, ..., ST (n / 2) _R.

The operation of the scan driver SD configured as described above is as follows.

First, when the second start pulse Vst2 from a timing controller (not shown) is supplied to the first stage ST1_R, the first stage ST1_R is enabled in response to the second start pulse Vst2. do.

Subsequently, the enabled first stage ST1_R receives the first clock pulse CLK1 from the timing controller and outputs a first scan signal SS1, which is then used to scan the first scan line SL1 and the second scan. Supply to line SL2. Then, the first pixel cell PXL1 connected to the first scan line SL1 and the second pixel cell PXL2 connected to the second scan line SL2 are simultaneously driven. That is, the second switching device TR2 provided in the first pixel cell PXL1 and the second switching device Tr2 provided in the second pixel cell PXL2 are turned on. Then, the first pixel cell PXL1 and the second pixel cell PXL2 are supplied with an AC common voltage Com_ac from an AC common line ACL to perform a black image.

Here, the first scan signal SS1 output from the first stage ST1_R is supplied to the second stage ST2_R to enable the second stage ST2_R. The enabled second stage ST2_R receives the third clock pulse CLK3 from the timing controller and outputs a third scan signal SS3, which is then output to the third scan line SL3 and the fourth scan line SL3. SL4). Then, the third pixel cell PXL3 connected to the third scan line SL3 and the fourth pixel cell PXL4 connected to the fourth scan line SL4 are simultaneously driven. That is, the second switching device TR2 provided in the third pixel cell PXL3 and the second switching device Tr2 provided in the fourth pixel cell PXL4 are turned on. Then, the third pixel cell PXL3 and the fourth pixel cell PXL4 are supplied with an AC common voltage Com_ac from an AC common line ACL to perform a black image.

Here, the third scan signal SS3 output from the second stage ST2_R is supplied to the third stage ST3_R to enable the third stage ST3_R. The enabled third stage ST3_R receives the first clock pulse CLK1 from the timing controller and outputs a fifth scan signal SS5, and the fifth scan line SL5 and the sixth scan line SL6). Then, the fifth pixel cell PXL5 connected to the fifth scan line SL5 and the sixth pixel cell PXL6 connected to the sixth scan line SL6 are simultaneously driven. That is, the second switching device TR2 provided in the fifth pixel cell PXL5 and the second switching device Tr2 provided in the sixth pixel cell PXL6 are turned on. Then, the fifth pixel cell PXL5 and the sixth pixel cell PXL6 receive the AC common voltage Com_ac from the AC common line ACL to display a black image.

In addition, the third scan signal SS3 output from the second stage ST2_R is supplied to the first stage ST1_R to disable the first stage ST1_R.

In this manner, the remaining stages (ST4_R to STn_R) sequentially output scan signals and simultaneously apply them to the two scan lines. As a result, two scan lines are sequentially scanned by the simultaneously output scan signal.

Here, as shown in FIG. 7, the first start pulse Vst1 and the second start pulse Vst2 are output once in one frame, wherein the first start pulse Vst1 and the second start pulse Vst2 are output. ) Have different output points. That is, the first start pulse Vst1 is output before the second start pulse Vst2. Accordingly, the gate driver GD operates before the scan driver SD.

For example, as shown in FIG. 7, if the first start pulse Vst1 is output in the start period T0 and the second start pulse Vst2 is output in the twelfth period T12. The gate driver GD is enabled in the start period T0, and the scan driver SD is enabled in the twelfth period T12.

In other words, a first stage ST1_L provided in the gate driver GD is enabled in the start period T0, and a first stage provided in the scan driver SD in the twelfth period T12. (ST1_R) is enabled.

Accordingly, the gate signals GS1 to GS13 are sequentially supplied from the first stage ST1_L to the thirteenth stage ST13_L included in the gate driver GD from the first period T1 to the thirteenth period T13. It outputs and sequentially drives from the first gate line GL1 to the thirteenth gate line GL13.

The thirteenth gate line GL13 is the reference gate line described above, and the first scan line SL1 and the second scan line SL2 are driven when the thirteenth gate line GL13 is driven. That is, in the thirteenth period T13, the thirteenth gate line GL13, the first scan line SL1, and the second scan line SL2 are simultaneously driven. In detail, the thirteenth stage ST13_L of the gate driver GD outputs a thirteenth gate signal GS13 to the thirteenth gate line GL13 in the thirteenth period T13, and supplies the thirteenth gate line GL13 to the thirteenth period. The first stage ST1_R of the scan driver SD outputs the first scan signal SS1 to the first scan line SL1 and the second scan line SL2 at T13.

Accordingly, in the thirteenth period T13, the thirteenth pixel cell PXL13 connected to the thirteenth gate line GL13 receives a data signal from the first data line DL1 to display a real image. The first common pixel cell PXL1 connected to the first scan line SL1 and the second pixel cell PXL2 connected to the second scan line SL2 have an AC common voltage Com_ac from an AC common line ACL. ) Is supplied to display a black image.

Next, in the fourteenth period T14, the fourteenth stage ST14_L included in the gate driver GD outputs the fourteenth gate signal GS14 and supplies it to the fourteenth gate line GL14. Accordingly, the fourteenth pixel cell PXL14 connected to the fourteenth gate line GL14 receives a data signal from the first data line DL1 to display a real image. However, in the fourteenth period T14, the scan driver SD does not output a scan signal.

As described above, after the thirteenth period T13, the pixel cells PXL positioned above the reference gate line (that is, the thirteenth gate line GL13_L) display a black image, and the pixels positioned below the reference gate line. The cells PXL start to display the real picture.

After a period of time, all of the pixel cells PXL positioned below the reference gate line also display a black image. In this case, the pixel cells PXL positioned above the reference gate line may have a first gate line GL1. ) And a pixel cell connected to the second gate line GL2 in order to display a real image. In other words, this process is repeated cyclically.

The gate lines GL1 to GLn and the scan lines SL1 to SLn may be alternately driven once, and at this time, the gate signals GS1 supplied to the gate lines GL1 to GLn. To GSn and the scan signals SS1 to SSn supplied to the scan lines SS1 to SSn are output by being overlapped for a predetermined period of time.

9 is a diagram illustrating a detailed configuration of the gate driver GD and the scan driver SD of FIG. 2, and FIG. 10 illustrates various clock pulses supplied to the gate driver GD and the scan driver SD of FIG. 9. A timing diagram of gate signals output from the gate driver GD and the scan driver SD is shown.

The gate driving circuit and the scan driver SD shown in FIG. 9 are similar to those shown in FIG. However, the stages ST1_L to STn_L of the gate driver GD illustrated in FIG. 9 may be configured to control the first and third clock pulses CLK1 to CLK3 of the first to fourth clock pulses CLK1 to CLK4. The scan driver SD receives the second and fourth clock pulses CLK2 and CLK4 among the first to fourth clock pulses CLK1 to CLK4. Of course, the stages ST1_L to STn_L of the gate driver GD are supplied with the second and fourth clock pulses CLK2 to CLK4, and the scan driver SD receives the first and third clock pulses. CLK1 to CLK3) may be supplied.

The odd stages ST1_L, ST3_L, ..., STn-1_L of the stages ST1_L to STn_L of the gate driver GD receive the first clock pulse CLK1 and receive the gate signals GS1 and GS3. , ..., GSn-1) and the even-numbered stages ST2_L, ST4_L ..., STn_L receive the third clock pulse CLK3 to receive the gate signals GS2, GS4, ..., GSn )

Of the stages ST1_R to STn_R of the scan driver SD, the odd stages ST1_R, ST3_R, ..., STn-1_R receive the second clock pulse CLK2 and receive the scan signals SS1 and SS3. , ..., SSn-1 is outputted, and even-numbered stages ST2_R, ST4_R, ..., STn_R are supplied with the fourth clock pulse CLK4 to receive the scan signals SS2, SS4, ..., Outputs SSn).

Accordingly, the gate signal and the scan signal are alternately output. For example, after the first gate signal GS1 is output, the first scan signal SS1 is output. Next, after the second gate signal GS2 is output, the second scan signal SS2 is output.

On the other hand, the pulse width sections of the clock pulses CLK1 to CLK4 output in the adjacent periods overlap each other.

For example, as shown in FIG. 9, the first 1/3 of the pulse width sections of the q th clock pulse overlap the second 1/3 of the pulse width sections of the q-1 clock pulse, and the q th clock. The second half third of the pulse width section of the pulse (q is a natural number) overlaps with the first third section of the pulse width section of the q + 1 clock pulse.

Although not shown, the first quarter section of the pulse width section of the q th clock pulse overlaps the second quarter section of the pulse width section of the q-1 clock pulse, and the q th clock pulse (q is a natural number). The second half quarter of the pulse width section may overlap the first quarter section of the pulse width section of the q + 1 clock pulse.

The size of the overlapping sections may vary. As the width of the overlapping section occupies more portion in the pulse width section, the period during which the pixel cells remain black increases, and the pixel cell as the size of the overlapping section occupies a smaller portion in the pulse width section is increased. The period of time it stays black is reduced.

The overlapping sections are preferably set to about 25% to 30% of one pulse width section.

When the pulse width sections of the clock pulses CLK1 to CLK4 output in the adjacent periods overlap each other, the gate signals and the scan signals output from the stages supplied with the clock pulses CLK1 to CLK4 are also described above. It has the same waveform as the clock pulse. That is, the pulse width section of the gate signal and the pulse width section of the scan signal which are output in adjacent periods overlap each other.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view for explaining a conventional impulsive driving method

2 illustrates a display device according to an exemplary embodiment of the present invention.

3 is a view for explaining a waveform of the AC common voltage from the AC power supply of FIG.

4 is a diagram illustrating a detailed configuration of a gate driver and a scan driver of FIG. 2;

FIG. 5 is a diagram illustrating timing diagrams of various clock pulses supplied to the gate driver and the scan driver of FIG. 4 and scan pulses output from the gate driver and the scan driver.

FIG. 6 is a diagram illustrating still another detailed configuration of the gate driver and the scan driver of FIG. 2; FIG.

FIG. 7 is a timing diagram of various clock pulses supplied to the gate driver and the scan driver of FIG. 6 and gate signals output from the gate driver and the scan driver.

FIG. 8 is a diagram illustrating another detailed configuration of the gate driver and the scan driver of FIG. 2.

9 is a diagram illustrating a detailed configuration of a gate driver and a scan driver of FIG. 2;

FIG. 10 is a timing diagram of various clock pulses supplied to the gate driver and the scan driver of FIG. 9 and gate signals output from the gate driver and the scan driver.

* Description of the main parts of the drawing:

GD: Gate Driver SD: Scan Driver

DD: Data Driver DL: Data Line

GL: Gate line DCL: DC common line

ACL: AC common line 255: AC power generating unit

200: liquid crystal panel Cst: storage capacitor

Ccl: liquid crystal capacitor Vcom: common electrode

Claims (10)

Pixel cells formed in each pixel region defined by a plurality of gate lines and a plurality of data lines crossing each other; Each pixel cell, A liquid crystal cell for displaying an image; A first switching device for switching data from the data line and supplying the data to the liquid crystal cell according to a gate signal from a gate line; And, And a second switching element for supplying an AC common voltage in the form of AC from the AC common line to the liquid crystal cell in response to a scan signal from the scan line. The method of claim 1, A gate driver supplying a gate signal to the gate lines; And, And a scan driver for supplying scan signals to the scan lines. The method of claim 1, The gate driver sequentially outputs the gate signals and sequentially supplies the gate signals to respective gate lines; The scan driver sequentially outputs the scan signals and sequentially supplies the scan signals to respective scan lines; And, And gate signals from the gate driver and scan signals from the scan driver are alternately output. The method of claim 2, And a pulse width section of the gate signal and the pulse width section of the scan signal overlapping each other for a predetermined period. The method of claim 3, wherein And the second half third section of the pulse width section of the gate signal overlaps the first half section section of the pulse width section of the scan signal. The method of claim 2, The gate driver sequentially outputs the gate signals and sequentially supplies the gate signals to respective gate lines; And the scan driver sequentially outputs scan pulses after the n-th (n is a natural number) gate signal from the gate driver and sequentially supplies them to each scan line. The method of claim 2, The gate driver sequentially outputs the gate signals and sequentially supplies the gate signals to respective gate lines; The scan driver starts outputting a scan pulse after the nth (n is a natural number) gate signal from the gate driver is output; And, The scan driver divides the scan lines into a plurality of line groups including at least two scan lines, simultaneously supplies scan pulses to scan lines in the same line group, and sequentially supplies scan signals for each line group. Liquid crystal display device characterized in that. The method of claim 1, And the AC common voltage is inverted every horizontal period during which one line of pixel cells is driven. The method of claim 1, The AC common voltage alternately represents a high potential voltage and a low potential voltage every period; The high potential voltage is the same as the data signal of the positive highest gradation for displaying the white color; And, Wherein the low potential voltage is the same as the data signal of the highest polarity of negative polarity for displaying the white color. A driving method of a liquid crystal display device comprising pixel cells formed in each pixel region defined by a plurality of gate lines crossing each other and a plurality of data lines. Switching data from the data line according to a gate signal from a gate line and supplying the data to the liquid crystal cell in the pixel cell; And, And switching the AC common voltage in the form of AC from the AC common line according to the scan signal from the scan line and supplying the AC voltage to the liquid crystal cell.

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