KR20160092607A - Shift resistor and Liquid crystal display device using the same - Google Patents

Abstract

The present invention relates to a display device and, specifically, to a shift register and a liquid crystal display device using the same, which can be driven at a low refresh rate by line, has improved image quality when driven at the low refresh rate, and has a minimized bezel size. The shift register comprises a plurality of stages, and each of the stages includes a carry pulse output unit and a scan pulse output unit independently outputting a carry pulse and a scan pulse, respectively. The carry pulse output unit includes a Q node ripple removing path for preventing ripples of a Q node, whereby at least two carry pulses, at least two carrier clock pulses, and at least two clock pulses or scanning are used.

Description

Technical Field [0001] The present invention relates to a shift register and a liquid crystal display using the shift register,

The present invention relates to a display device, and more particularly, to a shift register capable of driving an LRR (Low Refresh Rate) line by line, improving a picture quality defect when driving an LRR (Low Refresh Rate), minimizing a bezel size, And a display device.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device. FIG.

1, a liquid crystal display device generally includes a liquid crystal panel 2 for displaying an image, a gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2, A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2 and a driving circuit 4 for supplying image data RGB inputted from outside to the data driver 4, And a timing controller 8 for generating data control signals GCS and DCS to control the gate and data drivers 6 and 4, respectively.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, And a liquid crystal capacitor Clc. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the thin film transistor, and a common electrode arranged between the pixel electrode and the liquid crystal. The thin film transistor supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn.

The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage SVcom applied to the common electrode and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage Thereby implementing the gradation. At this time, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line sandwiched by the insulating film, and a parasitic capacitor Cgs may be further formed between the source electrode of the thin film transistor and the gate line GL.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, And converts the aligned data Data from the timing controller 8 into an analog voltage, that is, a video signal, using an SOE (Source Output Enable) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period.

The gate driver 6 sequentially drives the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8. [ Specifically, the gate driver 4 outputs a gate start signal (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal Or the like so that the scan pulses of the gate high voltage (VGH) level are sequentially supplied to the gate lines GL1 to GLn. And the gate-low voltage is supplied to the remaining period in which the scan pulse is not supplied.

The timing controller 8 controls the data driver 4 and the gate driver 6 in accordance with image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync and DE from the outside. Specifically, the timing controller 8 arranges image data (RGB) input from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data driver 4. A gate control signal GCS and a data control signal GCS are generated by using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync DCS, and supplies them to the gate driver 6 and the data driver 4, respectively.

The gate driver 6 includes a shift register for sequentially outputting the scan pulses as described above.

The shift register includes a plurality of stages for sequentially outputting scan pulses to the gate lines GL1 to GLn based on a plurality of clock pulses provided from a timing controller.

The shift register may be embedded in a display panel. That is, the display panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register SR can be embedded in the non-display portion (GIP).

The scan pulse generated from each stage is supplied to at least one of the rear stage and the front stage as well as to one of the gate lines.

Each of the stages has a plurality of transistors including a pull-up switching element and a pull-down switching element for outputting a scan pulse and a single bootstrap capacitor .

In recent years, a method of driving a low refresh rate (LRR) that minimizes power consumption has been proposed.

That is, it has been proposed to drive at a frame frequency of 30 Hz to 60 Hz when the full screen displays moving pictures or partial moving pictures, and to drive at a frame frequency of 1 Hz when the full screen displays still pictures.

Driving at a frame frequency of 60 Hz means that the liquid crystal capacitor Clc of each sub pixel is charged 60 times per second. Driving at a frame frequency of 1 Hz is performed once per second to the liquid crystal capacitor Clc of each sub pixel It is a case of charging.

2 (a) shows a case where the gate start pulse Vst and the scan pulse Vg_out1... Vg_outn are shown when driving at a frame frequency of 60 Hz. FIG. 2 (b) Pulse Vst and scan pulse Vg_out1 .... Vg_outn.

When driving at a frequency of 1 Hz, scan pulses of all gates are output at the same 1H timing as when driven at a frequency of 60 Hz, and then held without being driven for the remaining time of one frame. Therefore, the power consumption is small when driving at a frequency of 1 Hz as compared with driving at a frequency of 60 Hz.

However, since the whole area of the display device is driven at the same frequency, low frequency (1 Hz) drive is possible only in the case of a still image in which the entire screen does not change, and low frequency ) Can not be driven, and must be driven at a high frequency (60 Hz). Therefore, unnecessary power is consumed because high frequency driving is performed such that the area occupied by the still image in the entire screen is wider than the area occupied by the moving image.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a shift register capable of driving a display panel with different driving frequencies on a line by line basis as well as preventing ripple of a Q- And a liquid crystal display device using the same.

According to an aspect of the present invention, there is provided a shift register including a carry pulse output unit and a scan pulse output unit for independently outputting a carry pulse and a scan pulse, And at least two carry pulses, at least two carry clock pulses, and at least two scan clock pulses are provided with a node ripple removing path.

In addition, the circuit configuration of each stage is minimized to realize a narrow bezel.

The shift register according to the present invention having the same characteristics as the shifter and the liquid crystal display using the shift register have the following effects.

That is, since a Q-node ripple elimination path for preventing ripple of the Q-node is provided in each stage, it is possible to drive the LRR (Low Refresh Rate) line by line and prevent ripple of the Q-node, .

In addition, since the circuit configuration of each stage is minimized, a narrow bend can be realized.

1 is a circuit diagram showing a driving apparatus of a general liquid crystal display device.
2 (a) and 2 (b) show gate-start pulses and scan pulse timing diagrams according to the drive mode of the conventional liquid crystal display device
3 is a diagram showing a screen configuration for explaining an LRR driving method
Fig. 4 is a circuit diagram of a driving circuit of the display device proposed by the present applicant
FIG. 5 is a timing chart of various signals input and output and output signals when a moving picture is implemented in the shift register of FIG.
FIG. 6 is a timing chart of various signals input and output and output signals when a still image is implemented in the shift register of FIG.
FIG. 7 is a detailed configuration diagram of the shift register SR shown in FIG. 4
Fig. 8 is a diagram showing the configuration of one stage of the shift register shown in Fig. 7
9 is a detailed configuration diagram of the shift register SR according to the first embodiment of the present invention.
10 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention
11 is a detailed configuration diagram of a shift register (SR) according to a second embodiment of the present invention
12 is a diagram showing the configuration of one stage according to the second embodiment of the present invention

A shift register and a liquid crystal display using the same according to the present invention will now be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a LRR driving method according to an embodiment of the present invention.

In order to reduce unnecessary power, the applicant of the present invention has applied for a shift register of a gate driver for driving to display a moving image and a still image partly in an image displayed on the entire screen, as described in Fig. 3 (Patent Application No. 10-2014-0177397, filed on Dec. 10, 2014, entitled " Method of driving display device and display device ").

FIG. 4 is a diagram illustrating a shift register according to an embodiment of the present invention, FIG. 5 is a timing chart of various signals input and output and output signals when a moving picture is implemented in the shift register of FIG. 4 is a timing chart of various signals input and output and output signals when a still image is implemented in the shift register of FIG.

As shown in Fig. 4, the shift register of the paired gate driver of the present invention includes i carry clock pulses C-CLK_ # from the timing controller TC and j scan clock pulses S- CLK_ #). Specifically, the timing controller TC sequentially outputs the carry clock pulses C-CLK_ # of i (i is a natural number greater than 1), and j (j is a natural number greater than 1) Clock pulses S-CLK_ #, and supplies them to the shift register SR. In other words, the timing controller TC outputs the clock pulses for the i-th phase and the clock pulses for the j-th scan. As an example, in FIGS. 5 and 6, six-phase carry clock pulses C-CLK_1 to C-CLK_6 having different phase differences and six-phase scan clock pulses S- CLK_1 to S-CLK_6. However, the present invention is not limited to this, and can be configured in various ways, such as four-phase and eight-phase.

As shown in FIGS. 5 and 6, the pulse widths of the i carry clock pulses do not overlap each other, and the pulse widths of the j scan clock pulses do not overlap each other. However, as another embodiment, the output timings of the i carry clock pulses may be adjusted so that the pulse widths between the carry clock pulses output in the adjacent period overlap each other, and the output clock pulses The output timings of the i carry clock pulses may be adjusted so that the pulse widths between the carry clocks overlap each other.

The shift register SR sequentially generates a plurality of outputs on the basis of i clock pulses for carry and j clock pulses for scanning provided from the timing controller TC, And a plurality of stages for sequentially generating such a plurality of outputs. The output generated from each stage is composed of a pair of carry pulses and scan pulses that correspond to each other. In a pair of carry pulses and scan pulses, the carry pulse is supplied to at least one of the subsequent stage and the preceding stages, while the scan pulse is supplied to one of the gate lines.

At this time, the timing controller TC controls a scan clock pulse so that a scan pulse of a different driving frequency is outputted to the gate lines corresponding to the still image and the gate lines corresponding to the still image among the displayed images .

For example, in the timing controller TC, as shown in FIG. 5, a plurality of scan clock pulses (hereinafter referred to as " scan pulse pulses ") are applied to stages for outputting scan pulses to gate lines, (S-CLK_1 to S-CLK_6) at 60 Hz.

However, as shown in FIG. 6, the timing controller TC is provided with a plurality of scan clock pulses S (S) for outputting scan pulses to the gate lines corresponding to the still image among the displayed images, -CLK_1 to S-CLK_6) at 1 Hz.

A more specific method will be described later.

7 is a detailed configuration diagram of the shift register SR shown in FIG.

The shift register SR desired to be written out of the present invention includes a plurality of stages ST_n-2 to ST_n + 2, as shown in Fig. Here, each stage includes a total of six terminals I, II, III, IV, V, VI.

The carry clock pulse of any one of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 is applied to the fourth terminal IV of each stage, (Or one of the carry pulses CRPn-2 to CRPn + 2) through the second terminal II (hereinafter referred to as carry pulse output terminal COT) to which the carry pulse (or the start pulse Vst) do.

In addition, any one of scan clock pulses (S-CLK_1 to S-CLK_6) for the plurality of scan clock pulses is applied to the fifth terminal (V) of each stage, and the sixth terminal The output carry pulse is applied and one scan pulse (one of the scan pulses SCPn-2 to SCPn + 2) is output through the third terminal III (hereinafter, referred to as a scan pulse output terminal SOT).

Therefore, the carry pulse and the scan pulse as described above are independently output at the second and third terminals of each stage.

If the clock pulses C-CLK_1 to C-CLK_6 for six phases and the clock pulses S-CLK_1 to S-CLK_6 for scanning are provided to the shift register as shown in Figs. 5 and 6, For example, the 6k + 1th (k is a natural number including 0) stages among the stages including the (n-2) th to (n + 2) th stages (ST_n-2 to ST_n + 2) (C-CLK_1) and the first scan clock pulse (S-CLK_1), the 6k + 2 < th > stages output the second carry clock pulse (C- The 6k + 3 < th > stages output the third carry clock pulse C-CLK_3 and the third scan clock pulse S-CLK_3, the 6k + 4th stages carry the fourth carry clock pulse C- (6K + 5) -th stages carry a clock pulse (C-CLK_5) for a fifth carry and a clock pulse (S-CLK_5) for a fifth scan, Clock pulse for sixth carry (C-CLK_6) and a sixth scan clock pulse (S-CLK_6).

Each stage controls the operation of the stage located at the rear end of the stage and the stage located at the front end using a carry pulse. In addition, each stage drives a gate line connected to itself using a scan pulse. On the other hand, although not shown, a dummy stage for supplying a carry pulse to the final stage may further be provided at a rear stage of the last stage positioned at the end. Depending on the configuration of the shift register SR, this dummy stage may be plural instead of one. Since this dummy stage is not connected to the gate line, the scan pulse is not output.

Such a shift register SR may be embedded in the display panel. That is, the display panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register SR can be embedded in the non-display portion (GIP).

8 is a diagram showing the configuration of any one stage according to the present invention.

As shown in Fig. 8, each stage has a carry pulse output section 10 and a scan pulse output section 20 separately.

The carry pulse output section 10 of each stage (n-th stage) outputs a carry pulse (CRP_n + 1) or a start pulse (Vst) output from the previous stage) (C-CLK_ #) of one of the plurality of carry clock pulses (C-CLK_1 to C-CLK_6) is received by the node controller 11 for controlling the Q node and the QB node And a carry pulse output unit 12 for outputting a carry pulse CRP_n according to the voltages of the Q node and the QB node of the node control unit 11. [

The scan pulse output section 20 of each stage (n-th stage) receives the carry pulse CRP_n-1 or the start pulse Vst output from the previous stage and the carry pulse CRP_n + CLK_ #) of any one of the plurality of scan clock pulses (S-CLK_1 to S-CLK_6) for controlling the Q node and the QB node according to the scan clock pulses (S- And a scan pulse output unit 22 for outputting a scan pulse SCP_n according to the voltages of the Q and QB nodes of the node controller 21. [

Therefore, when the moving image is partially present in the still image, the gate lines corresponding to the moving image are driven at 60 Hz, and the gate lines corresponding to the remaining still images are driven at 1 Hz.

That is, in order to drive the gate lines corresponding to the moving image at 60 Hz, as shown in FIG. 5, in the timing controller TC, the carry clock pulses C-CLK_1 to C-CLK_6 ) And j scan clock pulses (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz to the corresponding stage of the gate driver.

In order to drive the gate lines corresponding to the still image at 1 Hz, as shown in FIG. 6, clock pulses (C-CLK_1 to C-CLK_6) for i-phase in the timing controller (TC) To the corresponding stage of the gate driver at a frequency of 60 Hz, and the scan clock pulses (S-CLK_1 to S-CLK_6) on the j-th stage output at a frequency of 1 Hz.

Thus, regardless of the moving image and the still image, the timing controller TC outputs the clock pulses C-CLK_1 to C-CLK_6 for the i-th phase at 60 Hz, CLK_1 to S-CLK_6 at the j-th phase in the section where the still image is driven, and outputs the scanning clock pulses S-CLK_1 to S-CLK_6 at the j- ) At a frequency of 1 Hz, so that even if there is a part of motion image, it is possible to drive a low frequency by gate lines (blocks).

However, in the present invention, as shown in Fig. 8, no path for removing the ripple of the Q node is formed in the carry pulse output section 10 and the scan pulse output section 20, Image quality failure due to ripple generation may occur.

That is, a ripple is generated in the Q-node by the carry clock pulse C-CLK (n) and the scan clock pulse S-CLK (n) supplied to the output unit, There is not formed a path for eliminating the ripples, so that image quality failure due to ripple generation may occur.

The present invention can drive the display panel in different driving frequencies on a line-by-line basis, and each stage can form a path capable of eliminating ripple of the Q node to prevent ripple of the Q node And to provide a shift register capable of improving image quality.

9 is a detailed configuration diagram of a shift register SR according to the first embodiment of the present invention.

The shift register SR according to the first embodiment of the present invention includes a plurality of stages ST_n-2 to ST_n + 2, as shown in FIG.

In each stage, three carry clock pulses among the plurality of carry clock pulses (C-CLK_1 to C-CLK_6) and carry pulses (or start pulse (Vst)) output from the previous stage and the previous stage , Three scan clock pulses among the plurality of scan clock pulses S-CLK_1 to S-CLK_6, and a carry pulse output from the next stage are applied. Then, one carry pulse is outputted through the carry pulse output terminal (COT), and one scan pulse is outputted through the scan pulse output terminal (SOT).

The carry clock pulses C-CLK_1 to C-CLK_6 and scan clock pulses S-CLK_1 to S-CLK_6 on the six phases are the same as those described with reference to FIGS. 5 and 6, The carry clock pulse and the three scan clock pulses are applied and the three carry pulses outputted at the front and rear ends are applied.

Each stage controls the operation of the stage located at the rear end of the stage and the stage located at the front end using a carry pulse. In addition, each stage drives a gate line connected to itself using a scan pulse. On the other hand, although not shown, a dummy stage for supplying a carry pulse to the final stage may further be provided at a rear stage of the last stage positioned at the end. Depending on the configuration of the shift register SR, this dummy stage may be plural instead of one. Since this dummy stage is not connected to the gate line, the scan pulse is not output.

10 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention.

As shown in Fig. 10, each stage includes a carry pulse output section 10 and a scan pulse output section 20 separately.

The carry pulse outputting section 10 of each stage (n-th stage) outputs the carry pulse CRP_n-1, CRP_n-2 (or the start pulse Vst) output from the previous stage, (N-1) according to any one of the carry clock pulses (CRP_n + 2) and the carry clock pulses (C-CLK_1 to C-CLK_6) CLK_ (n) and C-CLK_ (n + 2) out of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 and supplies the two carry clock pulses C- And a carry pulse output section 12 for outputting a carry pulse CRP_n in accordance with the voltage of the Q node of the memory cell array 11.

The scan pulse output section 20 of each stage (n-th stage) receives the carry pulses CRP_ (n-1), C-CRP_ (n-2)) or the start pulse Vst (N-1) of the scan pulse (CRP_n + 2) output from the subsequent stage and the scan clock pulse S-CLK_ (n-1) of the plurality of scan clock pulses S- CLK_ (n), S-CLK_ (n) of the plurality of scanning clock pulses S-CLK_1 to S-CLK_6, and a node controller 21 for controlling the Q- (n + 2)) and outputting a scan pulse (SCP_n) according to the voltage of the Q node of the node controller 21. [

Here, the circuit configuration of the carry pulse output unit 10 and the scan pulse output unit 20 will be described in more detail.

10, the node control unit 11 of the carry pulse output unit 10 outputs the carry pulse {CRP_ (2)) output from the carry pulse output unit 10 of the (n-2) (n + 2) th stage (ST_n + 2), a first switching device (T1) controlled in accordance with the carry pulse (CR_ A second switching element T3n controlled by the carry pulse CRP_ (n + 2) output from the output section 10 to discharge the node Q, and a plurality of carry clock pulses (N-1) th stage ST_ (n-1), which is controlled according to any one of {C-CLK -1)} to the node Q and a fourth switching element Tm controlled by the reset signal Reset or the start signal Vst to discharge the node Q T3r.

The output unit 12 of the carry pulse output unit 10 includes a capacitor C for bootstrapping the voltage of the Q node and a plurality of capacitors C controlled by the voltage of the node Q, A fifth switching element T6 for outputting any one of the carry clock pulses {C-CLK (n)} to the output terminal, and a fifth switching element T6 for outputting any one of the carry clock pulses {C-CLK (n + 2)} to discharge the output terminal, and a seventh switching device T7d.

The scan pulse output unit 20 is also configured as the carry pulse output unit 10, except that a scan clock pulse is applied instead of a carry clock pulse.

That is, the node control unit 21 of the scan pulse output unit 20 outputs the carry pulse CRP_ (n-2) output from the carry pulse output unit 10 of the (n-2) (N + 2) th stage (ST_n + 2), a first switching element T1 which is controlled to charge the node Q with the carry pulse {CRP_ A second switching element T3n controlled in accordance with the carry pulse {CRP_ (n + 2)} to discharge the node Q, and a second switching element T3n, (N-1)} output from the carry pulse outputting section 10 of the (n-1) th stage ST_ (n-1) by controlling the carry pulse {CRP A third switching element T3c for charging the node Q and a fourth switching element T3r for controlling the node Q in accordance with the reset signal Reset or the start signal Vst.

The output unit 22 of the scan pulse output unit 20 includes a capacitor C for bootstrapping a voltage of the Q node and a plurality of transistors Q1 to Qn that are controlled in accordance with the voltage of the node Q, A fifth switching element T6 for outputting one of the scan clock pulses {S-CLK (n)} to the output terminal, and a fifth switching element T6 for outputting any one of {S-CLK (n + 2)} to discharge the output terminal, and a seventh switching device T7d.

The operation of the n-th stage according to the first embodiment of the present invention will now be described.

First, the operation of the carry pulse output unit 10 will be described as follows.

when the high pulse of the carry pulse CRP_ (n-2) outputted from the carry pulse outputting section 10 of the (n-2) th stage ST_ (n-2) is inputted to the first switching element T1, The first switching device T1 is turned on to charge the node Q with the carry pulse CRP_ (n-2). [0064] Then, one of the plurality of carry clock pulses having different phases When the high pulse of the pulse {C-CLK (n + 2)} is inputted to the sixth switching element T7c, the sixth switching element T7c is turned on to discharge the output terminal.

In this state, one clock pulse {C-CLK (n-1)} and the n-1th stage ST_ (n-1) of the plurality of carry clock pulses having different phases are input to the third switching element T3c The carry pulse {CRP_ (n-1)} output from the carry pulse outputting section 10 of the first carry clock pulse C-CLK (n-1) The switching element T3c is turned on to charge the node Q with the carry pulse CRT_ (n-1), and the node Q maintains a high state.

When the node Q is kept in the high state, the fifth switching element T6 is turned on and bootstrapped by the capacitor C, and the different phases inputted to the source terminal of the fifth switching element T6 One carry clock pulse {C-CLK (n)} among the plurality of carry clock pulses having the carry pulse CRP_n is output to the output terminal.

Then, the fourth switching element T3r is turned on by the reset signal or the start signal to discharge the node Q, and one clock pulse {C-CLK (n + 2) Is input to the sixth switching element T7c, the sixth switching element T7c is also turned on to discharge the output terminal.

The operation of the scan pulse output unit 20 operates in the same manner as the carry pulse output unit 10 except that a plurality of scan clock pulses S-CLK_1 to S- CLK_6), the operation of the scan pulse output section 20 is omitted.

5 and 6, regardless of the motion image and the still image, the timing controller TC generates clock pulses C-CLK_1 to C-CLK_6 for the i-th phase, (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz in a period in which the moving image is driven, and outputs the j-th scan clock pulses (S-CLK_1 to S- Since the pulses S-CLK_1 to S-CLK_6 are outputted at a frequency of 1 Hz, low frequency driving is possible for each gate line (block) even if motion picture is partially present.

(C-CLK (n-1)} and (n-1) of the plurality of carry clock pulses indicating different phases regardless of whether the moving picture or the still picture is driven, are supplied to the third switching element T3c. The carry pulse CRP_ (n-1) output from the carry pulse output section 10 of the first stage ST_ (n-1) is applied at 60 Hz to form a path for eliminating ripple that may occur in the Q node Therefore, it is possible to provide a shift register capable of improving image quality.

In FIG. 10, the carry pulse output unit 10 and the scan pulse output unit 20 include the node controllers 11 and 21, respectively, but they can be commonly used.

That is, as described in FIG. 7 of the patent application (Patent Application No. 10-2014-0177397) desirous to be output by the present applicant, any one stage (nth stage) The carry pulse CRP_n-1, CRP_n-2 (or the start pulse Vst), the carry pulse CRP_n + 2 outputted from the next stage, and the carry clock pulses C-CLK_1 to C- A node controller 11 for controlling a Q node in accordance with one carry clock pulse C-CLK_ (n-1), and two carry outs of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 A carry pulse output section 12 which receives the clock pulses C-CLK_ (n) and C-CLK_ (n + 2) for outputting the carry pulse CRP_n according to the voltage of the Q node of the node control section 11, CLK_ (n) and S-CLK_ (n + 2) of the plurality of scanning clock pulses S-CLK_1 to S-CLK_6, and outputs the two scanning clock pulses S- 11) Q-furnace And a scan pulse output unit 22 for outputting the scan pulse SCP_n according to the voltage of the scan electrode.

Since the circuit configuration of each stage can be further reduced, a narrow bezel can be realized.

In the shift register of the first embodiment of the present invention as described with reference to FIGS. 9 and 10, since the third switching element T3c forms a path for removing ripples that may be generated at the Q node, image quality can be improved , A pulse of 60 Hz is always applied to the gate electrode and the source electrode of the third switching device T3c, so that the third switching device T3c may be deteriorated to fail to form a path for removing the ripple of the Q node have.

Therefore, the third switching element T3c may not be used and a path may be formed to remove ripple that may be generated at the Q node.

An embodiment in which a path for removing ripple that may occur in the Q node is separately formed will now be described.

FIG. 11 is a detailed configuration diagram of a shift register SR according to a second embodiment of the present invention, and FIG. 12 is a diagram illustrating the configuration of one stage according to the second embodiment of the present invention.

The shift register SR according to the second embodiment of the present invention includes a plurality of stages ST_n-2 to ST_n + 2, as shown in FIG.

In each stage, two carry clock pulses among the plurality of carry clock pulses C-CLK_1 to C-CLK_6, a carry pulse (or a start pulse Vst) output from the previous stage, Two scan clock pulses among the scan clock pulses S-CLK_1 to S-CLK_6, and a carry pulse output from the next stage are applied. Then, one carry pulse is outputted through the carry pulse output terminal (COT), and one scan pulse is outputted through the scan pulse output terminal (SOT).

The carry clock pulses C-CLK_1 to C-CLK_6 and the scan clock pulses S-CLK_1 to S-CLK_6 on the six phases are the same as those described with reference to FIGS. 5 and 6, There are differences in that a carry clock pulse and two scan clock pulses are applied and two carry pulses output at the front and rear ends are applied.

Each stage controls the operation of the stage located at the rear end of the stage and the stage located at the front end using a carry pulse. In addition, each stage drives a gate line connected to itself using a scan pulse. On the other hand, although not shown, a dummy stage for supplying a carry pulse to the final stage may further be provided at a rear stage of the last stage positioned at the end. Depending on the configuration of the shift register SR, this dummy stage may be plural instead of one. Since this dummy stage is not connected to the gate line, the scan pulse is not output.

Each stage according to the second embodiment of the present invention has a carry pulse output section 10 and a scan pulse output section 20 separately as shown in FIG.

The carry pulse output section 10 of each stage (n-th stage) receives the carry pulse CRP_n-2 (or the start pulse Vst) output from the previous stage and the carry pulse CRP_n + 2 CLK_ (n), C-CLK_ (n), and C-CLK_ (n) among the plurality of carry clock pulses C-CLK_1 to C-CLK_6, and a carry pulse output unit 12 for receiving a carry pulse (n + 2) and outputting a carry pulse (CRP_n) according to the voltage of the Q node of the node control unit 11. [

The scan pulse output section 20 of each stage (n-th stage) outputs a carry pulse C-CRP_ (n-2) (or a start pulse Vst) CLK_1 to S-CLK_6) of the plurality of scan clock pulses (S-CLK_1 to S-CLK_6) for controlling the Q node according to the carry pulse (CRP_n + and a scan pulse output unit 22 receiving the scan pulse SCP_n and the scan pulse SCP_n according to the voltage of the Q node of the node control unit 21.

Here, the circuit configuration of the carry pulse output unit 10 and the scan pulse output unit 20 will be described in more detail.

12, the node control unit 11 of the carry pulse output unit 10 outputs the carry pulse {CRP_ (CR-1)) output from the carry pulse output unit 10 of the (n-2) (n + 2) th stage (ST_n + 2), a first switching device (T1) controlled in accordance with the carry pulse (CR_ A second switching element T3n controlled in accordance with the carry pulse CRP_ (n + 2) output from the output section 10 to discharge the node Q, and a reset signal Reset or a start signal Vst, A third switching element T3r which is controlled in accordance with a control signal to discharge the node Q, a capacitor C2 which stores a discharge signal inputted from the outside, A fourth switching device T3c for forming a path for eliminating ripple generated in the node Q, and a fourth switching device T3b for storing the capacitor C2 in accordance with the voltage of the Q node Further included is a fifth switch (T3q) to discharge the discharge signal.

The output unit 12 of the carry pulse output unit 10 includes a capacitor C1 for bootstrapping the voltage of the Q node and a plurality of capacitors C1 and C2 which are controlled in accordance with the voltage of the node Q, A sixth switching device T6 for outputting any one of the carry clock pulses {C-CLK (n)} to the output stage, and a sixth switching device T6 for outputting any one of the carry clock pulses {C-CLK and a seventh switching device T7c and an eighth switching device T7d which are controlled in accordance with a control signal (n + 2) to discharge the output terminal.

The scan pulse output unit 20 is also configured as the carry pulse output unit 10, except that a scan clock pulse is applied instead of a carry clock pulse.

That is, the node control unit 21 of the scan pulse output unit 20 outputs the carry pulse CRP_ (n-2) output from the carry pulse output unit 10 of the (n-2) (N + 2) th stage (ST_n + 2), a first switching element T1 which is controlled to charge the node Q with the carry pulse {CRP_ A second switching element T3n which is controlled in accordance with the carry pulse CRP_ (n + 2) and discharges the node Q, and a second switching element T3n controlled by the reset signal Reset or the start signal Vst, A third switching element T3r for discharging a discharge signal from the node Q in response to a discharge signal stored in the capacitor C2, A fourth switching element T3c for forming a path for removing generated ripple and a fourth switching element T3b for discharging the discharge signal stored in the capacitor C2 according to the voltage of the Q node And a fifth switching element T3q.

The output unit 22 of the scan pulse output unit 20 includes a capacitor C1 for bootstrapping the voltage of the Q node and a plurality of capacitors C1 to C4 controlled by the voltage of the node Q, A sixth switching element T6 for outputting one of the scan clock pulses {S-CLK (n)} to the output terminal, and a sixth switching element T6 for outputting any one of {S-CLK and a seventh switching device T7c and an eighth switching device T7d which are controlled in accordance with a control signal (n + 2) to discharge the output terminal.

12, the carry pulse output unit 10 and the scan pulse output unit 20 are provided separately with the node controllers 11 and 21, respectively, but they can be commonly used.

That is, as described in FIG. 7 of the patent application (Patent Application No. 10-2014-0177397) desirous to be output by the present applicant, any one stage (nth stage) A node controller 11 for controlling a Q node in accordance with a carry pulse CRP_n-2 (or a start pulse Vst) output from the next stage and a carry pulse CRP_n + 2 output from the next stage, CLK_ (n + 2) and the carry pulse CRP_n (n + 2) according to the voltage of the Q node of the node control unit 11 in response to the carry clock pulses C- CLK_ (n), S-CLK_ (n), and S-CLK_ (n) out of the plurality of scan clock pulses S-CLK_1 to S- +2), and outputs a scan pulse SCP_n according to the voltage of the Q node of the node controller 11. The scan pulse output unit 22 may include a scan pulse output unit 22,

Likewise, since the circuit configuration of each stage can be further reduced, it is possible to realize a narrow bezel.

The operation of the n-th stage according to the second embodiment of the present invention will now be described.

First, the operation of the carry pulse output unit 10 will be described as follows.

when the high pulse of the carry pulse CRP_ (n-2) outputted from the carry pulse outputting section 10 of the (n-2) th stage ST_ (n-2) is inputted to the first switching element T1, The first switching device T1 is turned on to charge the node Q with the carry pulse CRP_ (n-2). [0064] Then, one of the plurality of carry clock pulses having different phases When the high pulse of the pulse {C-CLK (n + 2)} is input to the seventh switching device T7c, the seventh switching device T7c is turned on to discharge the output terminal.

When the node Q maintains the high state, the sixth switching element T6 is turned on and bootstrapped by the capacitor C1, and the sixth switching element T6 is turned on, One carry clock pulse {C-CLK (n)} among a plurality of carry clock pulses having different phases is output as an output terminal as a carry pulse (CRP_n).

When the carry pulse CRP_ (n + 2) in the high state is output from the carry pulse output section 10 of the (n + 2) th stage ST_n + 2, the second switching element T3n is turned on, Q) and one clock pulse {C-CLK (n + 2)} of a plurality of carry clock pulses is input to the seventh switching element T7c, the sixth switching element T7c is also turned on The third switching element T3r is turned on by the reset signal or the start signal to discharge the node Q.

The operation of the scan pulse output unit 20 operates in the same manner as the carry pulse output unit 10 except that a plurality of scan clock pulses S-CLK_1 to S- CLK_6), the operation of the scan pulse output section 20 is omitted.

5 and 6, regardless of the motion image and the still image, the timing controller TC generates clock pulses C-CLK_1 to C-CLK_6 for the i-th phase, (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz in a period in which the moving image is driven, and outputs the j-th scan clock pulses (S-CLK_1 to S- Since the pulses S-CLK_1 to S-CLK_6 are outputted at a frequency of 1 Hz, low frequency driving is possible for each gate line (block) even if motion picture is partially present.

In this case, when a discharge signal is inputted to the capacitor C2 from the outside, the capacitor C2 is charged, and the fourth switching device T3c is turned on according to the voltage charged in the capacitor C2. And is turned on to form a path for removing the ripple generated at the node Q. The fifth switching device T3q is turned on according to the voltage of the Q node to discharge the discharge signal stored in the capacitor C2.

Therefore, one discharge signal is applied to the capacitor C2 when driving the stereoscopic image, and two discharge signals are applied to the capacitor C2 when the still image is driven.

As described above, since the path for removing the ripple that may be generated in the Q node is separately formed, deterioration of the switching element can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Claims (9)

A plurality of stages,
In each stage,
Two carry pulses (or a start pulse) output from two front stage stages, one carry pulse output from the next stage, and three carry clock pulses among a plurality of carry clock pulses, A carry pulse output unit for outputting the carry pulse,
Two carry pulses (or a start pulse) output from two front stage stages, one carry pulse output from the next stage, and three scan clock pulses among a plurality of scan clock pulses, And a scan pulse output section for outputting a scan pulse. The method according to claim 1,
The carry pulse output section of the n < th >
a first switching element controlled according to a carry pulse output from a carry pulse output part of the (n-2) -th stage to charge the node Q with the carry pulse,
a second switching element controlled according to a carry pulse output from a carry pulse output part of an (n + 2) -th stage to discharge the node (Q)
A third switching element which is controlled according to any one of the plurality of carry clock pulses to charge the node Q with a carry pulse output from the carry pulse output part of the (n-1)
A fourth switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q)
A capacitor for bootstrapping the voltage of the Q node,
A fifth switching device controlled by a voltage of the node (Q) and outputting one of the plurality of carry clock pulses to an output terminal;
And a sixth switching element controlled according to any one of the plurality of carry clock pulses to discharge the output terminal. The method according to claim 1,
The scan pulse output section of the n < th >
a first switching element controlled according to a carry pulse output from a carry pulse output part of the (n-2) -th stage to charge the node Q with the carry pulse,
a second switching element controlled according to a carry pulse output from a carry pulse output part of an (n + 2) -th stage to discharge the node (Q)
A third switching element which is controlled according to any one of the plurality of scan clock pulses so as to charge the node Q with a carry pulse output from a carry pulse output part of the (n-1)
A fourth switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q)
A capacitor for bootstrapping the voltage of the Q node,
A fifth switching device controlled according to a voltage of the node (Q) to output one of the plurality of scanning clock pulses to an output terminal;
And a sixth switching element controlled according to any one of the plurality of scan clock pulses to discharge the output terminal. A plurality of stages,
In each stage,
Two carry pulses (or a start pulse) output from two front stage stages, and one carry pulse and a carry clock pulse (C-CLK_ a node controller for controlling the Q node according to the n-1,
A carry pulse output unit for receiving two carry clock pulses among the plurality of carry clock pulses and outputting a carry pulse (CRP_n) according to a voltage of a Q node of the node control unit;
And a scan pulse output unit for receiving two scan clock pulses among a plurality of scan clock pulses and outputting a scan pulse according to a voltage of a Q node of the node control unit. A plurality of stages,
In each stage,
One carry pulse (or start pulse) output from the front end stage, and one carry pulse from the rear stage and two carry clock pulses from the plurality of carry clock pulses and outputs a carry pulse An output section,
One carry pulse (or start pulse) output from the front stage, one carry pulse output from the rear stage, and two scan clock pulses among the plurality of scan clock pulses and outputs a scan pulse And an output section. 6. The method of claim 5,
In the carry pulse output section,
A first switching element controlled in accordance with a carry pulse output from a carry pulse output part of the front end stage to charge the node Q with the carry pulse,
A second switching element controlled in accordance with a carry pulse output from the carry pulse output part of the rear stage to discharge the node Q,
A third switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q)
A first capacitor for storing an external discharge signal,
A fourth switching device for forming a path for removing a ripple generated in the node (Q) according to a discharge signal stored in the second capacitor,
A fifth switching element for discharging the discharge signal stored in the first capacitor according to the voltage of the Q node,
A second capacitor for bootstrapping the voltage of the Q node,
A sixth switching device controlled by a voltage of the node (Q) and outputting one of the plurality of carry clock pulses to an output terminal;
And a seventh switching element controlled according to any one of the plurality of carry clock pulses to discharge the output terminal. 6. The method of claim 5,
Wherein the scan pulse output unit comprises:
A first switching element controlled in accordance with a carry pulse output from a carry pulse output part of the front end stage to charge the node Q with the carry pulse,
A second switching element controlled in accordance with a carry pulse output from the carry pulse output part of the rear stage to discharge the node Q,
A third switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q)
A first capacitor for storing an external discharge signal,
A fourth switching element for forming a path for removing a ripple generated in the node (Q) according to a discharge signal stored in the first capacitor,
A fifth switching element for discharging the discharge signal stored in the second capacitor according to the voltage of the Q node,
A second capacitor for bootstrapping the voltage of the Q node,
A sixth switching device controlled according to a voltage of the node (Q) to output one of a plurality of scanning clock pulses to an output terminal;
And a seventh switching element controlled according to any one of the plurality of scanning clock pulses to discharge the output terminal. A plurality of stages,
In each stage,
A node controller for controlling the Q node according to a carry pulse (or a start pulse Vst) output from the front stage and a carry pulse output from the rear stage,
A carry pulse output unit for receiving two carry clock pulses among a plurality of carry clock pulses and outputting a carry pulse according to a voltage of a Q node of the node control unit;
And a scan pulse output unit for receiving two scan clock pulses among a plurality of scan clock pulses and outputting a scan pulse according to a voltage of a Q node of the node control unit. A display panel having a plurality of gate lines and a plurality of data lines arranged to cross the gate lines;
A gate driver for sequentially driving the plurality of gate lines by using the shift register of claim 1, claim 4, claim 5 or claim 8;
Wherein a plurality of carry clock pulses and a plurality of scan clock pulses are supplied to the gate driver, and when a still image is partially present on the motion picture image, driving of the gate lines corresponding to the motion picture is performed for the plurality of carry And supplying clock pulses and a plurality of scanning clock pulses to a frequency for driving the moving image, and driving the gate lines corresponding to the still image to supply the plurality of carry clock pulses to a frequency for driving the moving image, And a timing controller for supplying a plurality of scanning clock pulses at a frequency lower than a frequency for driving the moving image.

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