JP2005208407A - Image output device and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image output device which suppresses an increase in driving circuit scale and lowers cost while maintaining image display of high gradations and high quality, in an image display device which divides an image of one frame into a plurality of sub-frames and performs sequential time-division display by the sub-frames. <P>SOLUTION: The image output device equipped with a sub-frame generating means (a decoder 5, a write control circuit 6, and sub-frame memories 1 to 4) for dividing pixel data of one frame into a plurality of sub-frames and sequentially outputting the sub-frames is further equipped with a field data generating means (sub-frame memories 1 to 4, a read control circuit, a +1 circuit 8, a decision circuit 9, and a selecting circuit 10) for dividing the output period of each sub-frame into a plurality of fields in time and generating and outputting output pixel data sequentially by the fields. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention divides pixel data for one frame into a plurality of subframes, and includes an image output device including subframe generation means for sequentially outputting each subframe, and the image output device, and a plurality of images. The present invention relates to an image display device that performs time-division display by dividing into sub-frames.

  In recent years, the resolution of a display image has been increased more and more due to a dramatic increase in the processing capacity of a computer, and accordingly, there is an increasing demand for higher resolution in an image display apparatus such as a projector. However, for example, in projectors and the like, the resolution of the spatial light modulation element for displaying an image has not kept up with the demand, and various techniques for realizing high resolution have been proposed. As an example, Patent Document 1 discloses a projector having optical path shifting means (herein, “shift” is synonymous with “deflection” (hereinafter the same)).

In this prior art, an optical path modulation element as an optical path shift means comprising a polarization direction control panel and a crystal plate is provided in a projection optical path from a display liquid crystal panel as a spatial light modulation element, and the polarization direction control panel is operated. This changes the polarization direction of the light incident on the quartz plate. The crystal plate is arranged with its crystal axis tilted with respect to the optical axis of the projection light, and the optical path shifts for polarized light that vibrates in the tilt direction, and no shift occurs for orthogonal polarized light. .
In this prior art, one frame image is composed of two or four fields (here, “field” is synonymous with “subframe” (hereinafter the same)), and each field is displayed on the liquid crystal panel. In addition to the time-division display, the polarization direction control panel is operated in synchronization with the display, and the optical path is shifted by one pitch or less of the pixels, thereby displaying an image with a resolution higher than that of the liquid crystal panel.

  In many projectors including the above-described conventional technology, a liquid crystal display panel is used as a spatial light modulation element for forming a projection image. In general, a liquid crystal display panel forms an image by applying a voltage corresponding to pixel data to be displayed on each pixel. FIG. 13 shows a configuration example of a conventional liquid crystal display panel.

  In FIG. 13, (P1,1) to (Py, x) represent each pixel. Each pixel has a pixel driving transistor and a storage capacitor, and constitutes an active matrix circuit as a whole. The gate driver sequentially selects pixels in units of one line in the horizontal (x) direction. The source driver outputs video data of an analog voltage input in synchronization with the selected line to each corresponding pixel. The gates of the pixel driving transistors in the selected line are turned on, and video data output from the source driver is written into the storage capacitor. A liquid crystal is sandwiched between a counter substrate on which an active matrix circuit, a source driver, and a gate driver are formed, and a counter substrate. The optical state of each pixel is controlled based on the written video data, and an image as a whole is displayed. It is formed.

  In many cases, pixel data is generated as digital data, and a voltage applied to each pixel is generated by converting digital pixel data into an analog signal by a digital / analog converter (D / A converter). . On the other hand, with the recent increase in image resolution, pixel data transfer has been further accelerated. As an effective means for that purpose, there is a method in which pixel data is transferred to a display panel as digital data and converted into an analog signal by incorporating a D / A converter in a source driver on a circuit board, for example. However, the D / A converter has a dramatically complicated circuit configuration as the number of bits of digital data increases, and the display panel is increased in size and cost due to a decrease in yield and an increase in circuit area. There's a problem. In recent years, pixel data of 8 bits or more has become mainstream in order to obtain a high-quality image with high gradation of a display image.

As a method for maintaining the gradation performance while suppressing the complexity of the D / A converter, a gradation display method combining voltage gradation and time gradation is disclosed in Patent Document 2.
In this prior art, among the m-bit digital pixel data inputted from the outside, the upper n bits are used as information for generating an analog voltage to be applied to the pixel, and the lower (mn) bits are used for time gradation. Use as information. Specifically, one frame is composed of 2 ^mn subframes for time gradation, and the voltage supplied to each pixel in each subframe is generated by converting from the upper n bits.

Japanese Patent No. 2939826 JP 2000-310980 A

The present invention provides an image display apparatus that divides an image of one frame into a plurality of subframes and sequentially time-divisionally displays each subframe, and suppresses an increase in the size of a drive circuit while maintaining high-gradation and high-quality image display. An object (problem) is to provide an image output apparatus for further cost reduction.
Another object of the present invention is to provide specific means for generating and outputting output pixel data in an image output apparatus.

  Furthermore, the present invention provides an image display device that includes the above-described image output device, divides an image of one frame into a plurality of subframes, and sequentially performs time-division display for each subframe. It is an object (problem) to provide an image display device capable of displaying an accurate image.

In addition, in the case where one frame image is displayed by synthesizing the subframe display images that are time-divisionally projected for each subframe using the optical path shift means by shifting the display positions on the projection plane, the optical path shift is performed. When the image switching speed of the image display element is not sufficient with respect to the speed of the image, the so-called image crosstalk in which the sub-frame image before the optical path shift is displayed in the sub-frame image after the optical path shift occurs, and the image quality deteriorates. May cause.
Accordingly, an object of the present invention is to provide means (problem) for preventing image quality deterioration due to image crosstalk and obtaining a higher quality image in the above image display apparatus.

In the above image display device, one frame is divided into a plurality of subframes, and further, one subframe is divided into a plurality of fields for time-division display, so that an extremely high data transfer speed and image display switching speed are achieved. Desired. For example, if the frame frequency is 60 Hz, the number of subframes is 2, and the number of fields in one subframe is 4, the image display element must be able to switch the display at a frequency of 60 Hz × 2 × 4 = 480 Hz.
Therefore, an object of the present invention is to provide an image display element having a suitable configuration in the above-described image display apparatus.

As means for achieving the above object, the present invention has the following features.
(1) In an image output apparatus having subframe generation means for dividing pixel data for one frame into a plurality of subframes and sequentially outputting each subframe, the output period of each subframe is set to a plurality of fields. And a field data generation means for generating output pixel data for each field and sequentially outputting the output pixel data.
(2): In the image output device according to (1), each of the pixel data is m-bit pixel data, and the field data generation unit determines that the upper n bits (m> n) of the m-bit pixel data For the lower (mn) bits, the output period of the subframe is time-divided into 2 ^mn fields, and the output pixel data in each field is based on the lower (mn) bit values. Is generated from the value of the upper n bits (claim 2).
(3): In the image output device according to (2), the output pixel data is either n-bit data of the upper n-bit value as it is or a value obtained by adding 1; It is generated so as to have a gradation level corresponding to the m-bit pixel data on average over all fields (claim 3).

(4): The image output apparatus according to any one of (1) to (3), an image display element that displays an image according to output pixel data from the image output apparatus, and the image display element A light source and an illuminating device for illuminating, an optical path deflecting unit for deflecting an optical path of the outgoing light from the image display element, and an optical device for enlarging and projecting the outgoing light from the optical path deflecting unit on a projection surface, The subframe display image that is time-divisionally projected for each subframe is synthesized by shifting the display position on the projection plane to display the image of the one frame, and each subframe is further divided into a plurality of fields. In addition, a desired gradation display is performed in one subframe period by performing time-division projection with predetermined gradations, respectively.
(5): In the image display device according to (4), each pixel data of the one-frame image is m-bit pixel data, and the upper n bits (m> n) and the lower bits of the m-bit pixel data Each subframe is divided into 2 ^mn fields for (mn) bits, and each field is generated from the upper n bits based on the lower (mn) bits. By performing gradation display using the output pixel data thus obtained, a desired gradation display is performed by averaging over the display period of the one subframe.
(6): In the image display device according to (5), the output pixel data is n-bit data that is either the value of the upper n bits as it is or a value obtained by adding 1; A desired gradation display is performed on average during the display period.

(7): In the image display device according to any one of (4) to (6), a display period of a predetermined gradation level is provided between the display of the subframes. (Claim 7).
(8): In the image display device according to (7), the predetermined gradation level is a minimum gradation level.
(9): In the image display device according to (7), the predetermined gradation level is a maximum gradation level.
(10) In the image display device according to any one of (4) to (9), the image display element has a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer formed on a silicon backplane. It is LCOS (Liquid Crystal On Silicon) (claim 10).

In the configuration of (1) of the present invention, in an image output device that divides pixel data for one frame into a plurality of subframes and outputs the pixel data for each subframe, the voltage gradation and the time gradation are combined. Since means for generating and outputting pixel data for gradation display is provided, it is possible to realize an image display device capable of displaying high-quality images with high gradation while maintaining high resolution at low cost. .
In the configuration of (2) or (3) of the present invention, the output pixel data is set to n bits (n <m) with respect to the m-bit pixel data in the configuration of (1), so that D / The circuit scale of the A converter is reduced, and a specific cost reduction is achieved.

In the configuration of (4) of the present invention, the image output device according to any one of (1) to (3), and an image display element that displays an image according to output pixel data from the image output device, A light source and an illuminating device that illuminate the image display element, an optical path deflecting unit that deflects an optical path of light emitted from the image display element, and an outgoing light from the optical path deflecting unit is enlarged and projected onto a projection surface. An optical device is provided, and the one-frame image is displayed by synthesizing the sub-frame display images that are time-divisionally projected for each sub-frame by shifting the display positions on the projection plane. Furthermore, the desired gradation display is performed in one sub-frame period by dividing into a plurality of fields and time-division projecting each with a predetermined gradation, so that a high-quality image display with a high gradation can be achieved while maintaining a high resolution. Picture Display device can be realized at low cost.
In the configuration of (5) or (6) of the present invention, the output pixel data is set to n bits (n <m) with respect to the m-bit pixel data in the configuration of (4), so that D / The circuit scale of the A converter is reduced, and a specific cost reduction is achieved.

In the configuration of (7) of the present invention, in the image display device according to any one of (4) to (6), the optical path is shifted to a predetermined gradation level when the display of the subframe is switched. Since it did in this way, generation | occurrence | production of the crosstalk of the image between sub-frames can be prevented and a high quality image is obtained.
In the configuration of (8) of the present invention, in the image display device described in (7), the display image is shifted to the lowest gradation level, that is, black display, particularly when the display of the subframe is switched. A high contrast and clear display image can be obtained.
In the configuration (9) of the present invention, in the image display device according to (7), the display image is shifted to the highest gradation level, that is, white display, particularly when the subframe display is switched, and the optical path is shifted. As a result, the light use efficiency is increased, and the luminance is reduced and the power consumption is reduced.

  Furthermore, in the configuration (10) of the present invention, in the image display device according to any one of (4) to (6), a liquid crystal layer is driven on a single crystal silicon backplane as an image display element. Since LCOS having a display portion including electrodes is used, a high-speed driving circuit can be configured on the silicon backplane, and the liquid crystal layer can be formed extremely thin to achieve a high optical response speed. High-speed image switching for each field is easily realized.

  Hereinafter, the configuration, operation, and operation of the image output apparatus and the image display apparatus according to the present invention will be described in detail based on the illustrated embodiments.

[Example 1]
First, an embodiment of the image output apparatus described in (1) to (3) of the above-described solving means will be described.
FIG. 1 schematically shows a configuration example of an image output apparatus according to the present invention. The image output device divides pixel data for one frame into a plurality of subframes, and outputs subframes sequentially for each subframe (decoder 5, write control circuit 6, subframe memories 1-4). Field data generation means (subframe memories 1 to 4, readout control circuit 7, +1 circuit) that time-divides the output period of each subframe into a plurality of fields, generates output pixel data for each field, and sequentially outputs the output pixel data 8, determination circuit 9 and selection circuit 10).

In FIG. 1, a signal DVI is an input image signal formatted in the DVI standard, which is one of digital image data transmission standards. The decoder 5 decodes the input image signal DVI and outputs m-bit pixel data Di (m), its synchronization clock WCK, and horizontal / vertical synchronization signal HD / VD.
The input image is, for example, an image having the number of pixels N in the horizontal direction M and the vertical direction as shown in FIG. 2, and (x, y) represents the xth pixel in the yth line in the vertical direction. Pixel data is sequentially input from one line to N lines in order, and in each line from the top (1, y) to (M, y) in order.

  The write control circuit 6 generates and outputs the write address WA and the selection signals CS1 to CS4 of the subframe memories 1 to 4 from the synchronization clock WCK and the horizontal / vertical synchronization signal HD / VD output from the decoder 5, respectively. FIG. 3 is a timing chart of input / output signals for explaining the operation of the write control circuit 6. The write address WA includes a horizontal address part WA (x) and a vertical address part WA (y).

  FIG. 3A shows the relationship between the horizontal / vertical synchronization signal HD / VD and the vertical address portion WA (y). The vertical synchronization signal VD is a signal that becomes “H” level for a predetermined time at the start timing of pixel data input for one frame, and the horizontal synchronization signal HD is “H” for a predetermined time at the start timing of pixel data input for one line. It is a signal that goes to “level”. The value of the vertical address portion WA (y) of the write address WA increases by 1 every two cycles of the horizontal synchronization signal.

  FIG. 3B shows the relationship among the horizontal synchronization signal HD, the horizontal address portion WA (x) of the write address WA, the synchronization clock WCK, and the selection signals CS1 to CS4. The synchronization signal WCK transitions to the “H” level in synchronization with each input pixel data Di (m). The value of the horizontal address part WA (x) of the write address WA increases by 1 every two cycles of the synchronization signal WCK. The selection signal CS1 of the sub-frame memory 1 becomes “H” level with respect to the odd-numbered pixel data from the beginning of the odd-numbered line of the input image. The selection signal CS2 of the sub-frame memory 2 becomes “H” level with respect to even-numbered pixel data from the beginning of the odd-numbered line of the input image. The selection signal CS3 of the sub-frame memory 3 becomes “H” level for the odd-numbered pixel data from the top of the even-numbered line of the input image. Then, the selection signal CS4 of the subframe memory 4 becomes “H” level with respect to the even-numbered pixel data from the top of the even-numbered line of the input image.

  The sub-frame memories 1 to 4 are memories for storing four sub-frames 1 to 4 for dividing and displaying one frame of the input image, and each of the sub-frame memories 1 to 4 is “H”. The input pixel data Di (m) is stored based on the write address WA. The subframe 1 belongs to an odd-numbered line of the input image and includes odd-numbered pixels from the top of each line. The subframe 2 belongs to an odd-numbered line of the input image and includes even-numbered pixels from the top of each line. The subframe 3 belongs to the even-numbered lines of the input image and is composed of odd-numbered pixels from the top of each line. The subframe 4 belongs to even-numbered lines of the input image and is composed of even-numbered pixels from the top of each line. FIG. 4 shows a pixel array of each subframe image. In the present embodiment, the number of subframes is four, but this is not a limitation. The same applies to the pixel arrangement of each subframe.

The read control circuit 7 receives a read address RA, OE1 to OE4, which are output enable signals of the subframe memories 1 to 4, respectively, from the synchronization clock WCK and the horizontal / vertical synchronization signal HD / VD output from the decoder 5, and An FC that is the count value of the field constituting the subframe is generated and output. OE1 to OE4 sequentially become “H” level one by one at a predetermined timing.
In the subframe memories 1 to 4, when the output enable signals OE1 to OE4 are at "L" level, the outputs Di1 (m) to Di4 (m) are in a high impedance state, and OE1 to OE4 are at "H" level. The pixel data written at this time is read out sequentially based on the read address RA. Here, the subframe memories 1 to 4 are memories having a dual port function capable of reading data asynchronously with writing. The corresponding sub-frame pixel data is repeatedly read four times during the period when one output enable signal is “H”, and the count value FC of the field is updated each time.

  The upper n bits Di (n) of the pixel data read from any of the subframe memories 1 to 4 are input to the selection circuit 10 as they are, and 1 is added by the +1 circuit 8 (Di (n) +1). ) And input to the selection circuit 10. On the other hand, the lower (mn) bits of the pixel data read from any of the subframe memories 1 to 4 are input to the determination circuit 9. The determination circuit 9 controls the state of the output signal S based on the lower (mn) bits of the pixel data and the value of the field count value FC. The selection circuit 10 selects either input data Di (n) or Di (n) +1 based on the value of the signal S and outputs it as output pixel data Do (n). FIG. 5 shows an example of pixel data output for each field when the lower order (mn) is 2 bits.

In the configuration of this embodiment, in an image output apparatus that divides pixel data for one frame into a plurality of subframes and outputs the pixel data for each subframe, a grayscale that combines voltage grayscale and time grayscale Since means for generating and outputting pixel data for display is provided, it is possible to realize an image display device capable of displaying high-quality images with high gradation while maintaining high resolution at low cost.
Further, since the output pixel data is set to n bits (n <m) with respect to the m-bit pixel data, the circuit scale of the D / A converter is reduced, and the specific cost can be reduced.

[Example 2]
Next, an embodiment of the image display device described in the above solution means (4) to (6) will be described.
FIG. 6 schematically shows a configuration example of a projection type image display apparatus according to the present invention. In FIG. 6, the integrator optical system 22 is configured by a fly-eye lens array, for example, and uniformizes the light from the light source 21. The condenser lens 23 is for condensing and illuminating illumination light on the spatial light modulation element 25 which is an image display element. Here, the spatial light modulator 25 is a reflective liquid crystal panel. The drive device 27 includes the image output device having the configuration shown in FIG. 1, divides the display image data into subframes, and further outputs each subframe sequentially for each of a plurality of fields. The spatial light modulator 25 modulates illumination light incident on each pixel based on pixel data from the driving device 27. The illumination light that has been spatially modulated by the spatial light modulator 25 enters the optical path deflecting element 26 as image light, and is deflected so that the image light is shifted by an amount set in the pixel arrangement direction. The optical path deflection operation is controlled by the driving device 28. The polarization beam splitter 24 is for separating illumination light and image light. Further, light emitted from the optical path deflecting element 26 is magnified by the projection lens 29 and projected onto the screen 30.

  The amount of optical path deflection by the optical path deflecting element 26 is preferably 1 / integer of the pixel pitch. It is preferable to set the pixel pitch to ½ when performing image multiplication twice as much as the pixel arrangement direction, and to ¼ the pixel pitch when performing pixel multiplication four times. In any case, the image frame is composed of a plurality of subframes divided in time according to the number of deflection directions to be switched, and the optical path deflecting element 26 is operated for each subframe, and the operating state of the optical path deflecting element 26 is By displaying the image information corresponding to the display position corresponding to the image on the spatial light modulation element 25 that is an image display element, an apparently high-definition image can be displayed. FIG. 7 shows a state in which a display image by an arbitrary pixel of the spatial light modulation element is multiplied by four times by the optical path deflecting element and projected onto the screen, and FIG. 8 shows the result on the screen. A one-frame image projected and displayed as an example is shown. In the present embodiment, the configuration using the reflective spatial light modulator 25 as an image display element has been described as an example, but a configuration example using a transmissive image display element is also possible.

[Example 3]
Next, an embodiment of the image display device described in (7) to (10) of the above-described solving means will be described.
FIG. 9 schematically shows a configuration example of an LCOS in which a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer is formed on a silicon backplane as an example of an image display element in the image display device according to the present invention. It is. That is, the LCOS uses a silicon substrate (Si substrate) 41 as one of upper and lower substrates enclosing liquid crystal.
More specifically, on the Si substrate 41, a circuit composed of pixel transistors 42 and the like, a light shielding layer 43, and a mirror electrode 44 are formed. A glass substrate 48 on which an ITO counter electrode 47 is formed is disposed opposite to the Si substrate 41, and a predetermined gap (gap) is provided between both substrates by a columnar spacer 45. A liquid crystal layer is formed in the gap. 46 is enclosed.

  FIG. 10 shows a circuit configuration example of a backplane suitable for an image display device based on the present invention. Each pixel driving circuit has a holding capacitor C as a memory for holding analog pixel data, a transistor Q1 as a first switch for controlling the storage of image data in the memory, and the image data stored in the memory. It comprises a transistor Q2 as a second switch for controlling the output to the corresponding pixel P, and a transistor Q3 as means for setting the voltage applied to the liquid crystal pixel to a voltage value of a predetermined gradation. The source driver performs D / A conversion on the pixel data Do (n) output from the image output device, converts the pixel data Do (n) into analog pixel data, and outputs the analog data from corresponding outputs Video_1, Video_2,. The gate driver sequentially drives the line drive signals PV1, PV2,..., PVN, turns on the gate of the transistor Q1 of the corresponding line, and stores the analog pixel data output from the source driver in the storage capacitor C. When data is written in all the pixels, the signal TD is set to the “H” level to drive the transistors Q2 all at once, and the analog pixel data stored in the storage capacitor C is applied to the liquid crystal pixel P. When the subframe is switched, the signal REST is set to the “H” level to drive the transistors Q3 all at once, and the voltage applied to the liquid crystal pixel P is rewritten to a voltage value of a predetermined gradation level. In this embodiment, the ground level, that is, zero volts (0 [V]) is used, but other voltage values may be used.

  In this embodiment, since the silicon substrate 41 is used, the same microfabrication process as that of a normal semiconductor device can be used, and the above driving circuit can be formed on the same substrate. A circuit can be realized.

  FIG. 11 and FIG. 12 show examples of display operation of each pixel of the spatial light modulator. 11 and 12, Tf is a display period of one frame, Tsf1 to Tsf4 are display periods of subframes 1 to 4, Tfd1 to Tfd4 are display periods of each field, and Trst is a predetermined gradation level at the time of subframe switching. Indicates the period to be. FIG. 11 shows a case where the minimum gradation level, ie, black display is set as the predetermined gradation level, and FIG. 12 shows a state where the maximum gradation level, ie, white display, is set as the predetermined gradation level.

In the configuration of the present embodiment described above, in the image display device described in the second embodiment, the display image is shifted to the predetermined gradation level when the display of the subframe is switched. It is possible to prevent image crosstalk from occurring between frames, and a high-quality image can be obtained.
Further, in the image display device of this embodiment, the display image is shifted to the lowest gradation level, that is, black display, especially when the display of the sub-frame is switched, and the optical path is shifted, so that a clear display image with high contrast can be obtained. It is done.
Further, in the image display device of this embodiment, the display image is shifted to the highest gradation level, that is, white display, especially when the display of the sub-frame is switched, so that the light use efficiency is increased and the luminance is increased. And low power consumption.

  Further, in the image display device of this embodiment, since the LCOS in which the display portion including the liquid crystal layer and the electrode for driving the liquid crystal layer is formed on the single crystal silicon backplane is used as the image display element, high speed operation is performed on the silicon backplane. The liquid crystal layer can be formed extremely thin to realize a high optical response speed, and high-speed image switching for each field can be easily realized.

  As described above, according to the present invention, it is possible to realize an image display device capable of displaying a high-quality image with high gradation while maintaining a high resolution at a low cost. It can be used for an image display device.

It is a block diagram which shows roughly the example of a structure of the image output device based on this invention. It is a figure which shows an example of an input image. 4 is a timing chart of input / output signals for explaining the operation of the write control circuit. It is a figure which shows the pixel arrangement | sequence of each sub-frame image. It is a figure which shows the pixel data output example for every field in case low-order (mn) is 2 bits. It is a schematic block diagram which shows the structural example of the projection type image display apparatus based on this invention. It is a figure which shows a mode that the display image by arbitrary 1 pixels of a spatial light modulation element is multiplied by a 4 times pixel with an optical path deflection element, and is projected on a screen. It is a figure which shows an example of the 1 frame image projected and displayed on a screen. It is a schematic sectional drawing which shows an example of the image display element in the image display apparatus based on this invention. It is a figure which shows the circuit structural example of the backplane suitable for the image display apparatus based on this invention. It is a figure which shows an example of the display operation | movement of each pixel of a spatial light modulation element. It is a figure which shows another example of the display operation of each pixel of a spatial light modulation element. It is a figure which shows the structural example of the conventional liquid crystal display panel.

Explanation of symbols

1-4: Subframe memory 5: Decoder 6: Write control circuit 7: Read control circuit 8: +1 circuit 9: Determination circuit 10: Selection circuit 21: Light source 22: Integrator optical system 23: Condenser lens 24: Polarization beam splitter 25 : Spatial light modulation element (image display element)
26: Optical path deflecting element 27: Driving device 28: Driving device 29: Projection lens 30 Screen 41: Si substrate 42: Pixel transistor 43: Light shielding layer 44: Mirror electrode 45: Columnar spacer 46: Liquid crystal layer 47: ITO counter electrode 48 : Glass substrate

Claims (10)

In an image output device including subframe generation means for dividing pixel data for one frame into a plurality of subframes and sequentially outputting each subframe,
An image output apparatus comprising field data generation means for time-dividing an output period of each subframe into a plurality of fields, generating output pixel data for each field, and sequentially outputting the output pixel data. The image output apparatus according to claim 1,
Each of the pixel data is m-bit pixel data, and the field data generation unit is configured to generate the sub-frame for the upper n bits (m> n) and the lower (mn) bits of the m-bit pixel data. The output period is time-divided into 2 ^mn fields, and output pixel data in each field is generated from the upper n-bit values based on the lower (mn) bit values. Image output device. The image output apparatus according to claim 2, wherein
The output pixel data is n-bit data that is either the upper n-bit value as it is or a value obtained by adding 1, and corresponds to the m-bit pixel data on average in all fields of the one subframe. An image output device that is generated so as to have a gradation level.   The image output device according to claim 1, an image display element that displays an image according to output pixel data from the image output device, a light source that illuminates the image display device, and an illumination device And an optical path deflecting means for deflecting the optical path of the emitted light from the image display element, and an optical device for enlarging and projecting the emitted light from the optical path deflecting means on the projection surface. The one-frame image is displayed by combining the divided and projected sub-frame display images on the projection plane while shifting the display positions, and each of the sub-frames is further divided into a plurality of fields. An image display device characterized in that a desired gradation display is performed in one subframe period by time-division projection in a key. The image display device according to claim 4.
Each pixel data of the one-frame image is m-bit pixel data, and the sub-frames are assigned to upper n bits (m> n) and lower (mn) bits of the m-bit pixel data. 2 fields are divided into ^mn fields, and each field is displayed in grayscale with output pixel data generated from the upper n bits based on the lower (mn) bits. An image display device that performs a desired gradation display on average during a frame display period. The image display device according to claim 5,
The output pixel data is n-bit data which is either the value of the upper n bits as it is or a value obtained by adding 1, and performing desired gradation display on average during the display period of the one subframe. A characteristic image display device. In the image display device according to any one of claims 4 to 6,
An image display device, wherein a display period of a predetermined gradation level is provided between display of the subframes. The image display device according to claim 7,
The image display apparatus according to claim 1, wherein the predetermined gradation level is a minimum gradation level. The image display device according to claim 7,
The image display apparatus according to claim 1, wherein the predetermined gradation level is a maximum gradation level. In the image display device according to any one of claims 4 to 9,
The image display device is an LCOS (Liquid Crystal On Silicon) in which a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer is formed on a silicon backplane.

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