CN117409708B - Method for effectively improving refresh rate of LED display driving chip - Google Patents
Method for effectively improving refresh rate of LED display driving chip Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention relates to the technical field of LED display driving chips, and provides a method for effectively improving the refresh rate of an LED display driving chip, which comprises the following steps: setting the register value of the break-up group number as S; setting the clock frequency division coefficient register value as Div; acquiring an input display Gray level register value as Gray, and calculating an actual display Gray level register value as NGray according to the input display Gray level Gray and the clock frequency division coefficient Div; calculating a register value of a high significant bit as MSB and a register value of a low significant bit as LSB according to the actual display gray NGray and the scattering group number S; setting a counter register as a counter and a register value Ncounter; and calculating the display gray scale register value of each group as SGray according to the MSB, LSB and Ncounter. Under different application conditions, the display refresh rate of the driving chip is improved by utilizing the integer frequency division relation of the actual application clock and the chip highest frequency clock and the PMW scattering technology.
Description
Technical Field
The invention relates to the technical field of LED display driving chips, in particular to a method for effectively improving the refresh rate of an LED display driving chip.
Background
In the technical development of LED display driving chips, PWM (pulse width modulation) technology is widely used to increase the display refresh rate of the LED driving chips. In order to improve the display refresh rate, the break-up PWM technique increases the overall refresh rate of the LED display screen by decomposing the on-time of a set of data into a plurality of time periods. Refresh rate refers to the number of refreshes per second of a display screen, typically expressed in hertz (Hz). The lower refresh rate may cause blurring, flickering, or tearing of the image during movement, affecting the viewing experience. Such unstable images may put a large burden on the eyes, resulting in viewing fatigue and discomfort. Higher refresh rates can provide smoother image display, reduce flicker and blurring phenomena, thereby reducing the burden on the eyes and reducing the risk of viewing fatigue. The break-up PWM technique has limited effect on improving refresh rate when corresponding to low frequency low gray display.
For multi-frequency, multi-clock display processing applications with integer divide relationships (each clock frequency is equal to the division of the highest clock by a particular integer), it is common in conventional practice to generate different frequency clocks using the OSC (oscillator) of the chip itself. As shown in fig. 2, when the frequency-divided-by-1 clock is required, the frequency-divided-by-1 clock is generated by OSC. When a divided-by-2 clock is required, then the OSC is used to generate the divided-by-2 clock, and so on. In addition, in the field of LED display driving chips, PWM scattering technology is often used to break down the on-time of a group of data into multiple time segments, thereby increasing the overall refresh rate (refresh rate, in hertz (Hz), defined as the number of screen brightness changes per second, refresh rate = frame rate (Hz)) of the LED display screen. For example, as shown in fig. 3, the gray value data 4096 is broken into 8 groups, 4096/8=512, the gray value displayed by each group is 512, the display is broken into eight groups from one group of 4096, the number of times of lighting and darkness is increased by 8 times, the high level represents that the LED is on, and the low level represents that the LED is off, so that the display refresh rate is increased by 8 times. A high display refresh rate is advantageous for reducing display flicker and glare, providing a more comfortable viewing experience.
However, in the low gray condition, as shown in fig. 4, in the condition that the display gray value is only 1 gray value, although the display gray value is broken up into 8 groups, since only 1 gray value is used, only one group has a high level (lit up), and the other 7 groups have no, and if the frame rate is 60, the refresh rate is 60×1=60 Hz. The frequency is equal to the refresh rate without using the scattering technology, which means that the scattering technology does not well improve the refresh rate at the time of low ash, and sometimes the problem caused by low refresh rate is not obvious at the time of high frequency and low ash, but the problem of low refresh rate caused by low frequency and low ash is often needed to be solved, and the phenomenon caused by low refresh rate is obvious as the frequency is lower.
Disclosure of Invention
The invention aims to provide a method for effectively improving the refresh rate of an LED display driving chip.
The invention aims to solve the problem that the scattering PWM technology in the existing LED display driving chip technology has limited effect on improving the refresh rate when the LED display driving chip technology corresponds to low-frequency low-gray driving display.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
a method for effectively improving the refresh rate of an LED display driving chip comprises the following steps: setting a break-up group number register value S; setting a clock frequency division coefficient register value Div; acquiring an input display Gray register value Gray, and calculating an actual display Gray register value NGray according to the input display Gray register value Gray and the clock frequency division coefficient register value Div; calculating an MSB (high significant bit) register value and an LSB (low significant bit) register value according to the actual display gray level register value NGray and the break-up group number register value S; setting a counter register and a counter register Ncounter; calculating a display gray scale register value SGray of each group according to the MSB, the LSB and the Ncounter;
the actual display gray scale register value NGray is:
NGray＝Gray*Div
wherein NGray is the actual display Gray scale register value, gray is the input display Gray scale register value, div is the clock frequency division coefficient register value;
the setting counter register and counter register Ncounter includes: setting the counter register for recording the serial numbers of each group, and calculating the value of the counter register Ncounter; the counter register Ncounter is equal to a value symmetrically exchanged between high and low bits of the counter register data; the counter register counter= { counter [2], counter [1], counter [0] }, { counter [2], counter [1], counter [0] } is transformed into { counter [0], counter [1], counter [2] }, then the counter register Ncounter= { counter [0], counter [1], counter [2] };
the maximum values of the counter register and the counter register Ncounter are S-1;
the display gray register value SGray of each group is:
SGray=MSB+b
wherein SGray is the display gray scale register value of each group, MSB is the high-efficient bit register value;
when Ncounter < LSB, b is equal to 1;
when Ncounter is greater than or equal to LSB, then b is equal to 0.
As a further improvement, the break-up group number register value S is:
S=2 n
wherein S is a break-up group number register value, and n is an integer.
As a further refinement, the high-significant bit register value MSB is:
MSB＝NGray/S
wherein MSB is the register value of the high-efficient bit, NGray is the register value of the actual display gray scale, S is the register value of the broken group number.
As a further improvement, the low significant bit register value LSB is:
LSB＝NGray％S
wherein LSB is the register value of low significant bit, NGray is the register value of actual display gray scale, S is the register value of broken group number.
The beneficial effects of the invention are as follows:
the invention relates to a method for effectively improving the refresh rate of an LED, which utilizes the integer frequency division relation of an actual application clock and a highest frequency clock under different application conditions, forms a display pulse width with low frequency in the actual application by using the display pulse width of the highest frequency clock, and disperses a plurality of display pulse widths formed by the highest frequency into other groups so that other individual groups can obtain effective display data, thereby improving the refresh rate.
Drawings
Fig. 1 is a schematic diagram of a method for effectively improving a refresh rate of an LED display driving chip according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of generating different frequency clocks using OSC in the prior art.
Fig. 3 is a schematic diagram of prior art gray scale values 4096 broken up into 8 groups.
Fig. 4 is a schematic diagram of the prior art, in which gray values 4096 are broken up into 8 groups in the case of low gray.
Fig. 5 is a schematic diagram of different divided clocks of an OSC design according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1 and 5, a method for effectively improving a refresh rate of an LED display driving chip includes: setting a break-up group number register value S; setting a clock frequency division coefficient register value Div; acquiring an input display Gray register value Gray, and calculating an actual display Gray register value NGray according to the input display Gray register value Gray and the clock frequency division coefficient register value Div; calculating an MSB (high significant bit) register value and an LSB (low significant bit) register value according to the actual display gray level register value NGray and the break-up group number register value S; setting a counter register and a counter register Ncounter; calculating a display gray scale register value SGray of each group according to the MSB, the LSB and the Ncounter;
the actual display gray scale register value NGray is:
NGray＝Gray*Div
wherein NGray is the actual display Gray scale register value, gray is the input display Gray scale register value, div is the clock frequency division coefficient register value;
the setting counter register and counter register Ncounter includes: setting the counter register for recording the serial numbers of each group, and calculating the value of the counter register Ncounter; the counter register Ncounter is equal to a value symmetrically exchanged between high and low bits of the counter register data; the counter register counter= { counter [2], counter [1], counter [0] }, { counter [2], counter [1], counter [0] } is transformed into { counter [0], counter [1], counter [2] }, then the counter register Ncounter= { counter [0], counter [1], counter [2] }; for example, when the value of the 3bit counter is 3' b001, the Ncounter obtained by the middle symmetrical exchange is 3' b100, and when the counter is 110, the Ncounter obtained by the middle symmetrical exchange is 3' b011.
The maximum values of the counter register and the counter register Ncounter are S-1;
the display gray register value SGray of each group is:
SGray=MSB+b
wherein SGray is the display gray scale register value of each group, MSB is the high-efficient bit register value;
when Ncounter < LSB, b is equal to 1;
when Ncounter is greater than or equal to LSB, then b is equal to 0.
The break-up group number register value S is:
S=2 n
wherein S is a break-up group number register value, and n is an integer. Since the chip digital signal consists of 0 or 1 binary, S is set to 2 here n Since S is an integer power of 2, the chip is advantageously simple in the following division and remainder processing.
The high-significant bit register value MSB is:
MSB＝NGray/S
wherein MSB is the register value of the high-efficient bit, NGray is the register value of the actual display gray scale, S is the register value of the broken group number.
The low significant bit register value LSB is:
LSB＝NGray％S
wherein LSB is the register value of low significant bit, NGray is the register value of actual display gray scale, S is the register value of broken group number.
The counter registers counter and Ncounter are both 3bit binary counters.
Assume that the set chip applies clock divide by 3; the number of the scattering groups is 8, the displayed gray level is 2, 0 such as MSB is calculated according to the formula, and LSB is equal to 6; the 8 sets of display data are (1, 0, 1, 0) at the highest frequency, respectively, 1+1+1+1+1+1=6. Whereas the 8 groups of display grayscales in the conventional manner are 3×1, 0, 1, 0, 3×1+1) =6, it can be seen that the theoretical values displayed by the two are identical, but the refresh rate of the method is 3 times [ (1+1+1+1+1)/(1+1) =3 (1 represents 1 change here) ] as compared with the conventional method; therefore, the method improves the refresh rate on the premise of keeping consistent brightness.
The invention relates to a method for effectively improving the refresh rate of an LED display driving chip. Under different application conditions, the integer frequency division relation of the actual application clock and the highest frequency clock is utilized, the display pulse width of the highest frequency clock is used for forming the display pulse width with low frequency in the actual application, and a plurality of display pulse widths formed by the highest frequency are scattered and dispersed into other groups, so that other individual groups can obtain effective display data, and the refresh rate is further improved. The display pulse width of the low-frequency clocks of frequency division 2, frequency division 3 and the like can be composed of the frequency division 1 clock of the highest frequency clock, the display pulse width of the frequency division 2 and the frequency division 1 gray scale can be composed of the frequency division 2 and the frequency division 1 gray scale display pulse width can be composed of the frequency division 3 and the frequency division 1 gray scale display pulse width can be composed of the frequency division 1 gray scale display pulse width. As shown in fig. 5, 1 display gray scale of the divided-by-2 clock may be composed of 2 divided-by-1 gray scales. It can be seen that, as long as the maximum 1 frequency division clock exists, other relatively low frequency clocks can be formed by utilizing the integral multiple frequency division relation with the maximum clock, so that when the OSC is designed, as long as the OSC clock is designed by 1 frequency division of the maximum frequency clock, other clocks are not required to be generated, and when other low frequency clocks are applied, the display pulse width can be formed by the pulse width generated by the maximum frequency clock, thereby being beneficial to simpler OSC structure and reducing the area of a chip. Meanwhile, when the low-frequency low-ash display device is applied, a PWM scattering technology is utilized to firstly convert the low-frequency display pulse width into a plurality of display pulse widths composed of the highest frequencies, and the plurality of display pulse widths composed of the highest frequencies are scattered and scattered into other groups, so that the refresh rate of the low-frequency low-ash display device is improved. If the method is applied to the frequency-divided-by-2 clock and 1 gray scale at the frame frequency of 60Hz, the traditional refresh rate is 60×1=60 Hz, and the frequency-divided-by-2 1 gray scale is composed of 2 frequency-divided-by-1 gray scales, and the 2 frequency-divided-by-1 gray scales are scattered into different groups, the refresh rate is equal to 60×2=120 Hz, and the refresh rate is doubled. Similarly, when the frequency is divided by 3, the refreshing is improved by 3 times under the condition of 1 gray scale and low gray scale.
The above examples are only for illustrating the technical scheme of the present invention and are not limiting. It will be understood by those skilled in the art that any modifications and equivalents that do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (4)
1. The method for effectively improving the refresh rate of the LED display driving chip is characterized by comprising the following steps of: setting a break-up group number register value S; setting a clock frequency division coefficient register value Div; acquiring an input display Gray register value Gray, and calculating an actual display Gray register value NGray according to the input display Gray register value Gray and the clock frequency division coefficient register value Div; calculating an MSB (high significant bit) register value and an LSB (low significant bit) register value according to the actual display gray level register value NGray and the break-up group number register value S; setting a counter register and a counter register Ncounter; calculating a display gray scale register value SGray of each group according to the MSB, the LSB and the Ncounter;
the actual display gray scale register value NGray is:
NGray＝Gray*Div
wherein NGray is the actual display Gray scale register value, gray is the input display Gray scale register value, div is the clock frequency division coefficient register value;
the setting counter register and counter register Ncounter includes: setting the counter register for recording the serial numbers of each group, and calculating the value of the counter register Ncounter; the counter register Ncounter is equal to a value symmetrically exchanged between high and low bits of the counter register data; the counter register counter= { counter [2], counter [1], counter [0] }, { counter [2], counter [1], counter [0] } is transformed into { counter [0], counter [1], counter [2] }, then the counter register Ncounter= { counter [0], counter [1], counter [2] };
the maximum values of the counter register and the counter register Ncounter are S-1;
the display gray register value SGray of each group is:
SGray=MSB+b
wherein SGray is the display gray scale register value of each group, MSB is the high-efficient bit register value;
when Ncounter < LSB, b is equal to 1;
when Ncounter is greater than or equal to LSB, then b is equal to 0.
2. The method for effectively increasing the refresh rate of an LED display driver chip according to claim 1, wherein the break-up group number register value S is:
S=2 n
wherein S is a break-up group number register value, and n is an integer.
3. The method for effectively increasing the refresh rate of an LED display driver chip according to claim 1, wherein said high-activity bit register value MSB is:
MSB＝NGray/S
wherein MSB is the register value of the high-efficient bit, NGray is the register value of the actual display gray scale, S is the register value of the broken group number.
4. The method for effectively increasing the refresh rate of an LED display driver chip according to claim 1, wherein said low significant bit register value LSB is:
LSB＝NGray％S
wherein LSB is the register value of low significant bit, NGray is the register value of actual display gray scale, S is the register value of broken group number.
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