CN100578935C - Pulse production circuit and circuit for realizing liquid crystal gray scale using the same - Google Patents
Pulse production circuit and circuit for realizing liquid crystal gray scale using the same Download PDFInfo
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- CN100578935C CN100578935C CN200580049251A CN200580049251A CN100578935C CN 100578935 C CN100578935 C CN 100578935C CN 200580049251 A CN200580049251 A CN 200580049251A CN 200580049251 A CN200580049251 A CN 200580049251A CN 100578935 C CN100578935 C CN 100578935C
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Abstract
The prevent invention provides a pulse generating circuit and a circuit which utilizes the pulse generating circuit to implement LCD gray scale. Said LCD gray scale implementing circuit possesses pulse generating unit, gray data reading control unit, gray data memory, frame synchronization generating unit and gray modulating unit. The pulse generating unit includes a first level pulse generating unit, a second level pulse generating unit and at least one end level pulse generating unit. Said first level pulse generating unit includes subframe counter and subframe determine unit. The second level pulse generating unit has a second level counter and second level pulse width generator, a second level comparator, a second level first selector and second level second selector. The end level pulse generating unit includes corresponding level counter, corresponding level pulse width generator, corresponding level comparator and corresponding level first selector. The invention reduces pulse reversal and saves power consumption, thus may improves display effect.
Description
Technical field
The present invention relates to a kind of Display Realization circuit of gradation data, relate in particular to a kind of at the liquid crystal greyscale Display Realization circuit of power consumption requirement than higher electronic product field.
Background technology
The luminous mechanism of LCDs is to realize different brightness by the electric field difference that is added on its certain picture element.Present chip for driving generally is to adopt the dynamic driving method, is divided into column electrode and row electrode.Generally column electrode is lined by line scan, the row electrode is applied signal bright or that do not work synchronously with the frame frequency more than the 30Hz.
Voltage gating on the row electrode or gating not are to give analog drive circuit because Digital Logic produces the pulse signal of different in width.When the pulse duration of sending is 0, gating not just, when the pulse duration of sending is not 0, with regard to the corresponding time span of gating, also just corresponding different light and shade grade, we are called gray scale.Therefore from the Design of Digital Circuit angle, how long the pulse duration of just giving analog drive circuit of care continues.The longest lasting level of pulse duration, the highest gray scale that can realize exactly.
All mixing obtains any color according to different proportion by RGB (RGB) three primary colors.If R, G, B have X, Y, Z kind probable value respectively, then can reach X * Y * Z kind color altogether, for example R, G, B respectively have 64 kinds of gray scales to select, and then having 64 * 64 * 64=262144 kind may make up.Because the realization circuit of R, G, B is the same, so need design a kind of circuit, can export to analog drive circuit to 64 gray values with certain waveform.
At present, PWM (Pulse Width Modulation, pulse-width modulation) pattern, and FRC (Frame Rate Control, frame frequency control) is a gray modulation method commonly used.
Pulse-width modulation, be to be divided into several timeslices in the time at single pass, as for 64 grades of gray scales, just be divided into 64 timeslices, if show 5/64 gray scale, having only in time of 5/64 so is (for the same point) that driving voltage is arranged, and last equivalent voltage just has only complete black 5/64, sees Fig. 1.
Frame frequency control is that each timeslice has become a subframe, shows 64 grades of gray scales, will use 64 subframes so.We at first will distinguish the notion of subframe (subframe).Frame frequency is meant the number of times of the full frame data of kind interscan in a second, and in order to realize FRC, a frame is divided into some subframes.Because the visual effect of human eye feels that the brightness that is adding up of all subframes, sees Fig. 2.
Than higher gray scale, generally adopt the mode of PWM+FRC combination for exponent number.Because gray scale is high more, the frequency that adopts PWM to need is just high more, and power consumption is also just big more.5PWM+1FRC is meant and is divided into two subframes that 32 timeslices are arranged in each subframe, therefore can realize 64 grades of gray scales, sees Fig. 3.4PWM+2FRC is meant and is divided into four subframes that 16 timeslices are arranged in each subframe, therefore also can realize 64 grades of gray scales, sees Fig. 4.The bit wide of gradation data has determined grey level, in general, jPWM+kFRC (j, k=0,1,2...) gray scale that can realize is 2 (j+K), j+k is exactly the bit wide of gradation data.
Gradation data changes into waveform different in size, can be by the circuit of Fig. 5, and P is a reference pulse, Q is the input data.Gradation data Q can think that is selected a signal, selects to export behind the reference pulse P as shown in Figure 6.The Q0 correspondence P0, and the Q1 correspondence P1, and the Qn correspondence Pn.
For example, as shown in Figure 6, data 42=6 ' b101010, corresponding Q5, Q4, Q3, Q2, Q1, Q0 respectively.Can see that from the realization of circuit the output pulse is sectional, a value needs several sections pulses to realize.With the 5PWM+1FRC pattern is example, is 42 value for gray scale, each sub-frame allocation 21, and then each subframe is that three sections pulses of 1,4 and 16 are formed by width.
Because the upset that pulse does not stop can cause power consumption to increase, and short pulse occurs frequent, because rising and falling edges needs the time, may cause the short pulse wave distortion, in addition,, thereby also influenced display effect because gray value is not all assigned to each subframe.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of pulse-generating circuit and utilizes this circuit to realize the circuit that liquid crystal greyscale shows, reduces the number of times of pulse upset and the appearance of short pulse, and gray value is divided equally in each subframe.
The invention provides a kind of pulse-generating circuit, comprise first order pulse generation unit, be used to produce pulse signal corresponding to liquid crystal greyscale data lowest order digit certificate, pulse generation unit in the second level is used to produce the pulse signal corresponding to liquid crystal greyscale data time low data, and at least one back level pulse generation unit, be used to produce pulse signal corresponding to liquid crystal greyscale data high position data, wherein, described first order pulse generation unit comprises:
The sub-frame count device is used for sub-frame sync signal and gray modulation mode signal according to input, carries out sub-frame count; And
The subframe judging unit, be used for output valve and described gray modulation mode signal according to described sub-frame count device, output first order subframe is judged signal and second level subframe judgement signal, wherein judges the output level of signal as described first order pulse with described first order subframe
Described second level pulse generation unit comprises:
Second level counter is used for counting according to clock signal;
Second level pulse duration generator is used to produce this grade pulse duration;
Second level comparator is used for the output of described second level pulse duration generator and the output of described second level counter are compared, if conform to then export one efficiency confirmed signal, with described second level counter reset, makes it to count again simultaneously;
Second level first selector, be used under the control of selecting signal, the gating input signal, it selects signal is described gray modulation mode signal, its input signal comprises the output signal of described second level comparator, and the second level subframe of described subframe judging unit output is judged signal; And
Second level second selector is used for the output signal of described second level first selector as selecting signal, its different input signal counter-rotating output of control gating,
Described back level pulse generation unit comprises:
This grade counter is used for counting according to input clock;
This grade pulse duration generator is used to produce this grade pulse duration;
This grade comparator is used for the output of more described this grade counter and this grade pulse duration generator, when both are equal, produces an output signal, and utilizes described this grade counter reset of this output signal control; And
This grade first selector is used for the output signal of described this grade comparator controlling its different input signal counter-rotating output as selecting signal.
The present invention and then a kind of circuit of realizing liquid crystal greyscale is provided comprises: the pulse generation unit is used to produce reference pulse signals at different levels, and generates line synchronizing signal; Gradation data reads control unit, is used for carrying out address choice according to described line synchronizing signal; The gradation data memory is used to store gradation datas at different levels, reads the address of control unit output and reads to apply for signal, output gray level data according to described gradation data; Frame synchronization generating unit is used to receive described line synchronizing signal, according to the size generation frame synchronizing signal of liquid crystal panel; And the gray modulation unit, be used for reference pulse signals described at different levels and gradation data according to input, export modulated pulse signal.
Wherein, described pulse generation unit, comprise first order pulse generation unit, be used to produce reference pulse signal corresponding to liquid crystal greyscale data lowest order digit certificate, second level pulse generation unit, be used to produce reference pulse signal corresponding to liquid crystal greyscale data time low data, and at least one back level pulse generation unit, be used to produce reference pulse signal corresponding to liquid crystal greyscale data high position data.Wherein, described first order pulse generation unit comprises:
The sub-frame count device is used for sub-frame sync signal and gray modulation mode signal according to input, carries out sub-frame count; And
The subframe judging unit, be used for output valve and described gray modulation mode signal according to described sub-frame count device, output first order subframe is judged signal and second level subframe judgement signal, wherein judges the output level of signal as described first order pulse with described first order subframe
Described second level pulse generation unit comprises:
Second level counter is used for counting according to clock signal;
Second level pulse duration generator is used to produce this grade pulse duration;
Second level comparator is used for the output of described second level pulse duration generator and the output of described second level counter are compared, if conform to then export one efficiency confirmed signal, with described second level counter reset, makes it to count again simultaneously;
Second level first selector, be used under the control of selecting signal, the gating input signal, it selects signal is described gray modulation mode signal, its input signal comprises the output signal of described second level comparator, and the second level subframe of described subframe judging unit output is judged signal; And
Second level second selector is used for the output signal of described second level first selector as selecting signal, its different input signal counter-rotating output of control gating,
Described back level pulse generation unit comprises:
This grade counter is used for counting according to input clock;
This grade pulse duration generator is used to produce this grade pulse duration;
This grade comparator is used for the output of more described this grade counter and this grade pulse duration generator, when both are equal, produces an output signal, and utilizes described this grade counter reset of this output signal control; And
This grade first selector is used for the output signal of described this grade comparator controlling its different input signal counter-rotating output as selecting signal.
Described gray modulation unit comprises chopped-off head cells modulate circuit, according to the chopped-off head gradation data of input, and corresponding chopped-off head reference pulse signal, output chopped-off head output pulse signal also comprises at least one back level cells modulate circuit, described back level cells modulate circuit comprises:
The modulating unit first selector is used under the control of selecting signal, the gating input signal, and it selects signal is this grade gradation data, its input signal is the anti-phase of this grade reference pulse signal and this grade reference pulse signal;
The modulating unit second selector, be used under the control of selecting signal, the gating input signal, it selects signal is the output signal of described modulating unit first selector, its input signal is this grade gradation data and its prime output pulse signal, and its output signal is as this level output modulation signal.
Compared with prior art, the present invention has reduced the number of times and the occurrence probability of short pulse of pulse upset, and has saved power consumption thus owing to export after having realized the merging of pulse, simultaneously, because gray value is divided equally in each subframe, so improved display effect.
Summary of drawings
Fig. 1 is the effect schematic diagram of PWM gray modulation in human eye;
Fig. 2 is modulated at effect schematic diagram in the human eye for FRC;
Fig. 3 is the 5PWM+1FRC pattern diagram;
Fig. 4 is the 4PWM+2FRC pattern diagram;
Fig. 5 is existing gray modulation electrical block diagram;
The impulse waveform that Fig. 6 need import for existing gray modulation circuit, and the gradation data output schematic diagram under this impulse waveform drives;
Fig. 7 is the schematic diagram of pulse-generating circuit of the present invention;
Fig. 8 is the schematic diagram that liquid crystal greyscale of the present invention is realized circuit;
Fig. 9 is the schematic diagram that concerns of frame synchronizing signal of the present invention and line synchronizing signal;
Figure 10 is the electrical block diagram of gray modulation of the present invention unit;
Figure 11 is the electrical block diagram of pulse generation unit of the present invention;
Figure 12 is that gray modulation circuit of the present invention is realized the waveform schematic diagram that pulse merges;
Figure 13 is according to the present invention, needs the pulse excitation waveform imported under the 5PWM+1FRC pattern, and the output of the gradation data under this circuit schematic diagram;
Figure 14 is according to the present invention, needs the pulse excitation waveform imported under the 4PWM+2FRC pattern, and the output of the gradation data under this circuit schematic diagram;
Figure 15 is the rank scanning schematic diagram of liquid crystal panel;
Figure 16 is that the impulse waveform that parity rows pulse of the present invention merges is improved schematic diagram;
Figure 17 is the circuit diagram after according to the present invention described pulse-generating circuit being improved;
Figure 18 is according to the present invention, under the 5PWM+1FRC pattern, realizes that the odd and even number horizontal pulse merges the data waveform schematic diagram of reference pulse waveform and output;
Figure 19 is according to the present invention, under the 4PWM+2FRC pattern, realizes that the odd and even number horizontal pulse merges the data waveform schematic diagram of reference pulse waveform and output;
Figure 20 is in the prior art, under the 5PWM+1FRC pattern, and the upset number of times statistical form of 64 gray values in a subframe; And
Figure 21 is in the prior art, the pulse upset number of times statistical form under the 4PWM+2FRC pattern.
Preferred forms of the present invention
As shown in Figure 7, be pulse-generating circuit schematic diagram provided by the invention, comprise first order pulse generation unit 701, be used to produce pulse signal corresponding to liquid crystal greyscale data lowest order digit certificate, second level pulse generation unit 702, be used to produce pulse signal corresponding to liquid crystal greyscale data time low data, and at least one back level pulse generation unit 703, be used to produce pulse signal corresponding to liquid crystal greyscale data high position data.
Wherein, described first order pulse generation unit 701 comprises: sub-frame count device 7011 and subframe judging unit 7012.Sub-frame count device 7011 is used for sub-frame sync signal and gray modulation mode signal according to input, carries out sub-frame count.Subframe judging unit 7012, be used for output valve and described gray modulation mode signal according to described sub-frame count device, output first order subframe is judged signal S1 and second level subframe judgement signal S2, wherein judges the output level P0 of signal S1 as described first order pulse with described first order subframe.
Described second level pulse generation unit 702 comprises: second level pulse duration generator 7021, second level counter 7022, second level comparator 7023, second level first selector 7024, and second level second selector 7025.Wherein, second level counter 7022 is used for counting according to clock signal; Second level pulse duration generator 7021 is used to produce this grade pulse duration; Second level comparator 7023 is used for the output of described second level pulse duration generator and the output of described second level counter are compared, if conform to then export one efficiency confirmed signal, with described second level counter reset, makes it to count again simultaneously; Second level first selector 7024, be used under the control of selecting signal, the gating input signal, it selects signal is described gray modulation mode signal, its input signal comprises the output signal of described second level comparator, and the second level subframe of described subframe judging unit output is judged signal; Second level second selector 7025 is used for the output signal of described second level first selector as selecting signal, its different input signal counter-rotating output of control gating.
Described back level pulse generation unit comprises: this grade pulse duration generator 7031, this grade counter 7032, this grade comparator 7033, and this grade selector 7034.Wherein, this grade counter 7032 is used for counting according to input clock; This grade pulse duration generator 7031 is used to produce this grade pulse duration; This grade comparator 7033 is used for the output of more described this grade counter and this grade pulse duration generator, when both are equal, produces an output signal, and utilizes this output signal to control described counter reset; This grade first selector 7034 is used for the output signal of described this grade comparator controlling its different input signal counter-rotating output as selecting signal.
Described gray modulation mode signal has been indicated at least two kinds of modulating modes: 5PWM+1FRC pattern and 4PWM+2FRC pattern; Under described 5PWM+1FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd subframe; The output of the described second level of first selector gating, described second level comparator; Under described 4PWM+2FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd, 3,4 subframes; Described second level subframe is judged signal, is output as high level in the 1st, 2,3 subframes, in the 4th subframe output low level; The described second level of first selector gating, described second level subframe is judged signal.
Described each back level pulse-generating circuit, the pulse signal of generation is a cyclical signal, its cycle is respectively 2 times of its prime.
Described back level pulse generation unit is if corresponding to the final stage pulse generation unit of liquid crystal greyscale data highest order data, then and then produce a line synchronizing signal.
As shown in Figure 8, be the electrical block diagram of realization liquid crystal greyscale of the present invention, comprise pulse generation unit 801, gradation data reads control unit 802, gradation data memory 803, frame synchronization generating unit 804, gray modulation unit 805.
Wherein, pulse generation unit 801 is used to produce reference pulse signals at different levels, and generates line synchronizing signal; Gradation data reads control unit 802, is used for carrying out address choice according to described line synchronizing signal; Gradation data memory 803 is used to store gradation datas at different levels, reads the address of control unit output and reads to apply for signal, output gray level data according to described gradation data; Frame synchronization generating unit is used to receive described line synchronizing signal, according to the size generation frame synchronizing signal 804 of liquid crystal panel; Gray modulation unit 805 is used for reference pulse signals described at different levels and gradation data according to input, exports modulated pulse signal.
As shown in Figure 9, pulse generation unit 801 is exported a line synchronizing signal by the timeslice counter.If the 5PWM+1FRC pattern, then timeslice count down at 32 o'clock and provides this signal.If the 4PWM+2FRC pattern, then timeslice count down at 16 o'clock and provides this signal.Line synchronizing signal represents that the data of LCD panel lastrow have shown and finishes that frame synchronization generating unit just adds up after receiving this signal, if the value that adds up reaches the line number of LCD panel, then exports a frame synchronizing signal.This signal is actually the end of a subframe of indication.After pulse-generating circuit receives frame synchronizing signal, judge, restart the output of line synchronizing signal then being in which subframe.
The structure of wherein said gray modulation element circuit, as shown in figure 10, comprise chopped-off head cells modulate circuit 1001, chopped-off head gradation data according to input, and corresponding chopped-off head reference pulse signal, output chopped-off head output pulse signal also comprises at least one back level cells modulate circuit 1002 (element circuit shown in the figure 1003, being the universal architecture form of described back level cells modulate circuit, also is the expression of version of the back level element circuit of afterbody).
Described back level cells modulate circuit (can with reference to 1003) comprising: modulating unit first selector 10031, be used under the control of selecting signal, and the gating input signal, it selects signal is this grade gradation data Q
n, its input signal is this grade reference pulse signal P
nAnti-phase～P with this grade reference pulse signal
nModulating unit second selector 10032, be used under the control of selecting signal, the gating input signal, it selects signal is the output signal Tn of described modulating unit first selector 10031, its input signal is this grade gradation data Qn and its prime output pulse signal Rn-1, and its output signal is as this level output modulation signal Rn.
Among the figure, P is the pulse that pulse-generating circuit generates, and Q is a gradation data.We can see, Q0 through an inverter after, with two inputs of P0 as NOR gate.According to the principle of NOR gate, as long as there is one to be input as 1, then exporting R0 is 0, and therefore as long as Q0 is 0, then R0 is 0, and Q0 is 1, then exports by P0 to determine.Q1 is as the selection signal of selector 1, and two inputs of selector 1 are respectively the anti-phase of P1 and P1.Q1 is 1, then selects P1, and Q1 is 0 selection～P1.And this output T1 is as the selection signal of selector 2, selector 2 be input as 01 and R0, T1 1 selects Q1, T1 0 to select R0, selector 2 is output as R1.
Gradation data can think that one is selected signal, exports behind the strobe pulse.The Q0 correspondence P0, and the Q1 correspondence P1, and the Qn correspondence Pn.If the circuit of pulse generation unit produces some special waveform P0......Pn, then can make the final output Rn of gray modulation circuit is the pulse of a merging, rather than discrete.
The embodiment of the circuit structure of described pulse generation unit can be as shown in figure 11.
At first analyze the generation of P0.Because the P0 correspondence the lowest order of gradation data, and binary each all represent the relation of 2 minutes or 2 times, therefore this has just determined the value of Q0 can only be embodied in the subframe, need carry out special processing to P0, just can so that gradation data all assign in two subframes.Under the 5PWM+1FRC pattern, in the 1st subframe, it is low that P0 is always, and in the 2nd subframe, it is high that P0 is always.Under the 4PWM+2FRC pattern, in the 1st subframe, it is low that P0 is always, and in the 2nd, 3,4 subframes, it is high that P0 is always.The subframe judging unit is according to the value and the gray modulation pattern of sub-frame count device, and decision output P0 is high level or low level.
Analyze the generation of P1.Under the 5PWM+1FRC pattern, P1 is the pulse of one-period.Because corresponding Q1, Q1 is the value of binary representation, if be 1 then the expression gray value is 2.Because the 5PWM+1FRC pattern is divided into two subframes, thus the cycle of P1 should be 1, the output of P1 pulse duration generator is 0.Counter 1 compares with the output of P1 pulse duration generator, thus the value time of decision high-low level.Because compare with 0 all the time, so each clock all will reverse, the acquisition cycle is 1 pulse.Under the 4PWM+2FRC pattern, be divided into 4 subframes, and Q1 can only represent gray scale 2, so the value of Q1 is embodied in the 2nd and the 3rd subframe.Therefore in the 1st, 2,3 subframes, it is high that P1 is always, and in the 4th subframe, it is low that P1 is always.The subframe judging unit is according to the value and the gray modulation pattern of sub-frame count device, and decision output P1 is high level or low level.The output of subframe judging unit, with the output of comparator 1, as the input of selector 0, selector 0 is selected according to the gray modulation pattern.
Analyze the generation of P2.No matter P2 under any modulating mode, is periodic pulse, only different modulating mode pulse width difference.Under the 5PWM+1FRC pattern, the output of P2 pulse duration generator is 1, and under the 4PWM+2FRC pattern, the output of P2 pulse duration generator is 0.Counter and P2 pulse duration generator compare, if counter has reached the output of P2 pulse duration generator, and the then high-low level of P2 counter-rotating, unison counter 2 resets, again since 0 counting.Under the 5PWM+1FRC pattern, the cycle of P2 is exactly 2.Under the 4PWM+2FRC pattern, the cycle of P2 is exactly 1.
Analyze the generation of P3.No matter P3 under any modulating mode, is periodic pulse, only different modulating mode pulse width difference.Under the 5PWM+1FRC pattern, the output of P3 pulse duration generator is 3, and under the 4PWM+2FRC pattern, the output of P2 pulse duration generator is 1.Counter and P3 pulse duration generator compare, if counter has reached the output of P3 pulse duration generator, and the then high-low level of P3 counter-rotating, unison counter 3 resets, again since 0 counting.Under the 5PWM+1FRC pattern, the cycle of P3 is exactly 4.Under the 4PWM+2FRC pattern, the cycle of P3 is exactly 2.
The pulse of back produces with P3 similar.Can produce a plurality of pulses of P0......Pn, n for 64 grades of gray scales, needs 6 gradation data by the bit wide decision of gradation data, so n=5 always.
Counter n reaches maximum, also shows the end that delegation shows, needs to produce line synchronizing signal this moment.
As shown in figure 12, if gradation data is 3, Q2, Q1, Q0, then pulse is also wanted 3, P2, P1, P0.Suppose that gradation data is 5, Q2=1 then, Q1=0, Q0=1.Analyze R0, the T1 of gray modulation circuit, the waveform of R1, T2, can analyze from circuit structure, a back rising edge of a pulse position has been passed in each pulse cleverly, like this, if these two pulses of gating, then two pulses and merge into a long pulse.
On this basis, we consider the 5PWM+1FRC pattern earlier.As shown in figure 13.The 5PWM+1FRC algorithm has 2 subframes, and according to the principle of binary counting, the length of fixed pulse can be selected the weights of binary counting, and promptly 1,2,4,8,16....The corresponding positions of the corresponding gradation data of each pulse will be represented the pulse duration of 0-31 with the combination of 5 kinds of pulse durations.Because data have 6, also need a pulse to represent whether lowest order is effective, because lowest order can only be effective in a subframe, be low so this pulse is the 0th subframe, the 1st subframe is high.
P0: the 0th subframe is always 0, the 1 subframe and is always 1, corresponding Q0;
P1: high-low level all is 1 recurrent pulses, corresponding Q1;
P2: high-low level is 2 recurrent pulses, corresponding Q2;
P3: high-low level is 4 recurrent pulses, corresponding Q3;
P4: high-low level is 8 recurrent pulses, corresponding Q4;
P5: high-low level is 16 recurrent pulses, corresponding Q5.
For example 42=6 ' b101010 has realized 21 pulse duration in the 0th subframe, in circuit, and Q0=0, Q1=1, Q2=0, Q3=1, Q4=0, Q5=1.Be the rising edge that 4 width have been shifted pulse5 onto with pulse3 exactly, pulse0 is the rising edge that 1 width has been shifted pulse3 onto, like this, 1+4+16, three pulses merge and show, have just become one 21 long pulse.
Certainly, be the situation of odd number for gradation data, because the value of Q0 is embodied in the 1st subframe, so the 1st subframe is Duoed a gray value than the 2nd subframe.
For the algorithm of 4PWM+2FRC, 4 subframes are arranged, as shown in figure 14:
P0: the 0th subframe is always 0, the 1,2,3 subframes and is always 1, corresponding Q0;
P1: 0th, 1,2 subframes are always 1, the 3 subframe and are always 0, corresponding Q1;
P2: high-low level all is 1 recurrent pulses, corresponding Q2;
P3: high-low level all is 2 recurrent pulses, corresponding Q3;
P4: high-low level is 4 recurrent pulses, corresponding Q4;
P5: high-low level is 8 recurrent pulses, corresponding Q5.
For example, 41=6 ' b101001, corresponding Q5, Q4, Q3, Q2, Q1, Q0 respectively.Can see that from the realization of circuit the 0th subframe output pulse is that width is two sections pulses merging of 1,2 and 8, the 1st, 2 and 3 subframes output pulse is that width is three sections pulses merging of 2 and 8, so the gray value of output is that 11+10+10+10 equals 41.See the signal data=41 of Figure 14.
Can not be for gradation data by 4 situations about dividing exactly, the value of Q0 is embodied in the 1st subframe, and the value of Q1 is embodied in the 2nd, 3 subframes.
The present invention can also further improve.Because liquid crystal display screen is the scanning of delegation of delegation, delegation scan period, columns is according to all simultaneously effectively, as shown in figure 15.Therefore, when odd-numbered line, pass behind the gradation data waveform, pass before when even number line, as shown in figure 16, just can make the gradation data waveform of odd-numbered line and even number line merge output.
According to this idea, the present invention and then provided a kind of new pulse-generating circuit as shown in figure 17, after original pulse output, increases one-level and selects, if even number line com even judges when signal is engineering noise, and inversion pulse then.That is to say, only judge invalidating signal in even number line, promptly during odd-numbered line (1,3,5...), pulse is just reversed.Nonreversible during even number line (0,2,4...).
By such circuit, for the 5PWM+1FRC pattern, waveform such as Figure 18 of reference pulse P1, the P2 of generation, P3, P4, P5, and the waveform of P0 is constant, and still first subframe is always low, and it is high that second subframe is always.Can see that the waveform of odd-numbered line and even number line is anti-phase, thereby cause the data waveform difference exported.
For the 4PWM+2FRC pattern, reference pulse P2, the P3 of generation, the waveform of P4, P5 as shown in figure 19, and the waveform of P0 and P1 is constant.
Because the pulse of even number line is a high level after the first low level, the pulse of odd-numbered line is a low level behind the first high level, thereby realizes that adjacent two row gradation data pulses merge.Among Figure 18, the gradation data of even number line is 21, the gradation data of odd-numbered line is 17, is 38 data pulse widths thereby formed a length.Among Figure 19, the gradation data of even number line is 11, the gradation data of odd-numbered line is 9, is 20 data pulse widths thereby formed a length.
Industrial applicibility
Because power consumption and digital signal level are closely related, the upset number of times of digital signal level is more many, Then power consumption is more big. 64 gray values as shown in figure 20, have been shown under the 5PWM+1FRC pattern Upset number of times in a subframe (pulse number that namely is divided into).
From statistical angle, 64 grades of gray scales are average appearance, therefore average upset number of times Be 1.5, and the scheme after improving does not need upset because pulse merges all the time, so power consumption Reduced by 33%.
As shown in figure 21, be presented at the pulse upset number of times statistics under the 4PWM+2FRC pattern, one Individual subframe is 16 grades of gray scales to the maximum, and from statistical angle, 64 grades of gray scales are average appearance, Therefore average upset number of times is 1.25, and the scheme after improving merges all the time owing to pulse, no Need the upset, so power-dissipation-reduced 17%.
In sum, pulse-generating circuit provided by the invention and liquid crystal display drive circuit, not only real A plurality of pulses of existing gradation data merge, and have reduced power consumption, and for 5PWM+1FRC and 4PWM+2FRC two kinds of modulation systems have been accomplished gradation data as far as possible in the dividing equally of each subframe, Be conducive to display effect.
Claims (11)
1, a kind of pulse-generating circuit, comprise first order pulse generation unit, be used to produce pulse signal corresponding to liquid crystal greyscale data lowest order digit certificate, second level pulse generation unit, be used to produce pulse signal corresponding to liquid crystal greyscale data time low data, and at least one back level pulse generation unit, be used to produce pulse signal corresponding to liquid crystal greyscale data high position data, it is characterized in that
Described first order pulse generation unit comprises:
The sub-frame count device is used for sub-frame sync signal and gray modulation mode signal according to input, carries out sub-frame count; And
The subframe judging unit, be used for output valve and described gray modulation mode signal according to described sub-frame count device, output first order subframe is judged signal and second level subframe judgement signal, wherein judges the output level of signal as described first order pulse with described first order subframe
Described second level pulse generation unit comprises:
Second level counter is used for counting according to clock signal;
Second level pulse duration generator is used to produce this grade pulse duration;
Second level comparator is used for the output of described second level pulse duration generator and the output of described second level counter are compared, if conform to then export one efficiency confirmed signal, with described second level counter reset, makes it to count again simultaneously;
Second level first selector, be used under the control of selecting signal, the gating input signal, it selects signal is described gray modulation mode signal, its input signal comprises the output signal of described second level comparator, and the second level subframe of described subframe judging unit output is judged signal; And
Second level second selector is used for the output signal of described second level first selector as selecting signal, its different input signal counter-rotating output of control gating,
Described back level pulse generation unit comprises:
This grade counter is used for counting according to input clock;
This grade pulse duration generator is used to produce this grade pulse duration;
This grade comparator is used for the output of more described this grade counter and this grade pulse duration generator, when both are equal, produces an output signal, and utilizes described this grade counter reset of this output signal control; And
This grade first selector is used for the output signal of described this grade comparator controlling its different input signal counter-rotating output as selecting signal.
2, circuit as claimed in claim 1 is characterized in that, described gray modulation mode signal has been indicated at least two kinds of modulating modes: 5PWM+1FRC pattern and 4PWM+2FRC pattern;
Under described 5PWM+1FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd subframe; The output of the described second level of first selector gating, described second level comparator;
Under described 4PWM+2FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd, 3,4 subframes; Described second level subframe is judged signal, is output as high level in the 1st, 2,3 subframes, in the 4th subframe output low level; The described second level of first selector gating, described second level subframe is judged signal.
3, circuit as claimed in claim 1 is characterized in that, described back level pulse generation unit is if corresponding to the final stage pulse generation unit of liquid crystal greyscale data highest order data, then and then produce a line synchronizing signal.
4, circuit as claimed in claim 1 is characterized in that,
Described second level pulse generation unit, also comprise second level third selector, its input signal is the output signal and the inversion signal thereof of described second level second selector, and it selects signal is that even number line is judged signal, when this judgement signal is engineering noise, control its input signal counter-rotating output; And
Described back level pulse generation unit, also comprise this grade second selector, its input signal is the output signal and the inversion signal thereof of this grade first selector, and it selects signal is that even number line is judged signal, when this judgement signal is engineering noise, control its input signal counter-rotating output.
5, circuit as claimed in claim 1 is characterized in that, described each back level pulse generation unit, and the pulse signal of generation is a cyclical signal, its cycle is respectively 2 times of its prime.
6, a kind of circuit of realizing liquid crystal greyscale is characterized in that, comprising:
The pulse generation unit is used to produce reference pulse signals at different levels, and generates line synchronizing signal;
Gradation data reads control unit, is used for carrying out address choice according to described line synchronizing signal;
The gradation data memory is used to store gradation datas at different levels, reads the address of control unit output and reads to apply for signal, output gray level data according to described gradation data;
Frame synchronization generating unit is used to receive described line synchronizing signal, according to the size generation frame synchronizing signal of liquid crystal panel; And
The gray modulation unit is used for reference pulse signals described at different levels and gradation data according to input, exports modulated pulse signal,
Wherein, described pulse generation unit, comprise first order pulse generation unit, be used to produce the reference pulse signal corresponding to liquid crystal greyscale data lowest order digit certificate, pulse generation unit in the second level is used to produce the reference pulse signal corresponding to liquid crystal greyscale data time low data, and at least one back level pulse generation unit, be used to produce reference pulse signal, wherein corresponding to liquid crystal greyscale data high position data
Described first order pulse generation unit comprises:
The sub-frame count device is used for sub-frame sync signal and gray modulation mode signal according to input, carries out sub-frame count; And
The subframe judging unit, be used for output valve and described gray modulation mode signal according to described sub-frame count device, output first order subframe is judged signal and second level subframe judgement signal, wherein judges the output level of signal as described first order pulse with described first order subframe
Described second level pulse generation unit comprises:
Second level counter is used for counting according to clock signal;
Second level pulse duration generator is used to produce this grade pulse duration;
Second level comparator is used for the output of described second level pulse duration generator and the output of described second level counter are compared, if conform to then export one efficiency confirmed signal, with described second level counter reset, makes it to count again simultaneously;
Second level first selector, be used under the control of selecting signal, the gating input signal, it selects signal is described gray modulation mode signal, its input signal comprises the output signal of described second level comparator, and the second level subframe of described subframe judging unit output is judged signal; And
Second level second selector is used for the output signal of described second level first selector as selecting signal, its different input signal counter-rotating output of control gating,
Described back level pulse generation unit comprises:
This grade counter is used for counting according to input clock;
This grade pulse duration generator is used to produce this grade pulse duration;
This grade comparator is used for the output of more described this grade counter and this grade pulse duration generator, when both are equal, produces an output signal, and utilizes described this grade counter reset of this output signal control; And
This grade first selector is used for the output signal of described this grade comparator controlling its different input signal counter-rotating output as selecting signal,
Described gray modulation unit comprises chopped-off head cells modulate circuit, according to the chopped-off head gradation data of input, and corresponding chopped-off head reference pulse signal, output chopped-off head output pulse signal also comprises at least one back level cells modulate circuit, described back level cells modulate circuit comprises:
The modulating unit first selector is used under the control of selecting signal, the gating input signal, and it selects signal is this grade gradation data, its input signal is the anti-phase of this grade reference pulse signal and this grade reference pulse signal; And
The modulating unit second selector, be used under the control of selecting signal, the gating input signal, it selects signal is the output signal of described modulating unit first selector, its input signal is this grade gradation data and its prime output pulse signal, and its output signal is as this level output modulation signal.
7, circuit as claimed in claim 6 is characterized in that, described gray modulation mode signal has been indicated at least two kinds of modulating modes: 5PWM+1FRC pattern and 4PWM+2FRC pattern;
Under described 5PWM+1FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd subframe; The output of the described second level of first selector gating, described second level comparator;
Under described 4PWM+2FRC pattern, the judgment principle of described subframe judging unit is: described first order subframe is judged signal, is output as low level in the 1st subframe, is output as high level in the 2nd, 3,4 subframes; Described second level subframe is judged signal, is output as high level in the 1st, 2,3 subframes, in the 4th subframe output low level; The described second level of first selector gating, described second level subframe is judged signal.
8, circuit as claimed in claim 6 is characterized in that, described back level pulse generation unit is if corresponding to the final stage pulse generation unit of liquid crystal greyscale data highest order data, then and then produce a line synchronizing signal.
9, circuit as claimed in claim 6 is characterized in that,
Described second level pulse generation unit, also comprise second level third selector, its input signal is the output signal and the inversion signal thereof of described second level second selector, and it selects signal is that even number line is judged signal, when this judgement signal is engineering noise, control its input signal counter-rotating output; And
Described back level pulse generation unit, also comprise this grade second selector, its input signal is the output signal and the inversion signal thereof of this grade first selector, and it selects signal is that even number line is judged signal, when this judgement signal is engineering noise, control its input signal counter-rotating output.
10, circuit as claimed in claim 6 is characterized in that, described each back level pulse generation unit, and the pulse signal of generation is a cyclical signal, its cycle is respectively 2 times of its prime.
11, circuit as claimed in claim 6 is characterized in that,
Described modulating unit first selector when this grade gradation data is 1, is selected this grade reference pulse signal, when this grade gradation data is 0, selects the anti-phase of this grade reference pulse signal;
Described modulating unit second selector when described modulating unit first selector is output as 1, is selected this grade gradation data, when described modulating unit first selector is output as 0, selects its prime output pulse signal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2005/001414 WO2007028275A1 (en) | 2005-09-07 | 2005-09-07 | A pulse generating circuit and a circuit which implements lcd gray scale by utilizing the pulse generating circuit |
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| CN101147321A CN101147321A (en) | 2008-03-19 |
| CN100578935C true CN100578935C (en) | 2010-01-06 |
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| CN200580049251A Expired - Fee Related CN100578935C (en) | 2005-09-07 | 2005-09-07 | Pulse production circuit and circuit for realizing liquid crystal gray scale using the same |
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| WO (1) | WO2007028275A1 (en) |
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| CN102625541B (en) * | 2012-04-11 | 2014-06-11 | 深圳市明微电子股份有限公司 | Pulse modulation control method and device for driving LED |
| CN103606362A (en) * | 2013-11-27 | 2014-02-26 | 深圳市长江力伟股份有限公司 | Method of digital pulse width modulation grey level of liquid crystal displayer and liquid crystal displayer |
| CN105824015B (en) * | 2016-04-25 | 2018-11-06 | 中国人民解放军军械工程学院 | A kind of pulse-generating circuit of Phased Array Radar Antenna test device |
| CN114724494B (en) * | 2020-12-22 | 2023-08-18 | 酷矽半导体科技(上海)有限公司 | Display screen, display algorithm, display data processing method and current adjusting method |
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| JP3552699B2 (en) * | 2001-11-08 | 2004-08-11 | セイコーエプソン株式会社 | Pulse width modulation signal generation circuit, data line drive circuit, electro-optical device, and electronic equipment |
| JP2003186452A (en) * | 2001-12-20 | 2003-07-04 | Seiko Instruments Inc | Gradation driving method of liquid crystal display panel |
| EP1341150A1 (en) * | 2002-02-28 | 2003-09-03 | STMicroelectronics S.r.l. | Method for driving LCD modules with scale of greys by PWM technique and reduced power consumption |
| KR100542686B1 (en) * | 2003-07-25 | 2006-01-11 | 매그나칩 반도체 유한회사 | Apparatus of multi gray scale display using pulse width modulation |
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