CN101147321A - Pulse production circuit and circuit for realizing LCD gray scale using the same - Google Patents

Pulse production circuit and circuit for realizing LCD gray scale using the same Download PDF

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Publication number
CN101147321A
CN101147321A CNA2005800492518A CN200580049251A CN101147321A CN 101147321 A CN101147321 A CN 101147321A CN A2005800492518 A CNA2005800492518 A CN A2005800492518A CN 200580049251 A CN200580049251 A CN 200580049251A CN 101147321 A CN101147321 A CN 101147321A
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signal
level
output
subframe
grade
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CN100578935C (en
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文冠果
何剑
何刚跃
赵琮
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Sanechips Technology Co Ltd
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ZTE Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Abstract

The prevent invention provides a pulse generating circuit and a circuit which utilizes the pulse generating circuit to implement LCD gray scale. Said LCD gray scale implementing circuit possesses pulse generating unit, gray data reading control unit, gray data memory, frame synchronization generating unit and gray modulating unit. The pulse generating unit includes a first level pulse generating unit, a second level pulse generating unit and at least one end level pulse generating unit. Said first level pulse generating unit includes subframe counter and subframe determine unit. The second level pulse generating unit has a second level counter and second level pulse width generator, a second level comparator, a second level first selector and second level second selector. The end level pulse generating unit includes corresponding level counter, corresponding level pulse width generator, corresponding level comparator and corresponding level first selector. The invention reduces pulse reversal and saves power consumption, thus may improves display effect.

Description

Pulse-generating circuit and the circuit that liquid crystal greyscale is realized using the pulse-generating circuit
Pulse-generating circuit and the circuit that liquid crystal greyscale is realized using the pulse-generating circuit
Technical field
The present invention relates to a kind of Display Realization circuit of gradation data, more particularly to a kind of liquid crystal greyscale Display Realization circuit of the electronics field higher for power consumption requirements.Background technology
The luminous mechanism of LCDs, is to realize different brightness by being added in the electric field difference on its some picture element.Present driving chip is usually to use dynamic driving method, is divided into row electrode and row electrode.Typically row electrode is progressively scanned with more than 30Hz frame frequency, synchronously applies signal that is bright or not working to row electrode.
Voltage on row electrode is gated or not gated, and is because the pulse signal that Digital Logic produces different in width gives analog drive circuit.When the pulse width of submitting is 0, just do not gate, when the pulse width of submitting is not 0, just gates corresponding time span, also just correspond to different light and shade grades, and we are referred to as gray scale.Therefore in terms of Design of Digital Circuit angle, the pulse width for being only intended for analog drive circuit of care continue how long.The most long persistence level of pulse width, the highest gray scale being just that by.
Any color is all by RGB (RGBs）Three primary colours are mixed to get according to different proportion.If R, G, B have X, Y, Ζ kind probable value respectively, XX Υ Χ Ζ kind colors can be reached altogether, and such as R, G, B respectively there are 64 kinds of gray scale selections, then having 64=262144 kinds of 64 X, 64 X may combination.Realize that circuit is the same due to R, G, B, so needing to design a kind of circuit, 64 gray values can be exported to analog drive circuit with certain waveform.
At present, PWM (Pulse Width Modulation, pulsewidth modulation）Pattern, and FRC (Frame Rate Control, frame frequency control）It is more common gray modulation method.
Pulsewidth modulation, is to be divided into several timeslices within the single pass time, such as 64 grades of gray scales, is just divided into 64 timeslices, if 5/64 gray scale of display, then have driving voltage in only 5/64 time（For same point）, last equivalent voltage just only has completely black 5/64 , see Fig. 1.
Frame frequency is controlled, and is that each timeslice becomes a subframe, is shown 64 grades of gray scales, then will use 64 subframes.We first have to distinguish subframe（Subframe concept).Frame frequency refers to the number of times of the full frame data of scanning in one second kind, and in order to realize FRC, a frame is divided into some subframes.Due to the visual effect of human eye, the brightness felt is the cumulative of all subframes, sees Fig. 2.
It is general by the way of PWM+FRC combinations for the higher gray scale of exponent number.Because gray scale is higher, the frequency needed using PWM is higher, and power consumption is also bigger.5PWM+1FRC, which refers to be divided into two subframes, each subframe, 32 timeslices, therefore can realize 64 grades of gray scales, sees Fig. 3.4P M+2FRC, which refer to be divided into four subframes, each subframe, 16 timeslices, therefore can also realize 64 grades of gray scales, sees Fig. 4.The bit wide of gradation data determines the another U of gray level, in general, and the gray scale that jPWM+kFRC (j, k=0,1,2...) can be realized is2( +, j+k is exactly the bit wide of gradation data.
Gradation data changes into waveform different in size, can be by Fig. 5 circuit, and P is reference pulse, and Q is input data.Gradation data Q may be considered a selection signal, select to export after the reference pulse P as shown in Fig. 6.Q0 correspond to P0, and Q1 correspond to P1, and Qn correspond to Pn.
For example, as shown in fig. 6,42=6'bl01010 of data, corresponds to Q5, Q4, Q3, Q2, Ql, Q0 respectively.It can see from the realization of circuit, output pulse is sectional, and a value needs several sections of pulses to realize.By taking 5PWM+1FRC patterns as an example, for the value that gray scale is 42, each subframe distributes 21, then each subframe is made up of width for 1,4 and 16 three sections of pulses.
Because pulse is ceaselessly overturn, power consumption can be caused to increase, and, short pulse occurs that frequently, because rising and falling edges need the time, burst waveforms distortion may be caused, further, since gray value does not assign to each subframe, so as to also have impact on display effect.The content of the invention
The technical problems to be solved by the invention are the circuit for providing a kind of pulse-generating circuit and being shown using the circuit realiration liquid crystal greyscale, reduce the number of times of pulse upset and the appearance of short pulse, and Gray value is divided equally in each subframe.
The present invention provides a kind of pulse-generating circuit, including first order impulse generating unit, for producing the pulse signal corresponding to liquid crystal greyscale data lowest order digit evidence, second level impulse generating unit, the pulse signal of liquid crystal greyscale data time low data, and at least one rear class impulse generating unit are corresponded to for producing, for producing the pulse signal corresponding to liquid crystal greyscale data high position data, wherein, the first order impulse generating unit, including：
Sub-frame counter, for the sub-frame sync signal according to input and gray modulation mode signal, carries out sub-frame count；And
Subframe judging unit, for the output valve according to the sub-frame counter and the gray modulation mode signal, output first order subframe judges that signal and second level subframe judge signal, wherein judging signal as the output level of the first order pulse using the first order subframe
The second level impulse generating unit, including：
Second level counter, for being counted according to clock signal；
Second level pulse width generator, for producing this grade of pulse width；
Second level comparator, for the output and the output of the second level counter of the second level pulse width generator to be compared, one is exported if being consistent and confirms the validity signal, while by the second level counter resets, being allowed to count again；
Second level first selector, for under the control of selection signal, selected input signal, its selection signal to be the gray modulation mode signal, its input signal includes the output signal of the second level comparator, and the second level subframe of subframe judging unit output judges signal；And
Second level second selector, for the output signal of the second level first selector alternatively signal, its different input signal reversion output of control gating,
The rear class impulse generating unit, including：
This grade of counter, for being counted according to input clock；
This grade of pulse width generator, for producing this grade of pulse width；
This grade of comparator, for the output of relatively more described this grade of counter and this grade of pulse width generator, when both are equal, produces an output signal, and count using output signal control is described Device resets；And
This grade of first selector, for the output signal of this grade of comparator alternatively signal, controlling its different input signal reversion output.
The present invention and then a kind of circuit for realizing liquid crystal greyscale of offer, including：Impulse generating unit, for producing reference pulse signals at different levels, and generates line synchronising signal；Gradation data reads control unit, for carrying out address choice according to the line synchronising signal；Gradation data memory, for storing gradation datas at different levels, address and the reading application signal, output gray level data that control unit is exported are read according to the gradation data；Frame synchronization generating unit, for receiving the line synchronising signal, frame synchronizing signal is produced according to the size of liquid crystal panel；And gray modulation unit, for the reference pulse signals and gradation data at different levels according to input, export modulated pulse signal.
Wherein, the impulse generating unit, including first order impulse generating unit, for producing the reference pulse signal corresponding to liquid crystal greyscale data lowest order digit evidence, second level impulse generating unit, correspond to the reference pulse signal of liquid crystal greyscale data time low data, and at least one rear class impulse generating unit for producing, for producing the reference pulse signal corresponding to liquid crystal greyscale data high position data.Wherein, the first order impulse generating unit, including：
Sub-frame counter, for the sub-frame sync signal according to input and gray modulation mode signal, carries out sub-frame count；And
Subframe judging unit, for the output valve according to the sub-frame counter and the gray modulation mode signal, output first order subframe judges that signal and second level subframe judge signal, wherein judging signal as the output level of the first order pulse using the first order subframe
The second level impulse generating unit, including：
Second level counter, for being counted according to clock signal；
Second level pulse width generator, for producing this grade of pulse width；
Second level comparator, for the output and the output of the second level counter of the second level pulse width generator to be compared, one is exported if being consistent and confirms the validity signal, while by the second level counter resets, being allowed to count again；
Second level first selector, under the control of selection signal, selected input signal, it is selected Signal is selected for the gray modulation mode signal, its input signal includes the output signal of the second level comparator, and the second level subframe of subframe judging unit output judges signal；And
Second level second selector, for the output signal of the second level first selector alternatively signal, its different input signal reversion output of control gating,
The rear class impulse generating unit, including：
This grade of counter, for being counted according to input clock；
This grade of pulse width generator, for producing this grade of pulse width；
This grade of comparator, for the output of relatively more described this grade of counter and this grade of pulse width generator, when both are equal, produces an output signal, and control the counter resets using the output signal；And
This grade of first selector, for the output signal of this grade of comparator alternatively signal, controlling its different input signal reversion output.
The gray modulation unit, including chopped-off head cells modulate circuit, according to the chopped-off head gradation data of input, and its corresponding chopped-off head reference pulse signal, export chopped-off head output pulse signal, in addition at least one rear class cells modulate circuit, the rear class cells modulate circuit, including：
Modulating unit first selector, under the control of selection signal, selected input signal, its selection signal is this grade of gradation data, and it is anti-phase with this grade of reference pulse signal that its input signal is this grade of reference pulse signal；
Modulating unit second selector, for under the control of selection signal, selected input signal, its selection signal is the output signal of the modulating unit first selector, its input signal is this grade of gradation data and its prime output pulse signal, and its output signal exports modulated signal as the level.
Compared with prior art, exported after merging of the present invention due to realizing pulse, reduce the number of times of pulse upset and the occurrence probability of short pulse, and thereby saving power consumption, simultaneously as gray value is divided equally in each subframe, therefore improve display effect.Summary of drawings
Fig. 1 is effect diagram of the FWM gray modulations in human eye； Fig. 2 is the effect diagram that FRC is modulated in human eye；
Fig. 3 is 5PWM+ 1FRC pattern diagrams；
Fig. 4 is 4PWM+2FRC pattern diagrams；
Fig. 5 is existing gray modulate circuit structural representation； '
Fig. 6 is the impulse waveform that existing gray modulate circuit needs to input, and the gradation data under impulse waveform driving exports schematic diagram；
Fig. 7 is the schematic diagram of pulse-generating circuit of the present invention；
Fig. 8 is the schematic diagram that liquid crystal greyscale of the present invention realizes circuit；
Fig. 9 is the relation schematic diagram of frame synchronizing signal of the present invention and line synchronising signal；Figure 10 is the electrical block diagram of gray modulation unit of the present invention；
Figure 11 is the electrical block diagram of impulse generating unit of the present invention；
Figure 12 is that gray modulate circuit of the present invention realizes the waveform diagram that pulse merges；Figure 13 is that according to the present invention, the pulse excitation waveform of input, and the gradation data output schematic diagram under the circuit are needed under 5PWM+1FRC patterns；
Figure 14 is that according to the present invention, the pulse excitation waveform of input, and the gradation data output schematic diagram under the circuit are needed under 4PWM+2FRC patterns；
Figure 15 is the rank scanning schematic diagram of liquid crystal panel；
Figure 16 is that the impulse waveform that odd even horizontal pulse of the present invention merges improves schematic diagram；Figure 17 is the circuit diagram after being improved according to the present invention to the pulse-generating circuit；Figure 18 is according to the present invention, under 5PWM+1FRC patterns, to realize that odd and even number horizontal pulse merges, the data waveform schematic diagram of reference pulse waveform and output；
Figure 19 is according to the present invention, under 4PWM+2FRC patterns, to realize that odd and even number horizontal pulse merges, the data waveform schematic diagram of reference pulse waveform and output；
Figure 20 is in the prior art, under 5PWM+1FRC patterns, upset number of times statistical form of 64 gray values in a sub- frame in；And
Figure 21 is in the prior art, the pulse under 4PWM+2FRC patterns overturns number of times statistical form. The preferred forms of the present invention
As shown in Figure 7, the pulse-generating circuit schematic diagram provided for the present invention, including first order impulse generating unit 701, for producing the pulse signal corresponding to liquid crystal greyscale data lowest order digit evidence, second level impulse generating unit 702, correspond to the pulse signal of liquid crystal greyscale data time low data, and at least one rear class impulse generating unit 703 for producing, for producing the pulse signal corresponding to liquid crystal greyscale data high position data.
Wherein, the first order impulse generating unit 701, including：Sub-frame counter 7011 and subframe judging unit 7012.Sub-frame counter 7011, for the sub-frame sync signal according to input and gray modulation mode signal, carries out sub-frame count.Subframe judging unit 7012, for the output valve according to the sub-frame counter and the gray modulation mode signal, output first order subframe judges that signal S1 and second level subframe judge signal S2, wherein judging signal S1 as the output level P0 of the first order pulse using the first order subframe.
The second level impulse generating unit 702, including：Second level pulse width generator 7021, second level counter 7022, second level comparator 7023, second level first selector 7024, and second level second selector 7025.Wherein, second level counter 7022, for being counted according to clock signal；Second level pulse width generator 7021, for producing this grade of pulse width；Second level comparator 7023, for the output and the output of the second level counter of the second level pulse width generator to be compared, output one confirms the validity signal if being consistent, while by the second level counter resets, being allowed to count again；Second level first selector 7024, for under the control of selection signal, selected input signal, its selection signal is the gray modulation mode signal, its input signal includes the output signal of the second level comparator, and the second level subframe of subframe judging unit output judges signal；Second level second selector 7025, for the output signal of the second level first selector alternatively signal, its different input signal reversion output of control gating.
The rear class impulse generating unit, including：This grade of pulse width generator 7031, this grade of counter 7032, this grade of comparator 7033, and this grade of selector 7034.Wherein, this grade of counter 7032, for being counted according to input clock；This grade of pulse width generator 7031, for producing this Level pulse width；This grade of comparator 7033, for the output of relatively more described this grade of counter and this grade of pulse width generator, when both are equal, produces an output signal, and control the counter resets using the output signal；This grade of first selector 7034, for the output signal of this grade of comparator alternatively signal, controlling its different input signal reversion output.
Described gray modulation mode signal indicates at least two modulating modes：5PWM+ 1FRC patterns and 4PWM+2FRC patterns；Under the 5PWM+ 1FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd subframe；The second level first selector gates the output of the second level comparator；Under the 4PWM+2FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd, 3,4 subframes；The second level subframe judges signal, and high level is output as in the 1st, 2,3 subframes, and low level is exported in the 4th subframe；Raise the selector gating second level subframe and judge signal in the second level.
Each rear class pulse-generating circuit, the pulse signal of generation is cyclical signal, and its cycle is respectively 2 times of its prime.
The rear class impulse generating unit, if corresponding to the final stage impulse generating unit of liquid crystal greyscale data highest order data, then and then produces a line synchronising signal.
As shown in figure 8, be the electrical block diagram of the present invention for realizing liquid crystal greyscale, including impulse generating unit 801, gradation data reads control unit 802, gradation data memory 803, frame synchronization generating unit 804, gray modulation unit 805.
Wherein, impulse generating unit 801, for producing reference pulse signals at different levels, and generate line synchronising signal；Gradation data reads control unit 802, for carrying out address choice according to the line synchronising signal；Gradation data memory 803, for storing gradation datas at different levels, address and the reading application signal, output gray level data that control unit is exported are read according to the gradation data；Frame synchronization generating unit, for receiving the line synchronising signal, frame synchronizing signal 804 is produced according to the size of liquid crystal panel;Gray modulation unit 805, for the reference pulse signals and gradation data at different levels according to input, exports modulated pulse signal. As shown in figure 9, impulse generating unit 801 passage time piece counter, exports a line synchronising signal.If 5PWM+.1FRC patterns, then the signal is provided when timeslice count down to 32.If 4P M+2FRC patterns, then provide the signal when timeslice count down to 16.Line synchronising signal represents that the data of LCD lastrow have shown that completion, and frame synchronization generating unit is received and just added up after the signal, if cumulative value reaches the line number of LCD, exports a frame synchronizing signal.The signal is actually the end for indicating a subframe.Pulse-generating circuit is received after frame synchronizing signal, to judging in which subframe, then restarts the output of line synchronising signal.
The structure of wherein described gray modulation element circuit, as shown in Figure 10, including chopped-off head cells modulate circuit 1001, according to the chopped-off head gradation data of input, and its corresponding chopped-off head reference pulse signal, export chopped-off head output pulse signal, in addition at least one (element circuit 1003 shown in figure of rear class cells modulate circuit 1002, it is both the universal architecture form of the rear class cells modulate circuit, is also the expression of the structure type of the rear class element circuit of afterbody）.
The rear class cells modulate circuit（Refer to 1003), including：Modulating unit first selector 10031, under the control of selection signal, selected input signal, its selection signal to be this grade of gradation data Qn, its input signal is this grade of reference pulse signalWith the anti-phase P of this grade of reference pulse signaln;Modulating unit second selector 10032, for under the control of selection signal, selected input signal, its selection signal is the output signal Tn of the modulating unit first selector 10031, its input signal is this grade of gradation data Qn and its prime output pulse signal Rn-1, and its output signal exports modulated signal Rn as the level.
In figure, P is the pulse that pulse-generating circuit is generated, and Q is gradation data.It will be seen that Q0 is after a phase inverter, with two inputs of the P0 as nor gate.According to the principle of nor gate, if having one input be 1, then export R0 be 0, as long as therefore Q0 be 0, then R0 be 0, Q0 be 1, then export and determined by P0.The selection signal of Q1 alternatively devices 1, two inputs of selector 1 are the anti-phase of P1 and P1 respectively.Q1 is 1, then it is 0 selection Pl to select Pl, Q1.And the selection signal of this output T1 alternatively device 2, the input of selector 2 is Q1 and R0, and T1 is that 1 selection Ql, T1 is 0 to select R0, and selector 2 is output as Rl. Gradation data may be considered and be exported after a selection signal, strobe pulse.Q0 correspond to P0, and Ql correspond to Pl, and Qn correspond to Pn.If the circuit of impulse generating unit produces some special waveforms P0...... Pn, the pulse that the output Rn of gray modulate circuit finally is a merging can be made, rather than it is discrete.
The embodiment of the circuit structure of the impulse generating unit, can be as shown in figure 11.
P0 generation is analyzed first.Because P0 correspond to the lowest order of gradation data, and it is binary each all represent the relations of 2 points or 2 times, this just determines that Q0 value can only be embodied in a sub- frame in, it is therefore desirable to carries out specially treated to P0, can just cause gradation data to assign in two subframes.Under 5PWM+1FRC patterns, in the 1st subframe, P0 is always low, in the 2nd subframe, and P0 is always high.Under 4PWM+2FRC patterns, in the 1st subframe, P0 is always low, the 2nd, 3,4 subframes, P0 is always high.Subframe judging unit determines that output P0 is high level or low level according to the value and gray modulation pattern of sub-frame counter.
Analyze P1 generation.Under 5PWM+1FRC patterns, P1 is the pulse of a cycle.Because correspond to Ql, Ql is the value of binary representation, represents that gray value is 2 if 1.Because 5PWM+1FRC patterns are divided into two subframes, therefore P1 cycle should be 0 for the output of 1, P1 pulse width generators.The output of counter 1 and P1 pulse width generators is compared, so as to determine the Selecting time of low and high level.Because comparing all the time with 0, each clock will be inverted, and obtain the pulse that the cycle is 1.Under 4PWM+2FRC patterns, 4 subframes are divide into, and Q1 can only represent gray scale 2, so Q1 value is embodied in the 2nd and the 3rd subframe.Therefore the 1st, 2,3 subframes, P1 is always high, and in the 4th subframe, P1 is always low.Subframe judging unit determines that output P1 is high level or low level according to the value and gray modulation pattern of sub-frame counter.The output of subframe judging unit, the output with comparator 1, it is alternatively that the input of device 0, selector 0 is selected according to gray modulation pattern.
Analyze P2 generation.P2 is periodically pulsing, only different modulating mode pulse width is different no matter under any modulating mode.Under 5PWM+1FRC patterns, under the output of P2 pulse width generators is Isosorbide-5-Nitrae PWM+2FRC patterns, the output of P2 pulse width generators is 0.Counter is compared with P2 pulse width generators, if counter has reached that P2 pulse widths are produced The low and high level reversion of the output of device, then P2, unison counter 2 resets, started counting up again from 0.5Under PWM+1FRC patterns, P2 cycle is exactly 2.Under 4PWM+2FRC patterns, P2 cycle is exactly 1.
Analyze P3 generation.P3 is periodically pulsing, only different modulating mode pulse width is different no matter under any modulating mode.Under 5PWM+1FRC patterns, under the output of P3 pulse width generators is 3,4PWM+2FRC patterns, the output of P2 pulse width generators is 1.Counter is compared with P3 pulse width generators, if counter has reached the output of P3 pulse width generators, P3 low and high level reversion, unison counter 3 resets, started counting up again from 0.Under 5PWM+1FRC patterns, P3 cycle is exactly 4.Under 4PWM+2FRC patterns, P3 cycle is exactly 2.
Pulses generation below is similar with P3.P0...... Pn multiple pulses can be produced always, n is determined by the bit wide of gradation data, it is necessary to the gradation data of 6 for 64 grades of gray scales, therefore
Counter n reaches maximum, also shows the end that a line is shown, now needs to produce line synchronising signal.
As shown in figure 12, if gradation data is 3, Q2, Ql, Q0, then pulse also want 3, and P2, Pl, POo assume that gradation data is 5, then Q2=l, Q1=0, Q0=1.Analyze R0, Tl, Rl, T2 of gray modulate circuit waveform, it can be analyzed from circuit structure, each pulse, which is cleverly pushed away, has been moved to latter rising edge of a pulse position, so, if gating the two pulses, two pulses simultaneously merge into a long pulse.
On this basis, we first consider 5PWM+1FRC patterns.As shown in Figure 13.5PWM+1FRC algorithms have 2 subframes, according to the principle of binary counting, and the length of fixed pulse can select the weights of binary counting, i.e., 1,2,4,8,16 ....The corresponding positions of one gradation data of each pulse correspondence, 0 is represented with the combination of 5 kinds of pulse widths --- 31 pulse width.Because data have 6, in addition it is also necessary to which a pulse represents whether lowest order is effective, because lowest order can only be in a sub- frame in effectively, the pulse is that the 0th subframe is low, and the 1st subframe is height.
Ρ0:0th subframe is always 0, and the 1st subframe is always 1, correspondence Q0; PI :Low and high level is all 1 recurrent pulses, correspondence Q1;
P2:Low and high level is 2 recurrent pulses, correspondence Q2;
P3 :Low and high level is 4 recurrent pulses, correspondence Q3;
P4:Low and high level is 8 recurrent pulses, correspondence Q4;
P5:Low and high level is 16 recurrent pulses, correspondence Q5.
Such as 42=6' Μ 01010,21 pulse width is realized in the 0th subframe, in circuit, Q0=0, Ql=l, Q2=0, Q3=l, Q4=0, Q5=l.It is the rising edge that 4 width have shifted pulse5 onto exactly by pulse3, pulseO is the rising edge that 1 width has shifted pulse3 onto, so, and 1+4+16, three pulses merge display, just into the long pulse of one 21.
Certainly, when gradation data is odd number, because Q0 value is embodied in the 1st subframe, the 1st subframe gray value more than the 2nd subframe.
For 4PWM+2FRC algorithm, there are 4 subframes, as shown in figure 14：
P0:0th subframe is always 0, the 1st, 2,3 subframes be always 1, correspondence Q0;
P1 :0th, 1,2 subframes be always 1, the 3rd subframe is always 0, correspondence Q1;
P2:Low and high level is all 1 recurrent pulses, correspondence Q2;
P3 :Low and high level is all 2 recurrent pulses, correspondence Q3;
P4:Low and high level is 4 recurrent pulses, correspondence Q4;
P5:Low and high level is 8 recurrent pulses, correspondence Q5.
For example, 41=6, Μ 01001, corresponds to Q5, Q4, Q3, Q2, Ql, Q0 respectively.It can see from the realization of circuit, the output pulse of 0th subframe is that two sections of pulses that width is 1,2 and 8 merge, the subframe output pulse of 1st, 2 and 3 is that three sections of pulses that width is 2 and 8 merge, so the gray value of output is equal to 41 for 11+10+10+10.See Figure 14 signal data=41.
For gradation data can not by 4 the in the case of of dividing exactly, Q0 value is embodied in the 1st subframe, and Q1 value is embodied in the 2nd, 3 subframes.
The present invention can also be improved further.Because liquid crystal display is the scanning of a line a line, a line scan during, column data all and meanwhile effectively, as shown in figure 15.Therefore, in odd-numbered line after gradation data waveform elapse, in even number line before elapse, as shown in figure 16, so that it may so that odd-numbered line and even number Capable gradation data waveform merges output.- according to this idea, the present invention and then a kind of new pulse-generating circuit is provided, such as schemed
Shown in 17, after original pulse output, increase one-level selection, if when even number line com-even judges signal for " invalid ", then pulse is inverted.That is, only judging invalidating signal, i.e. odd-numbered line in even number line（1st, 3,5...) when, pulse is just inverted.Even number line（0th, 2,4...) when it is nonreversible.
By such circuit, for 5FWM+1FRC patterns, reference pulse Pl, P2, P3, P4, P5 of generation waveform such as Figure 18, and P0 waveform is constant, or the first subframe is always low, and the second subframe is always high.It can be seen that, the waveform of odd-numbered line and even number line is anti-phase, so as to cause the data waveform of output different.
For 4PWM+2FRC patterns, reference pulse P2, P3, P4, P5 of generation waveform are as shown in figure 19, and P0 and PI waveform is constant.
Because the pulse of even number line is high level after first low level, the pulse of odd-numbered line is low level after first high level, so as to realize that the pulse of adjacent rows gradation data merges.In Figure 18, the gradation data of even number line is 21, and the gradation data of odd-numbered line is 17, so as to form the data pulse widths that a length is 38.In Figure 19, the gradation data of even number line is 11, and the gradation data of odd-numbered line is 9, so as to form the data pulse widths that a length is 20.Industrial applicibility
Because power consumption is closely related with digital signal level, the upset number of times of digital signal level is more, then power consumption is bigger.As shown in figure 20, it is shown that under 5PWM+1FRC patterns, upset number of times of 64 gray values in a sub- frame in（The pulse number being divided into）.
For statistical angle, 64 grades of gray scales are average appearance, therefore averagely upset number of times is 1.5, and the scheme after improving is to merge all the time due to pulse, it is not necessary to overturn, so lower power consumption 33%. '
As shown in figure 21, the pulse upset number of times statistics under 4PWM+2FRC patterns is shown in, a subframe is 16 grades of gray scales to the maximum, for statistical angle, and 64 grades of gray scales are average appearance, Therefore averagely upset number of times is 1.25, and the scheme after improving is to merge all the time due to pulse, it is not necessary to overturn, so lower power consumption 17%.
In summary, pulse-generating circuit and liquid crystal display drive circuit that the present invention is provided, not only realize that multiple pulses of gradation data merge, ' reduce power consumption, and for two kinds of modulation systems of 5P M+1FRC and 4PWM+2FRC, accomplished gradation data as far as possible each subframe divide equally, be conducive to display effect.

Claims (9)

  1. Claims
    1st, a kind of pulse-generating circuit, including first order impulse generating unit, for producing the pulse signal corresponding to liquid crystal greyscale data lowest order digit evidence, second level impulse generating unit, the pulse signal of liquid crystal greyscale data time low data, and at least one rear class impulse generating unit are corresponded to for producing, for producing the pulse signal corresponding to liquid crystal greyscale data high position data, characterized in that, the first order impulse generating unit, including：
    Sub-frame counter, for the sub-frame sync signal according to input and gray modulation mode signal, carries out sub-frame count；And
    Subframe judging unit, for the output valve according to the sub-frame counter and the gray modulation mode signal, output first order subframe judges that signal and second level subframe judge signal, wherein judge signal as the output level of the first order pulse using the first order subframe, the second level impulse generating unit, including：
    Second level counter, for being counted according to clock signal；
    Second level pulse width generator, for producing this grade of pulse width；
    The:Level comparator, for the output and the output of the second level counter of the second level pulse width generator to be compared, one is exported if being consistent and confirms the validity signal, while by the second level counter resets, being allowed to count again；
    Second level first selector, for under the control of selection signal, selected input signal, its selection signal to be the gray modulation mode signal, its input signal includes the output signal of the second level comparator, and the second level subframe of subframe judging unit output judges signal；And
    Second level second selector, for the output signal of the second level first selector alternatively signal, its different input signal reversion output of control gating, the rear class impulse generating unit, including：
    This grade of counter, for being counted according to input clock; This grade of pulse width generator, for producing this grade of pulse width；
    This grade of comparator, for the output of relatively more described this grade of counter and this grade of pulse width generator, when both are equal, produces an output signal, and control the counter resets using the output signal；And
    This grade of first selector, for the output signal of this grade of comparator alternatively signal, controlling its different input signal reversion output.
    2nd, circuit as claimed in claim 1, it is characterised in that the gray modulation mode signal indicates at least two modulating modes：5PWM+ 1FRC patterns and 4PWM+2FRC patterns；Under the 5PWM+ 1FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd subframe；The second level first selector gates the output of the second level comparator；
    Under the 4PWM+2FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd, 3,4 subframes；The second level subframe judges signal, and high level is output as in the 1st, 2,3 subframes, and low level is exported in the 4th subframe；The second level first selector gates the second level subframe and judges signal.
    3rd, circuit as claimed in claim 1, it is characterised in that the rear class impulse generating unit, if corresponding to the final stage impulse generating unit of liquid crystal greyscale data highest order data, then and then produces a line synchronising signal.
    4th, circuit as claimed in claim 1, it is characterised in that
    The second level impulse generating unit, also include second level third selector, its input signal is the output signal and its inversion signal of the second level second selector, and its selection signal is that even number line judges signal, when this judges signal for " invalid ", the reversion output of its input signal is controlled；And
    ' the rear class impulse generating unit, in addition to this grade of second selector, its input signal is the level The output signal and its inversion signal of first selector, its selection signal are that even number line judges signal, when this judges signal for " invalid ", control the reversion output of its input signal.
    5th, circuit as claimed in claim 1, it is characterised in that each rear class pulse-generating circuit, the pulse signal of generation is cyclical signal, and its cycle is respectively 2 times of its prime.
    6th, a kind of circuit for realizing liquid crystal greyscale, it is characterised in that including：
    Impulse generating unit, for producing reference pulse signals at different levels, and generates line synchronising signal；Gradation data reads control unit, for carrying out address choice according to the line synchronising signal；Gradation data memory, for storing gradation datas at different levels, address and the reading application signal, output gray level data that control unit is exported are read according to the gradation data；
    Frame synchronization generating unit, for receiving the line synchronising signal, frame synchronizing signal is produced according to the size of liquid crystal panel；And
    Gray modulation unit, for the reference pulse signals and gradation data at different levels according to input, export modulated pulse signal, wherein, the impulse generating unit, including first order impulse generating unit, for producing the reference pulse signal corresponding to liquid crystal greyscale data lowest order digit evidence, second level impulse generating unit, correspond to the reference pulse signal of liquid crystal greyscale data time low data for producing, and at least one rear class impulse generating unit, for producing the reference pulse signal corresponding to liquid crystal greyscale data high position data, wherein,
    The first order impulse generating unit, including：
    Sub-frame counter, for the sub-frame sync signal according to input and gray modulation mode signal, carries out sub-frame count；And
    Subframe judging unit, for the output valve according to the sub-frame counter and the gray modulation mode signal, output first order subframe judges that signal and second level subframe judge signal, wherein judging signal as the output level of the first order pulse using the first order subframe The second level impulse generating unit, including：
    Second level counter, for being counted according to clock signal；
    Second level pulse width generator, for producing this grade of pulse width；
    Second level comparator, for the output and the output of the second level counter of the second level pulse width generator to be compared, one is exported if being consistent and confirms the validity signal, while by the second level counter resets, being allowed to count again； '
    Second level first selector, for under the control of selection signal, selected input signal, its selection signal to be the gray modulation mode signal, its input signal includes the output signal of the second level comparator, and the second level subframe of subframe judging unit output judges signal；And
    Second level second selector, for the output signal of the second level first selector alternatively signal, its different input signal reversion output of control gating,
    The rear class impulse generating unit, including-this grade counter, for being counted according to input clock；
    This grade of pulse width generator, for producing this grade of pulse width；
    This grade of comparator, for the output of relatively more described this grade of counter and this grade of pulse width generator, when both are equal, produces an output signal, and control the counter resets using the output signal；And
    This grade of first selector, for with the output signal of this grade of comparator alternatively signal, control its different input signal reversion output, the gray modulation unit, including chopped-off head cells modulate circuit, according to the chopped-off head gradation data of input, and its corresponding chopped-off head reference pulse signal, export chopped-off head output pulse signal, in addition at least one rear class cells modulate circuit, the rear class cells modulate circuit, including：
    Modulating unit first selector, under the control of selection signal, selected input signal, its selection signal is this grade of gradation data, and it is anti-phase with this grade of reference pulse signal that its input signal is this grade of reference pulse signal；And
    Modulating unit second selector, under the control of selection signal, selected input signal, its Selection signal is the output signal of the modulating unit first selector, and its input signal is this grade of gradation data and its prime output pulse signal, and its output signal exports modulated signal as the level.
    7th, circuit as claimed in claim 6, it is characterised in that the gray modulation mode signal indicates at least two modulating modes：5PWM+ 1FRC patterns and 4PWM+2FRC patterns；Under the 5PWM+ 1FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd subframe；The second level first selector gates the output of the second level comparator；
    Under the 4PWM+2FRC patterns, the judgment principle of the subframe judging unit is：Described first order subframe judges signal, and low level is output as in the 1st subframe, and high level is output as in the 2nd, 3,4 subframes；The second level subframe judges signal, and high level is output as in the 1st, 2,3 subframes, and low level is exported in the 4th subframe；The second level first selector gates the second level subframe and judges signal.8th, circuit as claimed in claim 6, it is characterised in that the rear class impulse generating unit, if corresponding to the final stage impulse generating unit of liquid crystal greyscale data highest order data, then and then produces a line synchronising signal.
    9th, circuit as claimed in claim 6, it is characterised in that
    The second level impulse generating unit, also include second level third selector, its input signal is the output signal and its inversion signal of the second level second selector, and its selection signal is that even number line judges signal, when this judges signal for " invalid ", the reversion output of its input signal is controlled；And
    The rear class impulse generating unit, also include this grade of second selector, its input signal is the output signal and its inversion signal of this grade of first selector, and its selection signal is that even number line judges signal, when this judges signal for " invalid ", the reversion output of its input signal is controlled.
    10th, circuit as claimed in claim 6, it is characterised in that each rear class pulses generation electricity Road, the pulse signal of generation is cyclical signal, and its cycle is respectively 2 times of its prime.11st, circuit as claimed in claim 6, it is characterised in that
    The modulating unit first selector, when this grade of gradation data is 1, selects this grade of reference pulse signal, when this grade of gradation data is 0, selects the anti-phase of this grade of reference pulse signal；
    The modulating unit second selector, when the modulating unit first selector is output as 1, selects this grade of gradation data, when the modulating unit first selector is output as 0, selects its prime output pulse signal.
CN200580049251A 2005-09-07 2005-09-07 Pulse production circuit and circuit for realizing liquid crystal gray scale using the same Expired - Fee Related CN100578935C (en)

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CN103606362A (en) * 2013-11-27 2014-02-26 深圳市长江力伟股份有限公司 Method of digital pulse width modulation grey level of liquid crystal displayer and liquid crystal displayer
CN105824015A (en) * 2016-04-25 2016-08-03 中国人民解放军军械工程学院 Pulse generating circuit of phased array radar antenna test device

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CN102625541B (en) * 2012-04-11 2014-06-11 深圳市明微电子股份有限公司 Pulse modulation control method and device for driving LED
CN114724494B (en) * 2020-12-22 2023-08-18 酷矽半导体科技(上海)有限公司 Display screen, display algorithm, display data processing method and current adjusting method

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JP3552699B2 (en) * 2001-11-08 2004-08-11 セイコーエプソン株式会社 Pulse width modulation signal generation circuit, data line drive circuit, electro-optical device, and electronic equipment
JP2003186452A (en) * 2001-12-20 2003-07-04 Seiko Instruments Inc Gradation driving method of liquid crystal display panel
EP1341150A1 (en) * 2002-02-28 2003-09-03 STMicroelectronics S.r.l. Method for driving LCD modules with scale of greys by PWM technique and reduced power consumption
KR100542686B1 (en) * 2003-07-25 2006-01-11 매그나칩 반도체 유한회사 Apparatus of multi gray scale display using pulse width modulation

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CN103606362A (en) * 2013-11-27 2014-02-26 深圳市长江力伟股份有限公司 Method of digital pulse width modulation grey level of liquid crystal displayer and liquid crystal displayer
CN105824015A (en) * 2016-04-25 2016-08-03 中国人民解放军军械工程学院 Pulse generating circuit of phased array radar antenna test device

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