CN100440305C - Liquid crystal greyscale realizing circuit - Google Patents
Liquid crystal greyscale realizing circuit Download PDFInfo
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- CN100440305C CN100440305C CNB2005101026353A CN200510102635A CN100440305C CN 100440305 C CN100440305 C CN 100440305C CN B2005101026353 A CNB2005101026353 A CN B2005101026353A CN 200510102635 A CN200510102635 A CN 200510102635A CN 100440305 C CN100440305 C CN 100440305C
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Abstract
A realization circuit for liquid crystal gray-level relates to impulse production unit, gray-level modulation unit, gray-level data reading control unit, data storage and frame synchronization production unit. The impulse production unit uses for producing seasonal impulse waveform and row synchronization signal. The impulse production unit owns one sub- frame counter, and each place of counter outputs counter replacement control signal and parallel connects with some counters and controls them to replacement. The clock signal of the counter and corresponding pulse width generator inputs to one corresponding comparative device, and the output of comparative device is one selecting signal to selector to select corresponding impulse waveform for high/ low level. The data storage stores gray-level data. The production unit of frame synchronization produces frame synchronization signal. The gray-level modulation unit unites impulse and outputs. It changes gray-level data into impulse with a few logic gates to save area with simple circuit.
Description
Technical field
The present invention relates to a kind of gray modulation unit of LCD Controller chip for driving, in particular a kind of pulse generation unit of liquid crystal greyscale improves.
Background technology
The prior liquid crystal display luminous mechanism is to realize different brightness by the electric field difference that is added on certain picture element.Present chip for driving generally is to adopt the dynamic driving method, is divided into column electrode and row electrode.Generally column electrode is lined by line scan, the row electrode is applied signal bright or that do not work synchronously with the frame frequency more than the 30Hz.
Make on the row electrode the voltage gating or not gating be to give analog drive circuit by the pulse signal that Digital Logic produces different in width to realize.When the pulse width of sending is 0, gating not just, when the pulse width of sending was not 0, with regard to the corresponding time span of gating, also just corresponding different light and shade grade was called gray scale.Therefore from the Design of Digital Circuit angle, how long the pulse width of just giving analog drive circuit of care continues.The longest lasting level of pulse width, the highest gray scale that can realize exactly.
Any color all is to be mixed according to different proportion by RGB (RGB) three primary colours to obtain.If R, G, B have X, Y, Z kind probable value respectively, then can reach X*Y*Z kind color altogether, for example R, G, B respectively have 64 kinds of gray scales to select, and then total 64*64*64=262144 kind may make up.Because the realization circuit striking resemblances of R, G, B so need design a kind of circuit, can be exported to 64 gray-scale values the driving circuit of simulation with certain waveform.
Two kinds of gray modulation methods are generally arranged at present, PWM and FRC.
PWM, i.e. width modulation (Pulse Width Modulation) is to be divided into several timeslices in the time at single pass, as 64 grades of gray scales, just is divided into 64 timeslices; If show 5/64 gray scale, so this point was had only in time of 5/64 driving voltage is arranged, last equivalent voltage just has only complete black 5/64.
FRC, promptly Frame-rate Control (Frame Rate Control) is that each timeslice has become a subframe, shows 64 grades of gray scales, will use 64 subframes so.At first will distinguish the notion of subframe (subframe), frame frequency is meant the number of times of the full frame data of kind interscan in a second, and in order to realize FRC, a frame is divided into some subframes.Because the visual effect of human eye feels that the brightness that is adding up of all subframes, sees effect shown in Figure 1, the gray scale of each point is the subframe cumulative effects by this point.
Than higher gray scale, generally adopt the mode of PWM+FRC combination for exponent number.Because gray scale is high more, the frequency that adopts PWM to need is just high more, and power consumption is also just big more.The bit wide of gradation data has determined grey level, in general, jPWM+kFRC (j, k=0,1,2...) gray scale that can realize is 2
(j+K), j+k is exactly the bit wide of gradation data.If realize 64 grades of gray scales, (j+k) should be 6.5PWM+1FRC is meant and is divided into two subframes that 32 timeslices are arranged in each subframe, sees shown in Figure 2.4PWM+2FRC is meant and is divided into four subframes that 16 timeslices are arranged in each subframe, sees shown in Figure 3.
Existing a kind of circuit structure for the gradation data of each pixel, all has a counter and it to compare as shown in Figure 4, if the value of counter is less than this gray-scale value, then be output as high level, if the value of counter greater than this gray-scale value, then is output as low level.
Though sort circuit realizes that simply, because each pixel all needs three such circuit on the liquid crystal display, a circuit just comprises one 6 digit counter and one 6 bit comparator,, from cost, use upward consideration not adopt with actual so area is very big.
Summary of the invention
The realization circuit that the purpose of this invention is to provide a kind of liquid crystal greyscale, hardware scheme by pulse gate, after each pulse width superposeed, utilize gradation data information, select different pulse widths to realize 64 grades of gray scales constantly in difference, for overcoming the big shortcoming of driving circuit area of prior art.
Technical scheme of the present invention comprises:
A kind of realization circuit of liquid crystal greyscale wherein, comprises that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit;
Described pulse generation unit is used to produce periodic pulse waveform, as the input of described gray modulation unit, generates line synchronizing signal simultaneously; Described pulse generation unit also comprises a sub-frame count device, and its everybody output produces counter reset control signal, a plurality of counters of Parallel Control, and control it and reset; The clock signal of described counter is imported a corresponding comparer with corresponding pulse width generator, and the output of this comparer is used for selecting the back to produce corresponding pulse waveform to high or low level as the selection signal of a selector switch;
Described gradation data reads control module and is used for carrying out address selection according to described line synchronizing signal, reads the input of gradation data as described gray modulation unit from described data-carrier store;
Described data-carrier store is used to store gradation data, reads the address of control module input and reads to apply for signal, output gray level data according to gradation data;
Described frame synchronization generating unit is used to receive described line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal;
Described gray modulation unit is used for input pulse and gradation data, realizes that the pulse of each section gradation data merges back output.
Described circuit, wherein, the pulse width generator in the described pulse generation unit forms according to predetermined width value and the merging of pre-assigned remainder pulse width.
Described circuit, wherein, the waveform of high or low level is exported in described gray modulation unit, and represents different gray scales according to height duration difference.
Described circuit, wherein, described gray modulation unit also comprises: a plurality of selector switchs of cascade, each grade selector switch is with the selection signal of pulse as data, and its input signal is the output of gradation data and upper level selector switch.
The realization circuit of a kind of liquid crystal greyscale provided by the present invention compared with prior art, uses logic gate seldom to realize that gradation data is converted to the function of pulse, has saved area, and has realized that circuit is simple.
Description of drawings
Fig. 1 is the effect synoptic diagram of the gray modulation of prior art at human eye;
Fig. 2 is the 5PWM+1FRC pattern diagram of prior art;
Fig. 3 is the 4PWM+2FRC pattern diagram of prior art;
Fig. 4 is the circuit theory diagrams that the counter mode of prior art realizes liquid crystal greyscale;
Fig. 5 is that pulse gate mode of the present invention realizes the liquid crystal greyscale circuit diagram;
Fig. 6 is gray modulation element circuit figure of the present invention;
Fig. 7 is a pulse generation unit circuit diagram of the present invention;
The driving pulse that Fig. 8 need import for 5PWM+1FRC of the present invention, and the gradation data output effect figure under the gray modulation unit;
The driving pulse that Fig. 9 need import for 4PWM+2FRC of the present invention, and the gradation data output effect figure under the gray modulation unit.
Embodiment
Below in conjunction with accompanying drawing, will the enforcement of technical scheme be described in further detail:
The realization circuit of liquid crystal greyscale of the present invention, structure comprise that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit as shown in Figure 5.
Described pulse generation unit is used to produce periodic pulse waveform, as the input of gray modulation unit, generates line synchronizing signal simultaneously.Described gradation data reads control module and is used for carrying out address selection according to described line synchronizing signal, reads the input of gradation data as described gray modulation unit from described data-carrier store.Described data-carrier store is used to store gradation data, reads the address of control module input and reads to apply for signal, output gray level data according to described gradation data.Described frame synchronization generating unit is used to receive line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal.Described gray modulation unit is used for input pulse and gradation data, realizes that the pulse of each section gradation data merges back output, and the waveform of its output has only high and low two kinds of level, represents different gray scales according to height duration difference.
Can't change owing to show the gradation data of any color, so the design of driving pulse generation unit and gray modulation unit has directly had influence on the waveform that circuit of the present invention is exported.
The present invention adopts the mode of pulse gate, can generate the different pulsewidth A of a group length, B, C, D... in advance, is the unit gating with A, B, C, D....The 5PWM+1FRC algorithm has 2 subframes, and each subframe will represent 0 with the combination of 5 kinds of pulse widths---31 pulse width; The 4PWM+2FRC algorithm has 4 subframes, and each subframe will represent 0 with the combination of 4 kinds of pulse widths---15 pulse width.According to the principle of binary counting, the length of fixed pulse can be selected the weights of binary counting, and promptly 1,2,4,8,16... etc.
In the jPWM+kFRC hybrid modulation, FRC is equivalent to do division, and remainder will add in each subframe, therefore also will generate each pulse that is used for replenishing remainder.Such as, showing among the 4PWM+2FRC that intensity 63 splits 4 subframes, a kind of array mode of each subframe pulse width is (15+1)/(15+1)/(15+1)/15.
Need to find A, B, four values of C, D in the 4PWM+2FRC pattern, need to find A, B, C, D, five values of E in the 5PWM+1FRC pattern, also need remainder in addition, the present invention presses following combination:
1.4PWM+2FRC，{+1，+2，A＝1，B＝2，C＝4，D＝8}
2.5PWM+1FRC，{+1，A＝1，B＝2，C＝4，D＝8，E＝16}
As shown in Figure 5, what deposit in the data-carrier store of the present invention is gradation data, and actual is exactly the information of certain pulsewidth of gating ABCD....Bit5, Bit4, Bit3, Bit2, Bit1, Bit0 respectively corresponding when the 4PWM+ 2FRC pattern 8,4,2,1,2,1}, when the 5PWM+ 1FRC pattern correspondence 16,8,4,2,1,1}, so the binary representation of any one value is exactly a gating signal.For example, 21=6 ' b010101, gating signal that Here it is, under the 5PWM+1FRC pattern, corresponding (E, D, C, B, A ,+1), can obtain by gating C, D and remainder pulse.
The design of gray modulation of the present invention unit is seen shown in Figure 6, imports on the gating when P is high level, and gating is imported down during for low level, can realize the gating of pulse width cleverly.A monochrome (R or G or the B) part of only drawing a pixel among Fig. 6, as can be seen, for 6 bit data, as long as 5 selector switchs just can realize that this will simplify a lot of circuit than original counter method.
As shown in Figure 7, pulse generation unit of the present invention has only one, and the pulse P0......Pn of generation gives the gray modulation units shared of all pixels.Its logic control is a more complicated, all can not have because the remainder pulse is each subframe.At first analyze the generation of P0, see shown in Figure 7ly, counter 0 compares with the output of P0 pulse width generator, if equate then the level counter-rotating of P0 that counter 0 resets, if unequal, then continues counting.P0 pulse width generator has determined the high level lasting time of pulse, the value of this duration and A and remainder pulse, and it is relevant to be in which subframe.How long continue on opportunity that resets of counter 0 and resetting, and be in which subframe, and it is relevant whether to have reached the maximal value of counter.
Generation and the P0 of described pulse P1......Pn are similar, and Pn pulse width generator need be considered all pulsewidth A, B...... and all remainder pulses.
Example for example above-mentioned, 21=6 ' b010101, under the 5PWM+1FRC pattern, corresponding (E, D, C, B, A ,+1), can obtain by gating C, D and remainder pulse, rapid pulse dashes if each subframe is all had a surplus, and then can obtain 22, rather than 21.Therefore, the present invention need be with remainder pulse reasonable distribution in certain subframe.
With 5PWM+1FRC is example, when subframe 0, and p0=(+1), p1=(A+1), p2=(A+B+1), p3=(A+B+C+1), p4=(A+B+C+D+1), and the low level of pulse4 is (E).
Because remainder pulse distribution difference, the width difference of each subframe under the 5PWM+1FRC pattern, has only subframe 0 that extra-pulse is arranged.Subframe 0 is 31+1=32, and subframe 1 is 31, sees shown in Figure 8.
Under the 4PWM+2FRC pattern, subframe 0 extra-pulse is 1, and subframe 1 extra-pulse is 2.Subframe 0 is 15+1=16, and subframe 1 is 15+2=17, and subframe 2 is 15, and subframe 3 is 15, sees shown in Figure 9.
The present invention has adopted the mode of pulse gate, need generate the different pulsewidth ABCD... of a group length in advance, is the unit gating with A, B, C, D....
For example, 42=6 ' b101010, corresponding b5, b4, b3, b2, b1, b0 respectively.When the 5PWM+1FRC pattern:
Gating b5 during P4=0 continues 16 pulses, and gating b3 when P4=1 and P3=1, P2=0 continues 4 pulses, and gating b1 when P4=1 and P3=1, P2=1, P1=1, P0=0 continues 1 pulse.Each subframe continues 21 pulses, two subframes totally 42.
42=6 ' b101010, when the 4PWM+2FRC pattern:
Gating b5 during subframe 0:P4=0 continues 8 pulses, gating b3 when P4=1 and P3=1, P2=0, continue 2 pulses, must P4=1 and P3=1, P2=1, P1=1, P0=0 could gating b1, this condition does not satisfy, so continue 8+2+1=10 pulse;
Gating b5 during subframe 1:P4=0 continues 8 pulses, and gating b3 when P4=1 and P3=1, P2=0 continues 2 pulses, and gating b1 when P4=1 and P3=1, P2=1, P1=1, P0=0 continues 2 pulses.Continue 8+2+2=12 pulse;
Gating b5 during subframe 2:P4=0 continues 8 pulses, and gating b3 when P4=1 and P3=1, P2=0 continues 2 pulses, and gating b1 when P4=1 and P3=1, P2=1, P1=0, P0=0 does not have the pulse of continuing.Continue 8+2=10 pulse;
Gating b5 during subframe 3:P4=0 continues 8 pulses, and gating b3 when P4=1 and P3=1, P2=0 continues 2 pulses, and gating b0 when P4=1 and P3=1, P2=1, P1=0, P0=0 does not have the pulse of continuing.Continue 8+2=10 pulse;
So four subframe 10+12+10+10=42.
The present invention has realized the gray modulation in a kind of lcd drive chip, the hardware scheme of pulse gate has at first been proposed, consider the restriction of hardware resource, improve, after each pulse width superposeed,, select different pulse widths to realize 64 grades of gray scales constantly in difference by gradation data information, saved area greatly, and realized that circuit is simpler.
Should be pointed out that above-mentioned description at specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1, a kind of realization circuit of liquid crystal greyscale is characterized in that, comprises that pulse generation unit, gray modulation unit, gradation data read control module, data-carrier store, frame synchronization generating unit;
Described pulse generation unit is used to produce periodic pulse waveform, as the input of described gray modulation unit, generates line synchronizing signal simultaneously; Described pulse generation unit also comprises a sub-frame count device, and its everybody output produces counter reset control signal, a plurality of counters of Parallel Control, and control it and reset; The clock signal of described counter is imported a corresponding comparer with corresponding pulse width generator, and the output of this comparer is used for selecting the back to produce corresponding pulse waveform to high or low level as the selection signal of a selector switch;
Described gradation data reads control module and is used for carrying out address selection according to described line synchronizing signal, reads the input of gradation data as described gray modulation unit from described data-carrier store;
Described data-carrier store is used to store gradation data, reads the address of control module input and reads to apply for signal, output gray level data according to gradation data;
Described frame synchronization generating unit is used to receive described line synchronizing signal, according to the size of LCD panel, produces frame synchronizing signal;
Described gray modulation unit is used for input pulse and gradation data, realizes that the pulse of each section gradation data merges back output.
2, circuit according to claim 1 is characterized in that, the pulse width generator in the described pulse generation unit forms according to predetermined width value and the merging of pre-assigned remainder pulse width.
3, circuit according to claim 1 is characterized in that, the waveform of high or low level is exported in described gray modulation unit, and represents different gray scales according to height duration difference.
4, circuit according to claim 1, it is characterized in that, described gray modulation unit also comprises: a plurality of selector switchs of cascade, and each grade selector switch is with the selection signal of pulse as data, and its input signal is the output of gradation data and upper level selector switch.
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| CNB2005101026353A CN100440305C (en) | 2005-09-12 | 2005-09-12 | Liquid crystal greyscale realizing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103345900A (en) * | 2013-06-24 | 2013-10-09 | 深圳市明微电子股份有限公司 | LED driving pulse modulation method and system |
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| CN102625541B (en) * | 2012-04-11 | 2014-06-11 | 深圳市明微电子股份有限公司 | Pulse modulation control method and device for driving LED |
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| CN1131993A (en) * | 1994-08-23 | 1996-09-25 | 旭硝子株式会社 | Driving method for a liquid crystal display device |
| JPH1124637A (en) * | 1997-07-04 | 1999-01-29 | Optrex Corp | Drive method for simple matrix liquid crystal display |
| CN1553419A (en) * | 2000-12-27 | 2004-12-08 | ���µ�����ҵ��ʽ���� | Matrix-type display device and driving method thereof |
| WO2004111987A1 (en) * | 2003-06-12 | 2004-12-23 | Koninklijke Philips Electronics N.V. | Energy saving passive matrix display device and method for driving |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1131993A (en) * | 1994-08-23 | 1996-09-25 | 旭硝子株式会社 | Driving method for a liquid crystal display device |
| JPH1124637A (en) * | 1997-07-04 | 1999-01-29 | Optrex Corp | Drive method for simple matrix liquid crystal display |
| CN1553419A (en) * | 2000-12-27 | 2004-12-08 | ���µ�����ҵ��ʽ���� | Matrix-type display device and driving method thereof |
| WO2004111987A1 (en) * | 2003-06-12 | 2004-12-23 | Koninklijke Philips Electronics N.V. | Energy saving passive matrix display device and method for driving |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103345900A (en) * | 2013-06-24 | 2013-10-09 | 深圳市明微电子股份有限公司 | LED driving pulse modulation method and system |
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Application publication date: 20070321 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2015440020319 Denomination of invention: Liquid crystal greyscale realizing circuit Granted publication date: 20081203 License type: Common License Record date: 20151123 |
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