WO2007028275A1

WO2007028275A1 - A pulse generating circuit and a circuit which implements lcd gray scale by utilizing the pulse generating circuit

Info

Publication number: WO2007028275A1
Application number: PCT/CN2005/001414
Authority: WO
Inventors: Guanguo Wen; Jian He; Gangyue He; Cong Zhao
Original assignee: Zte Corporation
Priority date: 2005-09-07
Filing date: 2005-09-07
Publication date: 2007-03-15
Also published as: CN100578935C; CN101147321A

Abstract

The prevent invention provides a pulse generating circuit and a circuit which utilizes the pulse generating circuit to implement LCD gray scale. Said LCD gray scale implementing circuit possesses pulse generating unit, gray data reading control unit, gray data memory, frame synchronization generating unit and gray modulating unit. The pulse generating unit includes a first level pulse generating unit, a second level pulse generating unit and at least one end level pulse generating unit. Said first level pulse generating unit includes subframe counter and subframe determine unit. The second level pulse generating unit has a second level counter and second level pulse width generator, a second level comparator, a second level first selector and second level second selector. The end level pulse generating unit includes corresponding level counter, corresponding level pulse width generator, corresponding level comparator and corresponding level first selector. The invention reduces pulse reversal and saves power consumption, thus may improves display effect.

Description

Pulse generating circuit and circuit for realizing liquid crystal gradation by using the pulse generating circuit

Technical field

The present invention relates to a grayscale data display implementation circuit, and more particularly to a liquid crystal grayscale display implementation circuit for an electronic product field having relatively high power consumption requirements. Background technique

The illumination mechanism of a liquid crystal display is to achieve different brightness by different electric fields applied to a certain pixel point. Current driver chips are generally driven by dynamic driving and are divided into row and column electrodes. The row electrodes are generally scanned progressively at a frame rate of 30 Hz or higher, and a bright or non-bright signal is applied to the column electrodes in synchronization.

The voltage on the column electrodes is strobed or not strobed because the digital logic generates pulse signals of different widths for the analog drive circuit. When the pulse width of the sent pulse is 0, it is not strobed. When the pulse width of the sent pulse is not 0, the corresponding time length is strobed, which corresponds to different brightness and darkness levels. Therefore, from the perspective of digital circuit design, it is only the length of the pulse that is sent to the analog drive circuit. The longest sustained level of the pulse width is the highest gray level that can be achieved.

Any color is obtained by mixing RGB (red, green and blue) three primary colors according to different ratios. If R, G, and B have X, Y, and 可能 possible values, respectively, a total of XX colors can be achieved. For example, R, G, and B each have 64 grayscale selections, and there are 64 X 64 X 64=262144 species. May be combined. Since the implementation circuits of R, G, and B are the same, it is necessary to design a circuit that can output 64 gray values to the analog driving circuit in a certain waveform.

Currently, PWM (Pulse Width Modulation) mode, and FRC (Frame Rate Control) are the more commonly used grayscale modulation methods.

Pulse width modulation is divided into several time slices in one scan time. For 64 gray levels, it is divided into 64 time slices. If 5/64 gray scale is displayed, then only 5/64 of the time has a driving voltage. (for the same point), the final equivalent voltage is only black 5/64 , see Figure 1.

The frame rate control is such that each time slice becomes a sub-frame and 64-level gray scale is displayed, then 64 sub-frames are used. We first want to conceptualize the concept of a molecular frame. The frame rate refers to the number of times of full-screen data scanned within one second. To implement FRC, one frame is divided into several subframes. Due to the visual effect of the human eye, the perceived brightness is the accumulation of all sub-frames, as shown in Figure 2.

For grays with higher order, PWM+FRC is generally used. Because the higher the gray level, the higher the frequency required for PWM, the greater the power consumption. 5PWM+1FRC means dividing into two sub-frames, each with 32 time slices, so 64 levels of gray can be achieved, as shown in Figure 3. 4P M+2FRC refers to dividing into four sub-frames with 16 time slices in each sub-frame, so 64-level gray scale can also be realized, as shown in Fig. 4. The bit width of the gray data determines the gray level. In general, the gray level that jPWM+kFRC (j, k=0, 1, 2...) can achieve is ^{2 ( +} , j + k is gray The bit width of the degree data.

The grayscale data is converted into a waveform of different lengths, which can be passed through the circuit of Fig. 5, P is the reference pulse, and Q is the input data. The gradation data Q can be regarded as a selection signal, and is output after selecting the reference pulse P as shown in Fig. 6. Q0 corresponds to P0, Q1 corresponds to P1, and Qn corresponds to Pn.

For example, as shown in Fig. 6, the data 42 = 6'bl01010, corresponding to Q5, Q4, Q3, Q2, Ql, Q0, respectively. As can be seen from the implementation of the circuit, the output pulse is a segment, and a value requires several pulses to achieve. Taking the 5PWM+1FRC mode as an example, for a value of 42 grayscale, each subframe is assigned 21, and each subframe is composed of three pulses of widths 1, 4, and 16.

Because the pulse is flipped over and over, it will lead to an increase in power consumption. Moreover, short pulses appear frequently, and time required for rising and falling edges may cause distortion of the short pulse waveform. In addition, since the gray values are not equally divided into the respective sub-frames, Also affects the display effect. Summary of the invention

The technical problem to be solved by the present invention is to provide a pulse generating circuit and a circuit for realizing liquid crystal gray scale display by using the circuit, thereby reducing the number of times of pulse inversion and the occurrence of short pulses, and The gray values are equally divided into individual sub-frames.

The present invention provides a pulse generating circuit comprising a first stage pulse generating unit for generating a pulse signal corresponding to the lowest bit data of the liquid crystal gradation data, and a second stage pulse generating unit for generating a gray level data corresponding to the liquid crystal a pulse signal of the lower-order data, and at least one post-stage pulse generating unit, configured to generate a pulse signal corresponding to the high-order data of the liquid crystal gradation data, wherein the first-stage pulse generating unit includes:

a sub-frame counter for performing sub-frame counting based on the input sub-frame synchronization signal and the gradation modulation mode signal;

a subframe determining unit, configured to output, according to an output value of the subframe counter and the grayscale modulation mode signal, a first-level subframe determination signal and a second-level subframe determination signal, where the first level is used a frame determination signal as an output level of the first stage pulse,

The second stage pulse generating unit includes:

a second stage counter for counting according to a clock signal;

a second stage pulse width generator for generating the pulse width of the stage;

a second stage comparator, configured to compare an output of the second stage pulse width generator with an output of the second stage counter, and if yes, output an acknowledge valid signal, and reset the second stage counter , make it count again;

a second stage first selector, configured to, under the control of the selection signal, strobe the input signal, the selection signal being the gradation modulation mode signal, the input signal comprising the output signal of the second stage comparator, and a second-level subframe determination signal output by the subframe determining unit; and

a second stage second selector, configured to use the output signal of the second stage first selector as a selection signal to control the different input signal inversion output of the gate

The post-stage pulse generating unit includes:

The stage counter is used to count according to the input clock;

a pulse width generator for generating the pulse width of the stage;

The stage comparator is configured to compare the output of the stage counter with the pulse width generator of the stage, and when the two are equal, generate an output signal, and use the output signal to control the counting Reset; and

The first selector of the stage is configured to control the different input signal inversion output by using the output signal of the comparator of the stage as a selection signal.

The present invention further provides a circuit for realizing liquid crystal gradation, comprising: a pulse generating unit for generating a reference pulse signal of each stage, and generating a line synchronizing signal; a gray data reading control unit for using the line synchronizing signal Performing address selection; a grayscale data storage for storing gray level data of each level, reading the address and the read request signal output by the control unit according to the gray data, and outputting the gray data; the frame synchronization generating unit, for receiving the a line synchronization signal is generated, and a frame synchronization signal is generated according to a size of the liquid crystal panel; and a gray level modulation unit is configured to output the modulated pulse signal according to the input of the reference pulse signals and the gray scale data.

The pulse generating unit includes a first stage pulse generating unit for generating a reference pulse signal corresponding to the lowest bit data of the liquid crystal gradation data, and a second stage pulse generating unit for generating the corresponding gray level data of the liquid crystal The reference pulse signal of the lower order data, and at least one post-stage pulse generating unit for generating a reference pulse signal corresponding to the high order data of the liquid crystal gradation data. The first stage pulse generating unit includes:

The second stage pulse generating unit includes:

a second stage counter for counting according to a clock signal;

a second stage first selector for strobing the input signal under the control of the selection signal The selection signal is the gradation modulation mode signal, and the input signal includes an output signal of the second-stage comparator and a second-level sub-frame determination signal output by the sub-frame determination unit;

The post-stage pulse generating unit includes:

The stage counter is used to count according to the input clock;

a pulse width generator for generating the pulse width of the stage;

The stage comparator is configured to compare the output of the stage counter with the pulse width generator of the stage, and when the two are equal, generate an output signal, and use the output signal to control the reset of the counter; and

The gradation modulating unit includes a first-stage unit modulating circuit, and outputs a first-stage output pulse signal according to the input first-level gradation data and its corresponding first-level reference pulse signal, and further includes at least one post-stage unit modulating circuit. The subsequent unit modulation circuit includes:

a first selector of the modulating unit, configured to strobe the input signal under the control of the selection signal, wherein the selection signal is the gray level data of the stage, and the input signal is an inversion of the reference pulse signal of the stage and the reference pulse signal of the stage;

a second selector of the modulating unit, configured to strobe the input signal under the control of the selection signal, wherein the selection signal is an output signal of the first selector of the modulating unit, and the input signal is the gradation data of the level and the output of the pre-stage The pulse signal, whose output signal is used as the output modulation signal of this stage.

Compared with the prior art, the present invention realizes the combined output of the pulse, reduces the number of times of pulse inversion and the probability of occurrence of short pulses, and thereby saves power consumption, and at the same time, In the sub-frame, the display effect is improved. BRIEF abstract

Figure 1 is a schematic diagram showing the effect of FWM gray scale modulation in the human eye; Figure 2 is a schematic diagram showing the effect of FRC modulation in the human eye;

Figure 3 is a schematic diagram of the 5PWM+ 1FRC mode;

Figure 4 is a schematic diagram of the 4PWM+2FRC mode;

Figure 5 is a schematic structural view of a conventional gradation modulation circuit;

6 is a schematic diagram of a pulse waveform that needs to be input by a conventional gradation modulation circuit, and a gray scale data output driven by the pulse waveform;

Figure 7 is a schematic diagram of a pulse generating circuit according to the present invention;

8 is a schematic diagram of a liquid crystal gradation realizing circuit according to the present invention;

9 is a schematic diagram showing the relationship between a frame synchronization signal and a line synchronization signal according to the present invention; FIG. 10 is a schematic diagram showing the circuit structure of the gradation modulation unit according to the present invention;

11 is a schematic diagram showing the circuit structure of a pulse generating unit according to the present invention;

12 is a schematic diagram of a waveform of a gray-scale modulation circuit for performing pulse combining according to the present invention; FIG. 13 is a schematic diagram of a pulse excitation waveform that needs to be input in a 5PWM+1 FRC mode according to the present invention, and a gray-scale data output diagram under the circuit;

14 is a diagram showing a pulse excitation waveform to be input in a 4PWM+2FRC mode according to the present invention, and a gray scale data output diagram under the circuit;

15 is a schematic view of the row and column scanning of the liquid crystal panel;

Figure 16 is a schematic diagram showing the improvement of the pulse waveform of the odd-even pulse combination according to the present invention; Figure 17 is a circuit diagram showing the improvement of the pulse generation circuit according to the present invention; Figure 18 is a schematic diagram of the 5PWM+1FRC mode according to the present invention. , the odd-numbered and even-line pulse combination, the reference pulse waveform and the output data waveform diagram;

Figure 19 is a diagram showing the data waveforms of the integration of the odd and even line pulses, the reference pulse waveform and the output in the 4PWM+2FRC mode according to the present invention;

20 is a statistical table of the number of times of inversion of 64 gray values in one subframe in the 5PWM+1 FRC mode in the prior art;

21 is a statistical table of pulse inversion times in the 4PWM+2FRC mode in the prior art. BEST MODE FOR CARRYING OUT THE INVENTION

As shown in FIG. 7, a schematic diagram of a pulse generating circuit provided by the present invention includes a first stage pulse generating unit 701 for generating a pulse signal corresponding to the lowest bit data of the liquid crystal gray scale data, and a second stage pulse generating unit 702. And generating at least one pulse signal corresponding to the second-order data of the liquid crystal gradation data, and at least one post-stage pulse generating unit 703 for generating a pulse signal corresponding to the high-order data of the liquid crystal gradation data.

The first stage pulse generating unit 701 includes: a subframe counter 7011 and a subframe determining unit 7012. The sub-frame counter 7011 is configured to perform sub-frame counting according to the input sub-frame synchronization signal and the gradation modulation mode signal. a subframe determining unit 7012, configured to output, according to the output value of the subframe counter and the grayscale modulation mode signal, a first-level subframe determination signal S1 and a second-level subframe determination signal S2, where The primary subframe determination signal S1 is used as the output level P0 of the first-stage pulse.

The second stage pulse generating unit 702 includes: a second stage pulse width generator 7021, a second stage counter 7022, a second stage comparator 7023, a second stage first selector 7024, and a second level second selection. 7025. The second stage counter 7022 is configured to perform counting according to a clock signal; the second stage pulse width generator 7021 is configured to generate the pulse width of the stage; and the second stage comparator 7023 is configured to use the second stage pulse width. The output of the generator is compared with the output of the second stage counter, and if it matches, an acknowledgment valid signal is output, and the second stage counter is reset and recounted; the second stage first selector 7024 is used Under the control of the selection signal, the input signal is strobed, the selection signal is the gradation modulation mode signal, and the input signal includes an output signal of the second-stage comparator, and the output of the sub-frame determination unit The second stage second frame determining unit 7025 is configured to control, by using the output signal of the second stage first selector as a selection signal, to gate the different input signal inversion output.

The post-stage pulse generating unit includes: the stage pulse width generator 7031, the stage counter 7032, the stage comparator 7033, and the stage selector 7034. The stage counter 7032 is configured to count according to an input clock; the stage pulse width generator 7031 is configured to generate the a stage pulse width; the stage comparator 7033 is configured to compare the output of the stage counter and the stage pulse width generator, when the two are equal, generate an output signal, and use the output signal to control the counter to be reset; The first stage selector 7034 is configured to control the output signal of the stage comparator as a selection signal to control the different input signal inversion output.

The gradation modulation mode signal indicates at least two modulation modes: 5PWM+1FRC mode and 4PWM+2FRC mode; in the 5PWM+1FRC mode, the judgment principle of the subframe determination unit is: the first level The sub-frame determination signal is outputted to a low level in the first sub-frame and is outputted to a high level in the second sub-frame; the second-stage first selector strobes the output of the second-stage comparator; In the 4PWM+2FRC mode, the determining principle of the subframe determining unit is: the first-level subframe determining signal is outputted in a low level in the first subframe, and is output in the second, third, and fourth subframes. The second level sub-frame determination signal outputs a high level in the first, second, and third sub-frames, and outputs a low level in the fourth sub-frame; The signal is determined by the second level subframe.

Each of the subsequent stage pulse generating circuits generates a pulse signal which is a periodic signal having a period twice that of its previous stage.

The post-stage pulse generating unit, if it is the last-stage pulse generating unit corresponding to the highest-order data of the liquid crystal gradation data, further generates a line of synchronizing signals.

FIG. 8 is a schematic diagram of a circuit structure for realizing liquid crystal gradation according to the present invention, including a pulse generating unit 801, a grayscale data reading control unit 802, a grayscale data memory 803, a frame synchronization generating unit 804, and a gray scale. Modulation unit 805.

The pulse generating unit 801 is configured to generate a reference pulse signal of each stage, and generate a line synchronization signal; a gray data reading control unit 802, configured to perform address selection according to the line synchronization signal; and a gray data memory 803, And storing the gray scale data of each level, and outputting the gray scale data according to the address and the read application signal output by the gray data reading control unit; the frame synchronization generating unit is configured to receive the line synchronization signal according to the size of the liquid crystal panel A frame synchronization signal 804 is generated; a gray level modulation unit 805 is configured to output the modulated pulse signal according to the input of the reference pulse signals and the gray scale data. As shown in Fig. 9, the pulse generating unit 801 outputs a line synchronizing signal through a time slice counter. If it is 5PWM+.1FRC mode, the signal is given when the time slice counts to 32. In the case of 4P M+2FRC mode, the signal is given when the time slice counts to 16. The line sync signal indicates that the data of one line on the LCD panel has been displayed, and the frame sync generating unit accumulates the signal after receiving the signal. If the accumulated value reaches the number of lines of the LCD panel, a frame sync signal is output. This signal actually indicates the end of a sub-frame. After receiving the frame sync signal, the pulse generating circuit judges which sub-frame is in, and then restarts the output of the line synchronizing signal.

The structure of the gradation modulation unit circuit, as shown in FIG. 10, includes a first-stage unit modulation circuit 1001, and outputs a first-stage output pulse signal according to the input first-level gradation data and its corresponding first-level reference pulse signal. Also included is at least one post-stage unit modulation circuit 1002 (the unit circuit 1003 shown in the figure is both a general structural form of the post-stage unit modulation circuit and a representation of the structural form of the last-stage post-stage unit circuit).

The subsequent unit modulation circuit (refer to 1003), comprising: a first modulation unit selector 10031, under control of selection signal, the gate input signal, a selection signal for which the gray level data Q _n, which Is the input signal the reference pulse signal of this level? „Inverting from the reference pulse signal of the stage~P _{n; the} second selector 10032 of the modulating unit is configured to strobe the input signal under the control of the selection signal, and the selection signal is the first selector 10031 of the modulating unit The output signal Tn has an input signal of the gray scale data Qn of the stage and its output pulse signal Rn-1 of the preceding stage, and an output signal thereof outputs the modulation signal Rn as the stage.

In the figure, P is a pulse generated by a pulse generating circuit, and Q is gradation data. We can see that after Q0 passes through an inverter, it is used as the two inputs of the NOR gate with P0. According to the principle of NOR gate, as long as one input is 1, the output R0 is 0. Therefore, as long as Q0 is 0, then R0 is 0 and Q0 is 1, the output is determined by P0. Q1 is the selection signal of the selector 1, and the two inputs of the selector 1 are the inversion of P1 and P1, respectively. If Q1 is 1, select Pl, and if Q1 is 0, select ~Pl. The output T1 is again used as the selection signal of the selector 2, the input of the selector 2 is Q1 and R0, the T1 is 1 to select Q1, the T1 is 0 to select R0, and the selector 2 is output as R1. The gray scale data can be regarded as a selection signal, and the pulse is selected and output. Q0 corresponds to P0, Ql corresponds to Pl, and Qn corresponds to Pn. If the circuitry of the pulse generation unit produces some special waveforms P0...Pn, then the final output Rn of the gradation modulation circuit can be a combined pulse, rather than discrete.

An embodiment of the circuit structure of the pulse generating unit can be as shown in FIG.

First analyze the generation of P0. Because P0 corresponds to the lowest bit of the grayscale data, and each bit of the binary represents a relationship of 2 or 2 times, which determines that the value of Q0 can only be reflected in one subframe, so special processing of P0 is required. , can make the grayscale data evenly divided into two sub-frames. In 5PWM+1FRC mode, P0 is always low in the 1st subframe, and P0 is always high in the 2nd subframe. In 4PWM+2FRC mode, P0 is always low in the 1st subframe, and P0 is always high in the 2nd, 3rd, and 4th subframes. The sub-frame judging unit determines whether the output P0 is high level or low level according to the value of the sub-frame counter and the gradation modulation mode.

Analyze the production of P1. In 5PWM+1FRC mode, P1 is a periodic pulse. Since Ql corresponds to Ql, Ql is the value represented by binary, and if it is 1, the gray value is 2. Since the 5PWM+1FRC mode is divided into two sub-frames, the period of P1 should be 1, and the output of the P1 pulse width generator is 0. Counter 1 is compared to the output of the P1 pulse width generator to determine the time of the high and low levels. Because it is always compared to 0, each clock is inverted to obtain a pulse with a period of one. In 4PWM+2FRC mode, it is divided into 4 sub-frames, and Q1 can only represent gray level 2, so the value of Q1 is reflected in the 2nd and 3rd sub-frames. Therefore, in the first, second, and third sub-frames, P1 is always high, and in the fourth sub-frame, P1 is always low. The subframe judging unit determines whether the output P1 is high or low according to the value of the sub-frame counter and the gradation modulation mode. The output of the sub-frame judging unit, and the output of the comparator 1, as the input of the selector 0, the selector 0 is selected in accordance with the gradation modulation mode.

Analyze the production of P2. P2 is a periodic pulse in any modulation mode, except that the pulse widths of different modulation modes are different. In 5PWM+1FRC mode, the output of the P2 pulse width generator is 1,4PWM+2FRC mode, and the output of the P2 pulse width generator is 0. The counter is compared with the P2 pulse width generator, if the counter reaches the P2 pulse width The output of the device, then the high and low levels of P2 are inverted, and the counter 2 is reset, counting from 0 again. ^{5 In} PWM+1FRC mode, the period of P2 is 2. In 4PWM+2FRC mode, the period of P2 is 1.

Analyze the production of P3. P3 is a periodic pulse in any modulation mode, except that the pulse widths of different modulation modes are different. In 5PWM+1FRC mode, the output of the P3 pulse width generator is 3, 4PWM+2FRC mode, and the output of the P2 pulse width generator is 1. The counter is compared with the P3 pulse width generator. If the counter reaches the output of the P3 pulse width generator, the high and low levels of P3 are inverted, and the counter 3 is reset, counting again from 0. In 5PWM+1FRC mode, the period of P3 is 4. In 4PWM+2FRC mode, the period of P3 is 2.

The latter pulse generation is similar to P3. Multiple pulses of P0...Pn can always be generated, n is determined by the bit width of the grayscale data, and for 64-level grayscale, 6-bit grayscale data is required, so

The counter n reaches the maximum value and also indicates the end of a line of display, at which point a line sync signal needs to be generated.

As shown in Figure 12, if the gradation data is 3 bits, Q2, Ql, Q0, then the pulse is also 3, P2, Pl, POo assume that the gradation data is 5, then Q2 = l, Q1 = 0, Q0 =1. The waveforms of R0, Tl, Rl, and T2 of the gray-scale modulation circuit are analyzed. From the circuit structure, it can be analyzed that each pulse is subtly shifted to the position of the rising edge of the next pulse, so that if the two pulses are gated, then two The pulses are combined and combined into one long pulse.

Based on this, we first consider the 5PWM+1FRC mode. As shown in Figure 13. The 5PWM+1FRC algorithm has 2 sub-frames. According to the principle of binary counting, the length of the fixed pulse can be selected as the weight of the binary count, that is, 1, 2, 4, 8, 16... Each pulse corresponds to the corresponding bit of a grayscale data, and a combination of five pulse widths is used to represent the pulse width of 0-31. Since the data has 6 bits, a pulse is needed to indicate whether the lowest bit is valid, because the lowest bit can only be valid in one subframe, so the pulse is the 0th subframe is low and the 1st subframe is high.

Ρ0: The 0th subframe is always 0, the 1st subframe is always 1, corresponding to Q0; PI: periodic pulse with high and low levels, corresponding to Q1;

P2: periodic pulse with high and low level 2, corresponding to Q2;

P3: periodic pulse with high and low level of 4, corresponding to Q3;

P4: periodic pulse with high and low level of 8, corresponding to Q4;

P5: A periodic pulse of 16 high and low levels, corresponding to Q5.

For example, 42=6'Μ01010, the pulse width of 21 is realized in the 0th sub-frame, in the circuit, Q0=0, Ql=l, Q2=0, Q3=l, Q4=0, Q5=l. That is, pulse3 is pushed to the rising edge of pulse5, and pulse0 is pushed to the rising edge of pulse3, so that 1+4+16, the three pulses are combined to display a long pulse of 21.

Of course, in the case where the gradation data is an odd number, since the value of Q0 is reflected in the first sub-frame, the first sub-frame has one more gradation value than the second sub-frame.

For the 4PWM+2FRC algorithm, there are 4 sub-frames, as shown in Figure 14:

P0: The 0th subframe is always 0, and the 1st, 2nd, and 3rd subframes are always 1, corresponding to Q0;

P1: The 0th, 1st, and 2nd subframes are always 1, and the 3rd subframe is always 0, corresponding to Q1;

P2: periodic pulse with high and low levels, corresponding to Q2;

P3: periodic pulses with high and low levels of 2, corresponding to Q3;

P4: periodic pulse with high and low level 4, corresponding to Q4;

P5: Periodic pulse with high and low level of 8, corresponding to Q5.

For example, 41=6, Μ01001, which correspond to Q5, Q4, Q3, Q2, Ql, and Q0, respectively. As can be seen from the implementation of the circuit, the 0th sub-frame output pulse is a two-stage pulse combination with widths of 1, 2, and 8, and the first, second, and third sub-frame output pulses are three-segment pulse combining with widths of 2 and 8. , so the gray value of the output is 11+10+10+10 equals 41. See Figure 14 for signal data=41.

For the case where the gradation data cannot be divisible by 4, the value of Q0 is reflected in the first sub-frame, and the value of Q1 is reflected in the 2nd and 3rd sub-frames.

The invention can be further improved. Because the LCD screen is scanned line by line, the column data is all valid at the same time during one line scan, as shown in Figure 15. Therefore, after the odd-numbered lines, the gray-scale data waveform is shifted, and the even-numbered lines are moved forward, as shown in Fig. 16, the odd-numbered lines and the even-numbered lines can be made. The grayscale data waveform of the line is combined and output. - In accordance with this idea, the present invention further provides a new pulse generating circuit, as shown

17 shows that after the original pulse output, the first-order selection is added. If the even-numbered line com- even determines that the signal is "invalid", the pulse is inverted. That is to say, the pulse is inverted only when the even line determines that the signal is invalid, that is, the odd line (1, 3, 5...). Even lines (0, 2, 4...) are not inverted.

According to such a circuit, for the 5FWM+1FRC mode, the waveforms of the generated reference pulses P1, P2, P3, P4, and P5 are as shown in FIG. 18, and the waveform of P0 is unchanged, or the first sub-frame is always low, and the second sub-frame is Always high. It can be seen that the waveforms of the odd and even rows are inverted, resulting in different data waveforms for the output.

For the 4PWM+2FRC mode, the waveforms of the generated reference pulses P2, P3, P4, and P5 are as shown in Figure 19, while the waveforms of P0 and PI are unchanged.

Because the pulse of the even row is the first low level and the high level, the pulse of the odd line is the first high level and then the low level, thereby realizing the merging of the adjacent two rows of gray data pulses. In Fig. 18, the gradation data of the even lines is 21, and the gradation data of the odd lines is 17, thereby forming a data pulse length of 38. In Fig. 19, the gradation data of the even-numbered lines is 11, and the gradation data of the odd-numbered lines is 9, thereby forming a data pulse width of length 20. Industrial applicability

Since the power consumption is closely related to the digital level signal, the more the digital level signal is flipped, the greater the power consumption. As shown in Figure 20, the number of flips of 64 gray values in one sub-frame (i.e., the number of divided pulses) is shown in 5PWM+1FRC mode.

From a statistical point of view, 64 gray levels appear on average, so the average number of flips is 1.5, and the improved scheme is 33% because the pulses are always merged and do not need to be flipped. '

As shown in FIG. 21, the number of pulse inversion times in the 4PWM+2FRC mode is displayed, and one subframe has a maximum of 16 gray levels. From a statistical point of view, 64 gray levels appear on average. Therefore, the average number of flips is 1.25, and the improved scheme is because the pulses are always merged and do not need to be flipped, so the power consumption is reduced by 17%.

In summary, the pulse generating circuit and the liquid crystal display driving circuit provided by the present invention not only realize multiple pulse combining of gray data, but also reduce power consumption, and for 5P M+1FRC and 4PWM+2FRC modulation modes, It achieves the equalization of the grayscale data in each sub-frame as much as possible, which is beneficial to the display effect.

Claims

Claim

A pulse generating circuit comprising a first stage pulse generating unit for generating a pulse signal corresponding to the lowest bit data of the liquid crystal gray scale data, and a second stage pulse generating unit for generating a lower level corresponding to the liquid crystal gray scale data a pulse signal of the data, and at least one post-stage pulse generating unit, configured to generate a pulse signal corresponding to the high-order data of the liquid crystal gradation data, wherein the first-stage pulse generating unit comprises:

a subframe determining unit, configured to output, according to the output value of the subframe counter and the grayscale modulation mode signal, a first-level subframe determination signal and a second-level subframe determination signal, where the first level is used The frame determination signal is used as an output level of the first-stage pulse, and the second-stage pulse generation unit includes:

a second stage counter for counting according to a clock signal;

a first stage comparator for comparing an output of the second stage pulse width generator with an output of the second stage counter, and if yes, outputting an acknowledge valid signal and resetting the second stage counter , make it count again;

a second stage second selector, configured to control, by using an output signal of the second stage first selector as a selection signal, to control a different input signal inversion output thereof, wherein the subsequent stage pulse generating unit comprises:

The stage counter is used to count according to the input clock; a pulse width generator for generating the pulse width of the stage;

The stage comparator is configured to compare the output of the stage counter and the stage pulse width generator, and when the two are equal, generate an output signal, and use the output signal to control the counter to be reset;

2. The circuit of claim 1, wherein the gradation modulation mode signal indicates at least two modulation modes: 5PWM+ 1FRC mode and 4PWM+2FRC mode; in the 5PWM+ 1FRC mode, the sub The judgment principle of the frame determination unit is: the first-level subframe determination signal is outputted to a low level in the first subframe, and is outputted to a high level in the second subframe; the second-stage first selector Swinging an output of the second stage comparator;

In the 4PWM+2FRC mode, the determining principle of the subframe determining unit is: the first-level subframe determining signal is outputted to a low level in the first subframe, and is in the second, third, and fourth sub-frames. The frame output is high level; the second-level sub-frame determination signal outputs a high level in the first, second, and third sub-frames, and outputs a low level in the fourth sub-frame; The device strobes the second level subframe determination signal.

The circuit according to claim 1, wherein said post-stage pulse generating unit, if it is a final-stage pulse generating unit corresponding to the highest-order data of the liquid crystal gradation data, further generates a line of synchronizing signals.

4. The circuit of claim 1 wherein:

The second stage pulse generating unit further includes a second stage third selector, wherein the input signal is an output signal of the second stage second selector and an inverted signal thereof, and the selection signal is an even line determining signal. When the determination signal is "invalid", the input signal is controlled to be inverted; and

The post-stage pulse generating unit further includes a second selector of the stage, the input signal of which is the level The output signal of the first selector and the inverted signal thereof are selected as an even-line determination signal. When the determination signal is "invalid", the input signal is controlled to be inverted.

5. The circuit according to claim 1, wherein each of the subsequent stages of pulse generating circuits generates a pulse signal which is a periodic signal having a period twice that of the preceding stage.

6. A circuit for realizing liquid crystal gradation, comprising:

a pulse generating unit, configured to generate a reference pulse signal of each stage, and generate a line synchronization signal; a grayscale data reading control unit, configured to perform address selection according to the line synchronization signal; and a grayscale data memory for storing gray levels Degree data, according to the grayscale data reading control unit output address and read request signal, output gray scale data;

a frame synchronization generating unit, configured to receive the line synchronization signal, and generate a frame synchronization signal according to a size of the liquid crystal panel; and

a gradation modulating unit, configured to output a modulated pulse signal according to the input of the reference pulse signal and the gradation data, wherein the pulse generating unit includes a first-stage pulse generating unit, configured to generate a corresponding a reference pulse signal of the lowest bit data of the liquid crystal gradation data, a second stage pulse generating unit for generating a reference pulse signal corresponding to the lower order data of the liquid crystal gradation data, and at least one post-stage pulse generating unit for generating a corresponding a reference pulse signal of liquid crystal gradation data high-order data, wherein

The first stage pulse generating unit includes:

a subframe determining unit, configured to output, according to the output value of the subframe counter and the grayscale modulation mode signal, a first-level subframe determination signal and a second-level subframe determination signal, where the first level is used a frame determination signal as an output level of the first stage pulse, The second stage pulse generating unit includes:

a second stage counter for counting according to a clock signal;

a second stage comparator, configured to compare an output of the second stage pulse width generator with an output of the second stage counter, and if yes, output an acknowledge valid signal, and reset the second stage counter , make it count again; '

The post-stage pulse generating unit includes - the stage counter for counting according to an input clock;

a pulse width generator for generating the pulse width of the stage;

a first selector of the stage, configured to control, by using an output signal of the comparator of the stage, a different input signal inversion output, wherein the gray level modulation unit comprises a first stage unit modulation circuit, according to the input The first level gradation data, and the corresponding first stage reference pulse signal, output the first stage output pulse signal, and further comprising at least one post stage unit modulating circuit, the rear stage unit modulating circuit comprising:

a first selector of the modulating unit, configured to strobe the input signal under the control of the selection signal, wherein the selection signal is the gray level data of the stage, and the input signal is an inversion of the reference pulse signal of the stage and the reference pulse signal of the stage; And

a second selector of the modulating unit, configured to strobe the input signal under the control of the selection signal, The selection signal is an output signal of the first selector of the modulation unit, and the input signal is the gray level data of the stage and the output pulse signal of the previous stage, and the output signal thereof is used as the output modulation signal of the stage.

7. The circuit of claim 6, wherein the gradation modulation mode signal indicates at least two modulation modes: 5PWM+ 1FRC mode and 4PWM+2FRC mode; in the 5PWM+ 1FRC mode, the sub The judgment principle of the frame determination unit is: the first-level subframe determination signal is outputted to a low level in the first subframe and is outputted to a high level in the second subframe; the second-stage first selector Swinging an output of the second stage comparator;

The circuit according to claim 6, wherein said post-stage pulse generating unit, if it is a final-stage pulse generating unit corresponding to the highest-order data of the liquid crystal gradation data, further generates a line of synchronizing signals.

9. The circuit of claim 6 wherein:

The post-stage pulse generating unit further includes a second selector of the stage, wherein the input signal is an output signal of the first selector of the stage and an inverted signal thereof, and the selection signal is an even-line determination signal, and the determination signal is “ When it is invalid, it controls its input signal to invert the output.

10. The circuit of claim 6 wherein said each of said subsequent pulses produces electricity The pulse signal generated is a periodic signal whose period is twice that of its previous stage.

11. The circuit of claim 6 wherein:

The first selector of the modulating unit selects the reference pulse signal of the level when the gradation data of the gradation is 1, and selects the inversion of the reference pulse signal when the gradation data of the gradation is 0;

a second selector of the modulating unit, when the output of the first selector of the modulating unit is 1, selecting the gradation data of the gradation, and when the output of the first selector of the modulating unit is 0, selecting the pre-level Output pulse signal.