CN101394703A - Time clock recovery system and method - Google Patents
Time clock recovery system and method Download PDFInfo
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- CN101394703A CN101394703A CNA2008102245205A CN200810224520A CN101394703A CN 101394703 A CN101394703 A CN 101394703A CN A2008102245205 A CNA2008102245205 A CN A2008102245205A CN 200810224520 A CN200810224520 A CN 200810224520A CN 101394703 A CN101394703 A CN 101394703A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a clock recovery system and a clock recovery method. The clock recovery system comprises a local clock module, and a clock signal extraction module. The local clock module is used for providing a clock signal for the clock signal extraction module. The clock signal extraction module comprises a counter (1), a counter (2), a divider (1), a divider (2) and a clock output unit. The clock recovery system recovers the clock signal in a cascade serial input data by extracting the clock signal of the cascade input data. The recovered clock signal has the advantages of high accuracy and low error rate.
Description
Technical field
The present invention relates to a kind of clock recovery system and method, in particular a kind of clock recovery system and method that is used for cascade control single line transmission plan.
Background technology
Along with being extensive use of of LED, adopting LED emission three primary colors to be made in a large number, and be used for message panel or billboard in sports ground, side of buildings, the railway station with the LED display unit that forms image according to pixel.
The LED display unit mainly comprises control circuit and some LED.In LED control field, mainly exist the scheme that 3 kinds of monobus parallel transmission structure, multi-thread (as two lines, four lines) serial transmission structure and single serial transmission structures etc. are used for cascade control signal transmission in the system.
Be illustrated in figure 1 as single serial transmission plan schematic diagram, adopt single holding wire to connect shown in the figure in the system between each light fixture, the control signal of light fixture is sent by the controller of left end, and the light fixture 1 of transmission process successively is to light fixture n from left to right.This cascade system is integrated on a cascade transmission line with clock signal and data-signal, with respect to monobus parallel transmission structure and multi-thread serial transmission structure, under the prerequisite that has guaranteed system's cascade performance, reduced the cost that system complexity and system realize.
In the middle of such system, the control device of each grade light fixture need carry out recovering clock signals to serial input signals, with the sampled value of acquisition lamp point control signal, thereby carries out the control that lamp point shows; On the other hand, system also will rebuild by the form identical with input signal the cascade serial data at output, thereby generates the cascade dateout, and therefore, control device also needs serial input signals is carried out the recovery that data are rebuild clock.
In the middle of existing technical scheme, a kind of method is to adopt fixing cascade serial data bit wide; get the frequency values of a certain frequency division value of local clock frequency as cascade signal; and use this clock signal to the cascade data value of sampling in the fixed position, with the generation that realizes display control signal and the reconstruction of output signal; Another kind method then is the length of the Cycle Length of cascade serial signal and per 1 bit data high-low level to be made scope limit, and use the local clock signal in the relevant position to the cascade signal value of sampling, when the length of cycle of cascade data or high and low level surpasses above-mentioned scope, then be considered as invalid signals.
Therefore existing clock recovery method proposes strict requirement to the cascade serial signal cycle in the whole cascade chain, the antijamming capability that increased the difficulty that system controls, has reduced system; On the other hand, if the antijamming capability of enhanced system, the then necessary Cycle Length that increases cascade signal, and this can reduce the cascade transmission rate, thus reduced the display performance of system.
Therefore, there is defective in prior art, needs further improvement.
Summary of the invention
Technical problem to be solved by this invention is at the deficiencies in the prior art, to provide a kind of clock recovery system and method, especially the clock recovery system and the method for LED control system single serial transmission plan
Technical scheme of the present invention is as follows:
A kind of clock recovery system wherein, comprising: local clock module, clock signal extraction module; Described local clock module is used for providing the local clock signal to described clock signal extraction module; Described clock signal extraction module comprises:
The clock output unit is used for when described ratio is default value, and at the output time of each default value correspondence, export each and pre-set clock signal, wherein, the output time of each adjacent default value correspondence, at least two local clock cycles of space.
Described clock recovery system, wherein, described clock output unit is provided with judgment sub-unit, be used for judging when described divider 2 is output as first default value, second default value, the 3rd default value, export the high level of first clock signal, second clock signal, the 3rd clock signal respectively, the duration of each high level is a local clock cycle.
A kind of clock recovery method, wherein, the method includes the steps of:
A1, transmission local clock signal;
A2, the local clock number that default figure place input signal accumulative total is comprised are counted, and obtain first count results;
A3, the local clock number that every input signal comprised is counted, obtained second count results;
In A4, the described default figure place input signal of calculating, the local clock number that average every input signal comprised obtains the 3rd count results;
The ratio of A5, described second count results of calculating and described the 3rd count results;
A6, when described ratio is default value, at the output time of each default value correspondence, export each and pre-set clock signal, wherein, the output time of each adjacent default value correspondence, at least two local clock cycles of space.
Described clock recovery method, wherein, among steps A 2, the A3, every input signal is the pulse signal of a complete cycle.
Described clock recovery method, wherein, among steps A 2, the A3, described input signal is set to: the signal long with high level time is logical one, the short signal of high level time is a logical zero, and wherein the high level time of logical one is than big at least two local clock cycles of high level time of logical zero.
Described clock recovery method, wherein, in the steps A 6, the output time of each adjacent default value correspondence, two local clock cycles of space.
Described clock recovery method, wherein, in the steps A 6, when described ratio is first default value, second default value, the 3rd default value, at the output time of each default value correspondence, export first clock signal, second clock signal, the 3rd clock signal respectively.
Described clock recovery method, wherein, when exporting first clock signal, second clock signal, the 3rd clock signal respectively, carry out following steps: export the high level of first clock signal, second clock signal, the 3rd clock signal respectively, the duration of each high level is a local clock cycle.
Described clock recovery method, wherein, described first default value, described second default value, described the 3rd default value are respectively 1/2nd, 1/4th, 3/4ths.
Described clock recovery method, wherein, described first default value, described second default value, described the 3rd default value are respectively 5/8ths, 3/8ths, one.
Adopt such scheme,, directly in the cascade serial input data, recover clock signal, increased the flexibility that system realizes, improved the cascade performance by extracting the clock signal of cascade input data.
Description of drawings
Fig. 1 is the single line transmission plan schematic diagram of prior art;
Fig. 2 is the agreement method of per 1 signal of serial data among the present invention;
Fig. 3 is the structural representation of clock recovery system of the present invention;
Fig. 4 is the waveform sequential chart of a preferred embodiment of the present invention;
Fig. 5 is the waveform sequential chart of a preferred embodiment of the present invention;
Fig. 6 is the waveform sequential chart of a preferred embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 3, the invention provides a kind of clock recovery system, this system has comprised local clock module and clock signal extraction module, the local clock module provides the local clock signal for the clock signal extraction module, the clock signal extraction module has comprised counter 1, counter 2, divider 1, divider 2 and clock output unit, wherein, the local clock number of cycles that 1 couple of continuous n of counter position cascade serial input signals sin accumulative total comprises is counted, obtain the first count results time_last, and time_last sent to divider 1, wherein the value of n is by systemic presupposition; Divider 1 obtains the second count results time_last_ave with the value of time_last divided by n, and time_last_ave is sent to divider 2; Counter 2 counts to get count results cnt to the local clock number that each serial input signals sin is comprised, and cnt is sent to divider 2; Divider 2 draws the two ratio clk_choose according to the cnt and the time_last_ave of input, send to the clock output unit, the clock output unit is according to different clk_choose values, when clk_choose is the numerical value of systemic presupposition, at the corresponding output time of this default value, export different clock signals.The value of clk_choose is crucial to realization of the present invention in the present invention, the primary condition that need satisfy for the value of clk_choose is, three time intervals of clk_choose value in the scope of a signal period are at least the twice in local clock cycle, also promptly in a signal period, choose three time points, at least 2 local clock cycles at interval in twos between the each point, could extract three different clock signals discriminatively like this, the cascade serial data that is used for the single line transmission plan is rebuild output.
Such as equaling two/for the moment in the value of clk_choose, in the moment of divider 2 outputs 1/2nd, the clock output unit is exported the first clock signal d_sync; Value at clk_choose equals four/for the moment, in the moment of divider 2 outputs 1/4th, and clock output unit output second clock signal d0_sync; Value at clk_choose equals at 3/4ths o'clock, and in the moment of divider 2 outputs 3/4ths, the clock output unit is exported the 3rd clock signal d1_sync, finishes the process of clock recovery.
Certainly, the invention is not restricted to only recover three clock signals, under the situation of needs, utilize the invention thought of said system, can recover four, five even the clock signal that needs more equally.
The value of time_last and time_last_ave in the said system, be adopt before in the input signal in multibit signal cycle, the sum and the mean value thereof of contained local clock clk number; For example, adopt the sum and the mean value thereof of the contained local clock clk of the input signal number of at least 2 signal periods, but not the contained local clock clk of the input signal of 1 signal period number before, such way can be avoided bigger skew occurring because of input signal sin sudden change causes clock signal d_sync, d0_sync, d1_sync extracting position, thereby mistake appears in the module that makes the back utilize above-mentioned three clock signals to carry out data signal samples.
The invention provides a kind of clock recovery method, the method includes the steps of: the local clock module provides the local clock signal of frequency unanimity to the clock signal extraction module; Counter 1 uses the local clock signal, system is preestablished the local clock number that the fixing cascade input signal of figure place totally comprises count, and obtains the first count results time_last; Counter 2 uses the local clock signal that the local clock number that every input signal comprised is counted, and obtains second count results; Divider 1 calculates in the described default fixedly figure place input signal according to first count results, and the local clock number that average every input signal comprised obtains the 3rd count results time_last_ave; Divider 2 calculates the ratio clk_choose of described second count results and described the 3rd count results.
Then, when described ratio was first default value, the clock output unit was exported first clock signal; When described ratio is second default value, clock output unit output second clock signal; When described ratio was the 3rd default value, the clock output unit was exported the 3rd clock signal; Wherein, the output time of described first default value, second default value, the 3rd default value, at least two local clock cycles of interval in twos.Like this, the high level that can guarantee each clock signal of extracting can not coincide together.
Be the sequential chart of a kind of embodiment of this method as shown in Figure 4, in this sequential chart, the high level time of logical one is 5 local clock cycles, the high level time of logical zero is 2 local clock cycles, the high level time of logical one is than big 3 local clock cycles of high level time of logical zero, the statistics figure place of systemic presupposition is 16, being default counts 16 the local clock number that input signal added up to comprise before the 2nd input signal shown in Fig. 4, first count results is 128 in this example, using 128 in divider 1, to obtain average bits per inch divided by 16 be 8 according to the local clock number time_last_ave that comprises, the ratio of divider 2 output second count results and the 3rd count results, the clock output unit is two/for the moment at divider 2 output ratio clk_choose, export the high level of the first clock signal d_sync signal, at clk_choose is four/for the moment, the high level of output second clock signal d0_sync signal, at clk_choose is 3/4ths o'clock, exports the high level of the 3rd clock signal d1_sync signal.
As shown in Figure 4,1/4th, 1/2nd, 3/4ths mutually between, at interval two local clock cycles.
And above-mentioned 3 high level are all reduced to low level at 1 local clock after the signal period.When the clock output unit is other numerical value at divider 2 output ratio clk_choose, keep the low level of clock signal constant.Make in this way, directly from the cascade signal of input, extract clock signal, do not need to limit the pulsewidth scope of input signal, realized the flexibility requirement of system.
As a kind of signal agreement method, on the basis of embodiment 2, as shown in Figure 2, the cascade input signal uses the pulse signal of a complete cycle as 1, has promptly comprised high level and low level in the middle of the one digit number certificate.Like this, help improving the accuracy that clock signal is extracted.
As a kind of signal agreement method, on the basis of embodiment 2, the cascade input signal can recently be distinguished the logical zero and the logical one of per 1 signal by different duties, and the high level time of logical one is greater than at least two local clock cycles of high level time of logical zero.As shown in Figure 5, it is the waveform sequential chart of the preferred embodiment, in this embodiment, the high level time of logical one is 6 local clock cycles, the high level time of logical zero is 2.5 local clock cycles, the high level time of logical one is than big 3.5 local clock cycles of logical zero high level time, average every the local clock number time_last_ave that comprises of input signal that illustrates before the 2nd input signal 16 is 8, the clock output unit is two/for the moment at clk_choose, export the high level of the first clock signal d_sync, at clk_choose is four/for the moment, the high level of output second clock signal d0_sync, at clk_choose is 3/4ths o'clock, exports the high level of the 3rd clock signal d1_sync, and above-mentioned 3 high level are all reduced to low level at 1 local clock after the cycle.
Again as shown in Figure 6, the high level time of logical one is 9 local clock cycles, the high level time of logical zero is 5 local clock cycles, the high level time of logical one is than big 4 local clock cycles of high level time of logical zero, before the 2nd input signal of diagram, 10 continuous clock numbers that signal added up to comprise are counted, count results is 150, then average every the local clock number time_last_ave that comprises of these 10 input signals is 15, the clock output unit is 7/15ths o'clock at clk_choose, export the high level of the first clock signal d_sync, at clk_choose is 3/15ths o'clock, the high level of output second clock signal d0_sync, at clk_choose is 10/15ths o'clock, export the high level of the 3rd clock signal d1_sync, above-mentioned 3 high level are all reduced to low level at 1 local clock after the cycle.Under every cascade signal high level differs the situation of 4 local clocks, recover three clock signals equally accurately like this, reached the invention effect of expection.
In embodiment 2 to 4, the clock output unit, the method of clock signal can be: when three default values of divider 2 outputs, export the high level of three clock signals respectively, the high level time of this clock signal is fallen through after the time that equates with the local clock cycle, and promptly the duration of each high level is a local clock cycle.Can avoid so at interval hour, extract three clock signal high level close together even coincide together, rebuild and export thereby influence follow-up data at three default value output times.
On the basis of embodiment 5, preferably first default value in divider 2 outputs is two/for the moment, exports the high level of first clock signal; At second default value is four/for the moment, the high level of output second clock signal; At the 3rd default value is 3/4ths o'clock, exports the high level of the 3rd clock signal, and above-mentioned each high level will be low level after through a clock cycle.In this case, between the output time of three default values, at interval two local clock cycles, can extract three clock signals like clockwork.
The first clock signal d_sync signal that obtains by technical solution of the present invention is used for per 1 Bits Serial input signal sin sampled and obtains this signals sampling value; Second clock signal d0_sync signal is used for determining that the high level of logical zero descends constantly when rebuilding output signal, the 3rd clock signal d1_sync is used for determining that the high level of logical one descends constantly when rebuilding output signal.
Should be understood that; for those of ordinary skills; can be improved according to the above description or conversion; under instruction of the present invention, also can select first default value, second default value and the 3rd default value to be respectively 5/8ths, 3/8ths, one such as those skilled in the art; can also select 7/16ths, 3/16ths, 10/16ths or the like values; for such conversion, all should fall into claim protection range of the present invention.
Claims (10)
1, a kind of clock recovery system is characterized in that, comprising: local clock module, clock signal extraction module;
Described local clock module is used for providing the local clock signal to described clock signal extraction module;
Described clock signal extraction module comprises:
Counter 1 is used for the local clock number that default figure place input signal accumulative total comprises is counted, and obtains first count results, sends to divider 1;
Counter 2, the local clock number that is used for every input signal is comprised is counted, and obtains second count results, sends to divider 2;
Divider 1 is used for calculating described default figure place input signal, and the local clock number that average every input signal comprised obtains the 3rd count results, sends to divider 2;
Divider 2 is used to calculate the ratio of described second count results and described the 3rd count results, exports to the clock output unit;
The clock output unit is used for when described ratio is default value, and at the output time of each default value correspondence, export each and pre-set clock signal, wherein, the output time of each adjacent default value correspondence, at least two local clock cycles of space.
2, clock recovery system according to claim 1, it is characterized in that, described clock output unit is provided with judgment sub-unit, be used for judging when described divider 2 is output as first default value, second default value, the 3rd default value, export the high level of first clock signal, second clock signal, the 3rd clock signal respectively, the duration of each high level is a local clock cycle.
3, a kind of clock recovery method is characterized in that, the method includes the steps of:
A1, transmission local clock signal;
A2, the local clock number that default figure place input signal accumulative total is comprised are counted, and obtain first count results;
A3, the local clock number that every input signal comprised is counted, obtained second count results;
In A4, the described default figure place input signal of calculating, the local clock number that average every input signal comprised obtains the 3rd count results;
The ratio of A5, described second count results of calculating and described the 3rd count results;
A6, when described ratio is default value, at the output time of each default value correspondence, export each and pre-set clock signal, wherein, the output time of each adjacent default value correspondence, at least two local clock cycles of space.
4, clock recovery method according to claim 3 is characterized in that, among steps A 2, the A3, every input signal is the pulse signal of a complete cycle.
5, clock recovery method according to claim 3, it is characterized in that, among steps A 2, the A3, described input signal is set to: the signal long with high level time is logical one, the short signal of high level time is a logical zero, and wherein the high level time of logical one is than big at least two local clock cycles of high level time of logical zero.
6, clock recovery method according to claim 3 is characterized in that, in the steps A 6, and the output time of each adjacent default value correspondence, two local clock cycles of space.
7, according to the arbitrary described clock recovery method of claim 3 to 6, it is characterized in that, in the steps A 6, when described ratio is first default value, second default value, the 3rd default value, at the output time of each default value correspondence, export first clock signal, second clock signal, the 3rd clock signal respectively.
8, clock recovery method according to claim 7, it is characterized in that, when exporting first clock signal, second clock signal, the 3rd clock signal respectively, carry out following steps: export the high level of first clock signal, second clock signal, the 3rd clock signal respectively, the duration of each high level is a local clock cycle.
9, clock recovery method according to claim 7 is characterized in that, described first default value, described second default value, described the 3rd default value are respectively 1/2nd, 1/4th, 3/4ths.
10, clock recovery method according to claim 7 is characterized in that, described first default value, described second default value, described the 3rd default value are respectively 5/8ths, 3/8ths, one.
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| CN2008102245205A CN101394703B (en) | 2008-10-17 | 2008-10-17 | Time clock recovery system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102540152A (en) * | 2011-11-25 | 2012-07-04 | 中国船舶重工集团公司第七二四研究所 | Method for improving capacity resistant to strong interference of radar transmitter for MAX 7219 |
| CN112399663A (en) * | 2019-08-13 | 2021-02-23 | 联咏科技股份有限公司 | Light emitting diode driving apparatus and light emitting diode driver |
| US11545081B2 (en) | 2019-08-13 | 2023-01-03 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
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| US11545081B2 (en) | 2019-08-13 | 2023-01-03 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
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