CN100546361C - A kind of high speed and string data converting system - Google Patents
A kind of high speed and string data converting system Download PDFInfo
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- CN100546361C CN100546361C CNB2005100221753A CN200510022175A CN100546361C CN 100546361 C CN100546361 C CN 100546361C CN B2005100221753 A CNB2005100221753 A CN B2005100221753A CN 200510022175 A CN200510022175 A CN 200510022175A CN 100546361 C CN100546361 C CN 100546361C
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Abstract
A kind of high speed and string data converting system that relates to electric numerical data processing, comprise high-speed phase-locked loop, also comprise than bit pad and serializer, wherein, than bit pad the seniority top digit parallel data signal of input is handled with frequency doubling clock, produce the parallel data output signal of lower-order digit: serializer receives the parallel data signal of exporting than bit pad, and serializer produces the serial output data signal according to the clock signal that high-speed phase-locked loop produced; High-speed phase-locked loop comprises control-signals generator and voltage controlled oscillator, control-signals generator is according to the different clocks input signal, produce the phase difference signal, the current controling signal that obtains being correlated with, voltage controlled oscillator produces the clock of N same frequency out of phase according to current controling signal, the phase difference of wherein adjacent two clocks is 360/N °, and the phase difference of N clock and first clock also is 360/N °, and cost of the present invention is low, exploitativeness can be strong.
Description
Technical field
The present invention relates to electric numerical data and handle, relate in particular to a kind of high speed and string data converting system.
Background technology
Digital visual interface (DVI:Digital Visual Interface) is a kind of standard that connects information source system and display device, particularly pure digi-tal display device, such as LCD etc.As shown in Figure 1, a DVI display system comprises a transmitter and a receiver, transmitter receives the parallel signal of image signal processor, these signals comprise data-signal Data, clock signal C lk, data enable signal DE, row synchronous control signal HSYNC, vertical synchronization control signal VSYNC, transmitter can in build in the video card chip, also can appear on the video card printing board PCB with the form of additional chips; Receiver receives serial digital signal, and with its decoding and be delivered in the numerical display device, by the two, the signal that video card sends becomes the image on the numerical display device.
Like this, just can realize this Digital Transmission by the digital visual interface cable, but because what transmitted on the digital visual interface cable is level conversion minimized differential signal (TMDS:Transition Minimized Differential Signaling) data up to 1.65Gbps, so, in transmitter, the parallel data of 165M is converted to the 1.65G serial data.
The method of the parallel/serial conversion of existing data is that to produce frequency be that the clock of 1.65Ghz sends out the data of 10 bits one by one to the high-speed phase-locked loop (PLL:Phase lock loop) with one ten frequency multiplication.
But because frequency of design is quite big up to the phase-locked loop difficulty of 1.65G, its difficulty imbody is in following several aspects:
1.1.65G frequency is too high, if use general live width (as 0.35um) design to implement very difficult.
2. the power consumption that high-speed phase-locked loop produced and the noise of ten frequencys multiplication are bigger, and integrated required area is very big, and cost is higher.
Therefore, prior art cost height, exploitativeness can be poor.
Summary of the invention
The object of the present invention is to provide a kind of cost is low and the exploitativeness energy is strong high speed and string data converting system, to overcome defective of the prior art.
High speed of the present invention and string data converting system, comprise high-speed phase-locked loop, also comprise than bit pad and serializer, wherein, described than bit pad to the input the seniority top digit parallel data signal handle with frequency doubling clock, produce the parallel data output signal of lower-order digit: serializer receives the parallel data signal of exporting than bit pad, and serializer produces the serial output data signal according to the clock signal that high-speed phase-locked loop produced.
Described high-speed phase-locked loop comprises control-signals generator and voltage controlled oscillator, and described control-signals generator produces the phase difference signal, the current controling signal that obtains being correlated with according to the different clocks input signal; Described voltage controlled oscillator is according to the clock of N same frequency out of phase of current controling signal generation, and the phase difference of wherein adjacent two clocks is 360/N °, and the phase difference of N clock and first clock also is 360/N °.
Described control-signals generator receives two different clocks input signals, and the clock signal of described voltage controlled oscillator output feeds back to control-signals generator as a clock input signal, and another clock input signal is relative external timing signal.
Described voltage controlled oscillator also connects driver, and described driver increases driving force to the clock signal of voltage controlled oscillator.
Described control-signals generator comprises 1/2 frequency divider, 1/N frequency divider, phase demodulation/frequency device, charge pump, low pass filter and voltage-current converter, wherein, described 1/2 frequency divider and 1/N output signal of frequency divider are sent to phase demodulation/frequency device, and described 1/2 frequency divider receives external timing signal; Described 1/N frequency divider receives the clock signal of voltage controlled oscillator or driver feedback; Described phase demodulation/frequency device, charge pump link to each other successively with voltage-current converter, and low pass filter is connected between charge pump and the voltage-current converter; Described phase demodulation/frequency device produces the phase difference signal; Described charge pump produces current pulse signal according to the phase difference signal that receives, and low pass filter carries out integration to the current pulse signal that charge pump produces, and produces voltage control signal; Described voltage-current converter is converted to current controling signal with the voltage control signal of input, with the operation of control voltage controlled oscillator.
Described voltage controlled oscillator comprises frequency controller, and the ring oscillator that is connected in turn by a plurality of delay unit input/output terminals, described frequency controller receives the current controling signal that control-signals generator produced, and the output frequency control signal is as the control signal of each delay unit in the ring oscillator.
Each delay unit in the described ring oscillator has one group of differential clocks input, and the differential clock signal of the time-delay of output process simultaneously is to next corresponding delay unit.
Described serializer comprises a plurality of fetch bit logical circuits and combinator circuit, described fetch bit logical circuit is done corresponding fetch bit to each bit in the parallel data signal, and export corresponding data-signal to the combinator circuit, after the combinator circuit receives the output signal of all fetch bit logical circuits, the output serial data signal.
Described fetch bit logical circuit comprises a logic NOT U31A and two logical AND U31B, U31C, wherein, logical AND U31B input signal is: the phase clock signal of this bit, inversion signal with corresponding next phase clock signal, wherein, described next phase clock signal exports logical AND U31B to through logic NOT U31A; Logical AND U31C input signal is: the output signal of data-signal of this bit and logical AND U31B.
Described combinator circuit is logic OR U32A.
Beneficial effect of the present invention is: in the present invention, than bit pad the seniority top digit parallel data signal of input is handled with frequency doubling clock, produce the parallel data output signal of lower-order digit, serializer receives the parallel data signal of exporting than bit pad, serializer is according to clock signal that high-speed phase-locked loop produced, produce the serial output data signal, with respect to prior art, for the parallel data signal of handling same figure place, the present invention is at first by handling with frequency doubling clock the parallel data signal of input than bit pad, for example, parallel data signal for 10, after frequency multiplication, have only 5 parallel-by-bit data-signals, correspondingly high-speed phase-locked loop only needs 5 frequencys multiplication to get final product, like this, in the present invention, just greatly reduce the design difficulty of high-speed phase-locked loop, it realizes that difficulty reduces greatly, the power consumption that high-speed phase-locked loop produced reduces, integrated required area is also corresponding to be reduced, and obviously, has reduced cost widely, in the chip circuit technique thereof, can use the design of general live width, as 0.35um, with regard to no matter in design is still made, exploitativeness of the present invention can be enhanced, and cost is under control.
Description of drawings
Fig. 1 is a DVI display system architectures schematic diagram in the prior art;
Fig. 2 is a general structure schematic diagram of the present invention;
Fig. 3 is an internal structure schematic diagram of the present invention;
Fig. 4 is a high-speed phase-locked loop structural representation of the present invention;
Fig. 5 is a voltage controlled oscillator structural representation of the present invention;
Fig. 6 is a serializer structural representation of the present invention;
Fig. 7 contrasts schematic diagram for the sequential of data-signal, clock signal and output signal among the present invention.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
According to Fig. 2 and Fig. 3, the present invention includes high-speed phase-locked loop 1, than bit pad 2 and serializer 3, seniority top digit parallel data signal than 2 pairs of inputs of bit pad is handled with frequency doubling clock, produce the parallel data output signal of lower-order digit, as shown in Figure 1, after the 10 parallel-by-bit data-signal Data_In process of frequency multiplication than 2 pairs of inputs of bit pad, produce 5 parallel data signal Data_in[4:0], serializer 3 receives the parallel data signal Data_in[4:0 that is exported than bit pad 2], the clock signal that serializer 3 is produced according to high-speed phase-locked loop 1 produces the serial output data signal.
As shown in Figure 3 and Figure 4, high-speed phase-locked loop 1 comprises control-signals generator 11, voltage controlled oscillator 12 and driver 13, control-signals generator 11 receives two different clocks input signal Clk_in, Clk_c, the clock signal of voltage controlled oscillator 12 outputs feeds back to control-signals generator 11 as a clock input signal Clk_c after driver 13 amplifies, clock input signal Clk_in is relative external timing signal, control-signals generator 11 is according to the different clocks input signal, the current controling signal that obtains being correlated with, voltage controlled oscillator 12 produces the clock of N same frequency out of phase according to current controling signal, the phase difference of wherein adjacent two clocks is 360/N °, the phase difference of N clock and first clock also is 360/N °, and the clock signal of 13 pairs of voltage controlled oscillators 12 of driver increases driving force.
As shown in Figure 4, control-signals generator 11 comprises 1/2 frequency divider 111,1/N frequency divider 112, phase demodulation/frequency device 113, charge pump 114, low pass filter 115 and voltage- current converter 116,1/2 frequency divider 111 and 1/N frequency divider 112 output signals are sent to phase demodulation/ frequency device 113,1/2 frequency dividers 111 and receive external timing signal Clk_in; 1/N frequency divider 112 receives the clock signal C lk_c that presses driver 13 feedbacks;
As shown in Figure 4, phase demodulation/frequency device 113, charge pump 114 and voltage-current converter 116 link to each other successively, low pass filter 115 is connected between charge pump 114 and the voltage-current converter 116, phase demodulation/frequency device 113 produces phase difference signal PU, PD, charge pump 114 carries out the charge/discharge lotus according to the phase difference signal PU, the PD that receive to low pass filter 115, produce voltage control signal VFILT, voltage-current converter 115 is converted to current controling signal I_CTL1, I_CTL2 with the voltage control signal VFILT of input.
As shown in Figure 5, voltage controlled oscillator 12 comprises frequency controller 121, and the ring oscillator 122 that is connected in turn by 5 delay unit input/output terminals, in the present embodiment, each delay unit in the ring oscillator 122 has one group of differential clocks input, and the differential clock signal of the time-delay of output process simultaneously is to next corresponding delay unit.
Frequency controller 121 receives current controling signal I_CTL1, the I_CTL2 that voltage-current converter 115 is produced, the output signal of frequency controller 121 is as the control signal of each delay unit in the ring oscillator 122, as shown in Figure 5, exporting adjacent clock skew by 5 delay units is 72 ° 5 phase clock signal Clk1, Clk2, Clk3, Clk4, Clk5, and 5 phase clock signal Clk1, Clk2, Clk3, Clk4, Clk5 transfer to serializer 3 after driver 13 strengthens driving forces.
As shown in Figure 6, serializer 3 comprises 5 fetch bit logical circuit a, b, c, d, e and combinator circuit 32, fetch bit logical circuit a, b, c, d, e do corresponding fetch bit to each bit in the parallel data signal, and export corresponding data-signal to combinator circuit 32, after combinator circuit 32 receives the output signal of all fetch bit logical circuits 31, the output serial data signal.
In the present invention, fetch bit logical circuit 31 comprises a logic NOT U31A and two logical AND U31B, U31C, and combinator circuit 32 adopts logic OR U32A.
As shown in Figure 6, logical AND U31B input signal is: the phase clock signal of this bit and the inversion signal of corresponding next phase clock signal, wherein, described next phase clock signal exports logical AND U31B to through logic NOT U31A.
As shown in Figure 6, logical AND U31C input signal is: the output signal of data-signal of this bit and logical AND U31B.
As shown in Figure 6, the output of the logical AND U31C among 5 fetch bit logical circuit a, b, c, d, the e is connected to each input of logic OR U32A respectively.
Specifically, as shown in Figure 6, in the present embodiment:
In fetch bit logical circuit a, logical AND U31B receive clock signal Clk1, logic NOT U31A receive clock signal Clk2, logic NOT U31A output connects the input of logical AND U31B, logical AND U31B output connects logical AND U31C input, and logical AND U31C receives data-signal Data_in[0].
In fetch bit logical circuit b, logical AND U31B receive clock signal Clk2, logic NOT U31A receive clock signal Clk3, logic NOT U31A output connects the input of logical AND U31B, logical AND U31B output connects logical AND U31C input, and logical AND U31C receives data-signal Data_in[1].
In fetch bit logical circuit c, logical AND U31B receive clock signal Clk3, logic NOT U31A receive clock signal Clk4, logic NOT U31A output connects the input of logical AND U31B, logical AND U31B output connects logical AND U31C input, and logical AND U31C receives data-signal Data_in[2].
In fetch bit logical circuit d, logical AND U31B receive clock signal Clk4, logic NOT U31A receive clock signal Clk5, logic NOT U31A output connects the input of logical AND U31B, logical AND U31B output connects logical AND U31C input, and logical AND U31C receives data-signal Data_in[3].
In fetch bit logical circuit e, logical AND U31B receive clock signal Clk5, logic NOT U31A receive clock signal Clk1, logic NOT U31A output connects the input of logical AND U31B, logical AND U31B output connects logical AND U31C input, and logical AND U31C receives data-signal Data_in[4].
As shown in Figure 7, data-signal Data_in[4:0] just by data shift being gone out, produce dateout data_out with 5 phase clock signal Clk1, Clk2, Clk3, Clk4, Clk5, its detailed process is:
Work as Clk1=1, send B0 data (Data_in[0]) during Clk2=0;
Work as Clk2=1, send B1 data (Data_in[1]) during Clk3=0;
Work as Clk3=1, send B2 data (Data_in[2]) during Clk4=0;
Work as Clk4=1, send B3 data (Data_in[3]) during Clk5=0;
Work as Clk5=1, send B4 data (Data_in[4]) during Clk1=0.
Like this, the present invention has just finished the stringization of data-signal.
Claims (9)
1, a kind of high speed and string data converting system comprise high-speed phase-locked loop, also comprise than bit pad and serializer,
Wherein:
Describedly the seniority top digit parallel data signal of input is handled with frequency doubling clock, produced the parallel data output signal of lower-order digit than bit pad;
Serializer receives the parallel data signal of exporting than bit pad, and serializer produces the serial output data signal according to the clock signal that high-speed phase-locked loop produced;
Described serializer comprises a plurality of fetch bit logical circuits and combinator circuit, described fetch bit logical circuit is done corresponding fetch bit to each bit in the parallel data signal, and export corresponding data-signal to the combinator circuit, after described combinator circuit receives the output signal of all fetch bit logical circuits, the output serial data signal.
2, high speed according to claim 1 and string data converting system, it is characterized in that: described high-speed phase-locked loop comprises control-signals generator and voltage controlled oscillator, described control-signals generator is according to the different clocks input signal, produce the phase difference signal, the current controling signal that obtains being correlated with; Described voltage controlled oscillator is according to the clock of N same frequency out of phase of current controling signal generation, and the phase difference of wherein adjacent two clocks is 360/N °, and the phase difference of N clock and first clock also is 360/N °.
3, high speed according to claim 2 and string data converting system, it is characterized in that: described control-signals generator receives two different clocks input signals, the clock signal of described voltage controlled oscillator output feeds back to control-signals generator as a clock input signal, and another clock input signal is relative external timing signal.
4, high speed according to claim 3 and string data converting system, it is characterized in that: described voltage controlled oscillator also connects driver, and described driver increases driving force to the clock signal of voltage controlled oscillator.
5, according to claim 3 or 4 described high speeds and string data converting system, it is characterized in that: described control-signals generator comprises 1/2 frequency divider, 1/N frequency divider, phase demodulation/frequency device, charge pump, low pass filter and voltage-current converter, wherein,
Described 1/2 frequency divider and 1/N output signal of frequency divider are sent to phase demodulation/frequency device, and described 1/2 frequency divider receives external timing signal; Described 1/N frequency divider receives the clock signal of voltage controlled oscillator or driver feedback;
Described phase demodulation/frequency device, charge pump link to each other successively with voltage-current converter, and low pass filter is connected between charge pump and the voltage-current converter;
Described phase demodulation/frequency device produces the phase difference signal of two input clocks;
Described charge pump produces current pulse signal according to the phase difference signal that receives, and low pass filter carries out integration to the current pulse signal that charge pump produces, and produces voltage control signal;
Described voltage-current converter is converted to current controling signal with the voltage control signal of input, with the operation of control voltage controlled oscillator.
6, according to claim 2 or 3 or 4 described high speeds and string data converting system, it is characterized in that: described voltage controlled oscillator comprises frequency controller, and the ring oscillator that is connected in turn by a plurality of delay unit input/output terminals, described frequency controller receives the current controling signal that control-signals generator produced, and the output frequency control signal is as the control signal of each delay unit in the ring oscillator.
7, high speed according to claim 6 and string data converting system is characterized in that: each delay unit in the described ring oscillator has one group of differential clocks input, and the differential clock signal of the time-delay of output process simultaneously is to next corresponding delay unit.
8, high speed according to claim 1 and string data converting system, it is characterized in that: described fetch bit logical circuit comprises a logic NOT (U31A) and two logical ANDs (U31B), (U31C), wherein, logical AND (U31B) input signal is: the phase clock signal of this bit, inversion signal with corresponding next phase clock signal, wherein, described next phase clock signal exports logical AND (U31B) to through logic NOT (U31A);
Logical AND (U31C) input signal is: the data-signal of this bit, and the output signal of logical AND (U31B).
9, high speed according to claim 1 and string data converting system is characterized in that: described combinator circuit is logic OR (U32A).
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| CNB2005100221753A CN100546361C (en) | 2005-11-25 | 2005-11-25 | A kind of high speed and string data converting system |
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| CNB2005100221753A CN100546361C (en) | 2005-11-25 | 2005-11-25 | A kind of high speed and string data converting system |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615912B (en) * | 2008-06-26 | 2011-10-26 | 中兴通讯股份有限公司 | Parallel-to-serial converter and realizing method thereof |
| CN103684445B (en) * | 2012-09-11 | 2016-08-17 | 成都锐成芯微科技有限责任公司 | Multiphase high-resolution phaselocked loop |
| KR101543704B1 (en) * | 2014-12-10 | 2015-08-12 | 연세대학교 산학협력단 | Serializer and data transmitter comprising the same |
| CN109547005B (en) * | 2018-11-15 | 2023-05-12 | 北京兆芯电子科技有限公司 | Conversion circuit |
| CN111049523A (en) * | 2019-12-26 | 2020-04-21 | 苏州普源精电科技有限公司 | Parallel-serial conversion unit, parallel-serial converter and time-interleaved ADC integrated circuit |
| KR20210145351A (en) * | 2020-05-25 | 2021-12-02 | 에스케이하이닉스 주식회사 | Transmitter for transmitting multi-bit data |
| CN116414079A (en) * | 2023-04-06 | 2023-07-11 | 东莞市新佰人机器人科技有限责任公司 | High-speed IO port remote mapping system based on PLC |
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| US5726651A (en) * | 1994-11-30 | 1998-03-10 | Sgs-Thomson Microelectronics S.A. | Device for serializing high flow of binary data |
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| US5726651A (en) * | 1994-11-30 | 1998-03-10 | Sgs-Thomson Microelectronics S.A. | Device for serializing high flow of binary data |
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