CN107911112A - A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology - Google Patents
A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology Download PDFInfo
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- CN107911112A CN107911112A CN201711126399.8A CN201711126399A CN107911112A CN 107911112 A CN107911112 A CN 107911112A CN 201711126399 A CN201711126399 A CN 201711126399A CN 107911112 A CN107911112 A CN 107911112A
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- charge pump
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- phaselocked loop
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
The invention discloses a kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology, by increasing the calibration circuit being made of time amplifier (TA), time voltage converter (TVC) and analog-digital converter (ADC), charge pump output current matching properties are made to be greatly improved, so that charge pump type phaselocked loop circuit high degree reduces output signal reference spur, so that the interference of the adjacent channel of wireless communication transceiver system greatly weakens, it can meet the communication system of high performance demands.
Description
Technical field
The present invention relates to technical field of radio frequency integrated circuits, more particularly to a kind of low ginseng of electrically charged pump correcting current technology
Examine spuious charge pump type phaselocked loop circuit.
Background technology
With the development of integrated circuit, also increasingly become on producing the research of phaselocked loop of clock signal or local oscillation signal
In maturation, wherein the pll output signal as local oscillation signal especially pays close attention to its reference spur performance, because wireless communication system
When the reference spur of the local oscillation signal of modulating/demodulating process is larger in system, crosstalk can be produced in adjacent channel, reduce communication system
Signal-to-noise ratio and communication quality, limit further increasing for communication system frequency.In other words, with to communication system quality and performance
More and more harsh requirement, can meet that the phaselocked loop of the low reference spur of system requirements also becomes and capture and Research Challenges.
So far, for the research of charge pump type phaselocked loop (Charge Pump Phase-Locked Loop, PLL)
Mainly focusing on reduces area occupied, phase noise, reduced consumption and reference spur, the wherein reduction of reference spur in recent years
Research hotspot, it has been suggested that be directed to reduce reference spur method mostly be improve charge pump (Charge Pump, CP) circuit
Structure is to improve its current matching attribute, so as to reduce voltage controlled oscillator (Voltage-Controlled Oscillator, VCO)
Voltage ripple on voltage-controlled curve, to achieve the purpose that to reduce reference spur.But the dynamic current matching of CP is hardly possible
Accomplish to match completely, therefore such method there can only be the less improvement of degree for reference spur performance.
Traditional charge pump type phaselocked loop circuit structure as shown in Figure 1, including：Phase frequency detector (Phase Frequency
Detector, PFD), charge pump (Charge Pump, CP), loop filter (Loop Filter, LP), voltage controlled oscillator
(VCO), frequency divider (Divider).Wherein, the spuious main source of traditional CPPLL circuit references is the non-thread of PFD and CP circuits
Property and the non-ideal characteristic such as current mismatch cause have voltage ripple on the voltage-controlled curves of VCO, and this ripple cycle refers to input
Signal period is identical, so as to be to have protrusion frequency at off-center frequency reference signal frequency cashing output signal spectrum
Spectrum.It is now assumed that ripple Vripple is approximately cosine wave：
Vripple(t)=Vmcos nωreft (1)
In formula (1), n=1,2,3 ....VmFor ripple amplitude, ωrefFor reference signal angular frequency.Then voltage controlled oscillator
Export and be：
Vout(t)=V0cos(ω0t+Kvco∫Vc(t)dt) (2)
Formula (2) be unfolded the output voltage of actual phaselocked loop is：
In formula (2) (3), n=1,2,3 ....V0For oscillator oscillator signal amplitude, ωrefFor reference signal angular frequency, ω0
For oscillator signal angular frequency, VmFor ripple amplitude, KVCOFor oscillator gain coefficient.From formula (3), the amplitude of reference spur
Increase with the increase of ripple amplitude on voltage controlled oscillator.
The content of the invention
, can be effective the object of the present invention is to provide a kind of charge pump type phaselocked loop circuit of low reference spur quick lock in
Reduction reference spur.
The purpose of the present invention is what is be achieved through the following technical solutions：A kind of low reference of electrically charged pump correcting current technology
Spuious charge pump type phaselocked loop circuit, including phase frequency detector (PFD), loop filter (LF), calibration circuit, charge pump
(CP), voltage controlled oscillator (VCO), frequency divider (Divider), lock detector (LD)；Its connection relation is as follows：
Sequentially connected phase frequency detector, charge pump, calibration circuit, loop filter, voltage controlled oscillator and frequency divider, school
Quasi- circuit input end is connected with phase frequency detector output terminal, and calibration circuit output signal is connected with the digital control position of charge pump；
The fraction frequency device input end is connected with voltage controlled oscillator output, and the frequency divider output terminal is connected with phase frequency detector Single port,
The phase frequency detector another port is connected with input reference signal, and the lock detecting circuit output terminal is enabled with calibration circuit
Control terminal is connected.
Wherein, the calibration circuit turns including sequentially connected time amplifier, time voltage converter and simulation numeral
Parallel operation.
Wherein, the time amplifier is symmetrical, half of circuit bag operational amplifier, switch S1、S2, current source I1,1,
I1,1, capacitance C1It is as follows with input IN1 controlling switches, connection relation：Operational amplifier cathode connects fixed reference potential, anode
With capacitance cathode, switch S1、S2It is connected and is connected with input IN1 controlling switches, output terminal is output signal end；Capacitance anode
It is connected to the ground, current source I1,1, I1,1Anode is connected to the ground, cathode and switch S1、S2It is connected.
As seen from the above technical solution provided by the invention, by introducing time amplifier between PFD and CP
(Time Amplifier, TA), time voltage converter (Time to Voltage Converter, TVC) and simulation numeral turn
The current calibration circuit that parallel operation (Analog to Digital Converter, ADC) is formed, to detect arteries and veins between UP and DN signals
It is wide poor, and pulse width difference is converted into digital signal with for adjusting the I of charge pumpUPAnd IDNSize to improve its currents match
Characteristic, so that loop output signal reference spur performance obtains the optimization of big degree so that wireless communication transceiver system
The interference of adjacent channel greatly weakens.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, without creative efforts, other can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is the charge pump type phaselocked loop basic structure and non-ideal characteristic schematic diagram that background of invention provides；
Fig. 2 is a kind of charge-pump type of the low reference spur of electrically charged pump correcting current technology provided in an embodiment of the present invention
Phase-locked loop circuit structure diagram；
Fig. 3 is time amplifier circuit diagram provided in an embodiment of the present invention；
Fig. 4 is time voltage converter circuit schematic diagram provided in an embodiment of the present invention；
Fig. 5 is the charge pump transistor level circuit diagram of the digital control position of band provided in an embodiment of the present invention.
Embodiment
With reference to the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, the every other implementation that those of ordinary skill in the art are obtained without making creative work
Example, belongs to protection scope of the present invention.
Fig. 2 is a kind of charge-pump type of the low reference spur of electrically charged pump correcting current technology provided in an embodiment of the present invention
Phase-locked loop circuit, as shown in Fig. 2, it mainly includes：Phase frequency detector (PFD), loop filter (LF), calibration circuit, electric charge
Pump (CP), voltage controlled oscillator (VCO), frequency divider (Divider), lock detector (LD).Its connection relation is：It is sequentially connected
Phase frequency detector, charge pump, loop filter (LF), voltage controlled oscillator and frequency divider, calibration circuit input end and PFD output terminals
It is connected, calibration circuit output signal is connected with the digital control positions of CP.The Divider input terminals are connected with VCO outputs, described
Divider output terminals are connected with PFD Single ports, and the PFD another port is connected with input reference signal, the LD output terminals with
Calibration circuit enables control terminal and is connected.
The calibration circuit includes sequentially connected time amplifier TA, time voltage converter TVC and simulation numeral
Converter ADC.
As shown in figure 3, it is the time amplifier circuit.The time amplifier is symmetrical, half of circuit Bao Yun
Calculate amplifier, switch S1、S2, current source I1,1, I1,1, capacitance C1With input IN1 controlling switches.Connection relation is as follows：Operation amplifier
Device cathode connects fixed reference potential, anode and capacitance cathode, switch S1、S2It is connected and is connected with input IN1 controlling switches,
Output terminal is output signal end；Capacitance anode is connected to the ground, current source I1,1, I1,1Anode is connected to the ground, cathode and switch S1、S2
It is connected.
As shown in figure 4, for the calibration circuit 1 and calibrate the time voltage converter TVC1 and TVC2 that are used in circuit 2
Transistor level circuitry.The time voltage converter TVC1 includes transistor NM1, NM2, PM1 and capacitance C1.TVC2 includes crystal
Pipe NM3, NM4, PM2 and capacitance C2.Connection relation is：NM1 source electrodes are grounded and drain electrode is connected with NM2 source electrodes, the connection of PM1 source electrodes
To VDD, drain electrode is connected with NM2 drain electrodes and is connected with capacitance cathode and output terminal, and capacitance anode is connected to the ground, the connection of NM1 grids
To VDD, NM2 grids are connected to DN signals, and PM1 grids are connected to the locking signal of LD outputs.NM4 source electrodes be grounded and drain electrode with
NM3 source electrodes are connected, and PM2 source electrodes are connected to VDD and drain electrode is connected with NM3 drain electrodes and is connected with capacitance cathode and output terminal, electricity
Hold anode to be connected to the ground, NM3 grids are connected to VDD, and NM4 grids are connected to DN signals, and PM2 grids are connected to the locking of LD outputs
Signal.
As shown in figure 5, the charge pump circuit for the 3 bit digital control bit of band.Wherein, transistor MN1-MN6And PM1-
PM4Realize current mirror function；MNC1-MNC3And MPC1-MNC3For digital control position, to adjust IUPAnd IDNSize improve electric current
Matching.MN10, MN11, MP9, MP10By bias current mirror image to electric charge pump main MN12And MP7。
When the charge pump type phaselocked loop loop is introduced into lock-out state, LD circuit outputs are 0, and calibration circuit does not work,
That is CPPLL will not carry out CP correcting current behaviors in common locking process, when CPPLL loops reach lock-out state, LD circuits
It is 1 to export signal, and calibration circuit triggering enters working status.Current mismatch and PFD delay mismatch due to CP etc. is non-ideal
UP signals caused by factor are differed with DN signal pulsewidths, and pulse width difference is amplified can differentiate pulsewidth precision by TA, and will be put
Signal after big is converted to magnitude of voltage corresponding with pulsewidth by TVC, which is converted to 3 position digital signals and be used in combination by ADC
In the currents match characteristic of adjusting and optimizing CP.For example, if UP pulsewidths are more than DN pulsewidths, namely IUP<IDNWhen, ADC output signal meeting
Make the I of CPDNIncrease to improve IUPAnd IDNMatching, situation is then opposite when UP pulsewidths are less than DN pulsewidths.CP and PFD unreasonablys
Think that UP caused by sexual factor and DN pulsewidths mismatch will be obtained big degree by collimation technique proposed by the present invention and reduced, so as to have
The reference spur for reducing loop output signal of effect.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art is in the technical scope of present disclosure, the change or replacement that can readily occur in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Subject to enclosing.
Claims (3)
- A kind of 1. low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology, it is characterised in that：Including Phase frequency detector, loop filter, calibration circuit, charge pump, voltage controlled oscillator, frequency divider, lock detector；Its connection relation It is as follows：Sequentially connected phase frequency detector, charge pump, calibration circuit, loop filter, voltage controlled oscillator and frequency divider, calibration electricity Road input terminal is connected with phase frequency detector output terminal, and calibration circuit output signal is connected with the digital control position of charge pump；It is described Fraction frequency device input end is connected with voltage controlled oscillator output, and the frequency divider output terminal is connected with phase frequency detector Single port, described Phase frequency detector another port is connected with input reference signal, and the lock detecting circuit output terminal enables control with calibration circuit End is connected.
- A kind of 2. low reference spur charge pump type phaselocked loop electricity of electrically charged pump correcting current technology according to claim 1 Road, it is characterised in that：The calibration circuit turns including sequentially connected time amplifier, time voltage converter and simulation numeral Parallel operation.
- A kind of 3. low reference spur charge pump type phaselocked loop electricity of electrically charged pump correcting current technology according to claim 2 Road, it is characterised in that：The time amplifier is symmetrical, half of circuit bag operational amplifier, switch S1、S2, current source I1,1, I1,1, capacitance C1It is as follows with input IN1 controlling switches, connection relation：Operational amplifier cathode connects fixed reference potential, anode With capacitance cathode, switch S1、S2It is connected and is connected with input IN1 controlling switches, output terminal is output signal end；Capacitance anode It is connected to the ground, current source I1,1, I1,1Anode is connected to the ground, cathode and switch S1、S2It is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711126399.8A CN107911112A (en) | 2017-11-15 | 2017-11-15 | A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711126399.8A CN107911112A (en) | 2017-11-15 | 2017-11-15 | A kind of low reference spur charge pump type phaselocked loop circuit of electrically charged pump correcting current technology |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736834A (en) * | 2018-05-23 | 2018-11-02 | 中国电子科技集团公司第二十四研究所 | A kind of high linearity time amplifier that charged inhibits |
| CN113726332A (en) * | 2021-08-18 | 2021-11-30 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, phase-locked loop circuit reference spurious elimination device and phase-locked loop system |
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|---|---|---|---|---|
| US6496554B1 (en) * | 1998-04-20 | 2002-12-17 | Samsung Electronics Co., Ltd. | Phase lock detection circuit for phase-locked loop circuit |
| CN101542907A (en) * | 2006-11-30 | 2009-09-23 | 高通股份有限公司 | Linear phase frequency detector and charge pump for phase-locked loop |
| CN101944909A (en) * | 2009-07-10 | 2011-01-12 | 智迈微电子科技(上海)有限公司 | Phase frequency detector and charge pump circuit for phase locked loop |
| CN103391101A (en) * | 2013-07-29 | 2013-11-13 | 江苏物联网研究发展中心 | Mono-pulse time-domain amplifier based on charge-discharge structure |
| CN103401519A (en) * | 2013-07-29 | 2013-11-20 | 江苏物联网研究发展中心 | Charge and discharge comparing unit-based time domain amplifier |
| CN105306048A (en) * | 2015-11-11 | 2016-02-03 | 成都振芯科技股份有限公司 | Phase-locked loop circuit used for spurious suppression and spurious suppression method thereof |
-
2017
- 2017-11-15 CN CN201711126399.8A patent/CN107911112A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6496554B1 (en) * | 1998-04-20 | 2002-12-17 | Samsung Electronics Co., Ltd. | Phase lock detection circuit for phase-locked loop circuit |
| CN101542907A (en) * | 2006-11-30 | 2009-09-23 | 高通股份有限公司 | Linear phase frequency detector and charge pump for phase-locked loop |
| CN101944909A (en) * | 2009-07-10 | 2011-01-12 | 智迈微电子科技(上海)有限公司 | Phase frequency detector and charge pump circuit for phase locked loop |
| CN103391101A (en) * | 2013-07-29 | 2013-11-13 | 江苏物联网研究发展中心 | Mono-pulse time-domain amplifier based on charge-discharge structure |
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| CN105306048A (en) * | 2015-11-11 | 2016-02-03 | 成都振芯科技股份有限公司 | Phase-locked loop circuit used for spurious suppression and spurious suppression method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736834A (en) * | 2018-05-23 | 2018-11-02 | 中国电子科技集团公司第二十四研究所 | A kind of high linearity time amplifier that charged inhibits |
| CN113726332A (en) * | 2021-08-18 | 2021-11-30 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, phase-locked loop circuit reference spurious elimination device and phase-locked loop system |
| CN113726332B (en) * | 2021-08-18 | 2023-07-07 | 上海聆芯科技有限公司 | Phase-locked loop circuit reference spurious elimination method, elimination device and phase-locked loop system |
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