CN103346874B - Digital communication clock synchronization system based on DDS - Google Patents
Digital communication clock synchronization system based on DDS Download PDFInfo
- Publication number
- CN103346874B CN103346874B CN201310246147.4A CN201310246147A CN103346874B CN 103346874 B CN103346874 B CN 103346874B CN 201310246147 A CN201310246147 A CN 201310246147A CN 103346874 B CN103346874 B CN 103346874B
- Authority
- CN
- China
- Prior art keywords
- module
- control word
- frequency control
- frequency
- dds
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a digital communication clock synchronization system based on a DDS. The digital communication clock synchronization system based on the DDS comprises a waveform preprocessor, a phase discriminator, a prefilter, a system data processing module and a DDS waveform generating module. The waveform preprocessor is connected with one input end of the phase discriminator, the output end of the phase discriminator is connected with the input end of the prefilter, the output end of the prefilter is connected with the input end of the system data processing module, the output end of the system data processing module is connected with the frequency control word input end of the DDS waveform generating module, the output end of the DDS waveform generating module is connected with the other input end of the phase discriminator, and meanwhile synchronous clock signals are output. The digital communication clock synchronization system controls the output of the DDS through a control algorithm with a highest frequency and a lowest threshold value, the DDS characteristics of being wide in covered frequency range, flexible in output frequency control and high in resolution ratio are fully utilized, and the digital communication clock synchronization system is not provided with an adjustable element, is low in debugging difficulty, enables working frequency to be easily set, and is suitable for multi-rate work.
Description
Technical field
The present invention relates to the Clock Synchronization Technology field in data transmission system, and in particular to a kind of numeral based on DDS
Communication clock synchronization system.
Background technology
Current communication networks just develop towards many systems, multimodal direction, for the communication system of compatible many systems, its
The rate of information throughput is varied, and receiving terminal realizes that the clock system of clock recovery will adapt to diversified speed.
In current communication networks Clock Synchronization Technology mainly have Clock Synchronization Technology using analog phase-locked look, using plus button pulse, become
The all-digital phase-locked loop Clock Synchronization Technology that the methods such as mould frequency dividing are realized, these technologies will be realized under various communications speed
Clock synchronously has corresponding difficulty.
Analog phase-locked look（PLL）Clock synchronous extraction circuit uses voltage controlled oscillator (VCO), Fig. 1 to be PLL circuit realization
The theory diagram that clock is synchronously extracted.The frequency and phase place change of phase-locked loop control VCO, make the clock that VCO is exported with to connecing
Receive the chip rate synchronization of data.But the centre frequency of VCO, frequency range are affected very big by component parameters, by temperature, humidity
Also larger etc. the impact of environmental factor, debugging difficulty is larger.VCO also more difficult frequency coverages for accomplishing wide scope, analog phase-locked look
Clock synchronization circuit is difficult in adapt to the synchronous task of various transfer rate clocks.
All-digital phase-locked loop clock synchronous extraction circuit uses digital controlled oscillator, when Fig. 2 is realized for all-digital phase-locked loop
The schematic diagram block diagram that clock is synchronously extracted.The conventional mode of digital controlled oscillator have high frequency clock add button pulsed digital controlled oscillator or
Person is that high frequency clock becomes mould frequency division type digital controlled oscillator.Phase discriminator obtain within each cycle the phase place of input signal with it is local
The advanced or delayed information of signal phase, is carried out plus button Pulse Width Control, or carries out becoming mould frequency dividing control, changes the clock of output
Phase state, makes local clock with the data syn-chronization for receiving.Divided due to using high frequency clock, to be produced various different frequencies
The high frequency clock of rate has certain complexity；Equally, the clock that clock synchronization circuit is exported is allowed to meet various transfer rates
Demand, to carry out fraction scale frequency dividing, neatly control divide ratio could realize, also have larger complexity in this approach
Degree.
The content of the invention
For the deficiencies in the prior art, the present invention provides one kind and utilizes Direct Digital Synthesizer（DDS）Module reality
The system of current clock synchronous phase-locked loop.Using DDS as controllable frequency source, and by with frequency highest, minimum threshold
Control algolithm makes full use of DDS covering frequence wide ranges controlling the output of DDS, and output frequency control is flexible, high resolution
Characteristic, realize without adjustable element, debugging difficulty it is low, operating frequency is set easily, be suitable to the digital communication of multi tate work
Clock system.
The present invention is achieved through the following technical solutions：
A kind of digital communication clock system based on DDS, including waveform preprocessor, phase discriminator, DDS waveforms are produced
Module；Waveform preprocessor output end connects an input of phase discriminator, phase detector output connection DDS waveform generation modules
Frequency control word input, DDS waveform generation modules output end connects another input of phase discriminator, while exporting synchronous
Clock signal.
To be conducive to data processing, the grafting prefilter between phase discriminator and the DDS waveform generation modules；Phase discriminator
Output end connects the input of prefilter, and prefilter output end connects the frequency control word of DDS waveform generation modules
Input.
In order to obtain superior technique effect, between prefilter output end and DDS waveform generation module inputs
Grafting system data processing module；The input of prefilter output end connection system data processing module, system data
Processing module output end connects the frequency control word input of DDS waveform generation modules.
The system data processing module includes value module, difference calculating module, loop filtering module, frequency adjustment
Computing module, frequency control word computing module, frequency transfinite judging module and frequency control word setup module, above-mentioned each module according to
It is linked in sequence.The data handling procedure of data processing module comprises the steps：
（1）The frequency that DDS initialization modules is connected to transfinites judge module, frequency control word setup module, transfinites to frequency
Judge module sends into highest, the minimum threshold of predetermined frequency control word, sends into frequency to frequency control word setup module initial
ValueCorresponding frequency control word；
（2）By value module obtain prefilter voltage output value, by its with numerical benchmark in difference calculating module
Carry out difference operation；Numerical benchmark therein is highest, the arithmetic mean of instantaneous value of minimum voltage value of prefilter output；
（3）Difference data sends into loop filtering module and is integrated computing, and its operation result is sent into frequency adjustment and calculated
Module；
（4）Result data is multiplied by voltage-controlled coefficient by frequency adjustment computing module, it is calculated DDS output signal frequencies
The variable of needs, frequency control word computing module of then making a gift to someone；
（5）Frequency control word computing module carries out the calculating of frequency control word, and the frequency control word exported after calculating is sent into
The frequency judging module that transfinites carries out the judgement of high-low threshold；
（6）When frequency control word is not above preset highest, minimum threshold, frequency transfinites judging module will input
Frequency control word is directly sent to frequency control word setup module, and the output signal frequency of DDS waveform generators is adjusted；
（7）When frequency control word has exceeded preset highest, minimum threshold, frequency control word is only taken accordingly most
High, minimum threshold, removes beyond part, and output is to frequency control word setup module, the output letter to DDS waveform generators
Number frequency is adjusted.
Wherein, step（5）Described in the computational methods of frequency control word computing module can be from one of following two：
（1）；
（2）。
Description of the drawings
Fig. 1 is that analog phase-locked look bit synchronization extracts circuit structure block diagram.
Fig. 2 is that digital phase-locked loop bit synchronization extracts circuit structure block diagram.
Fig. 3 is based on the digital communication clock system circuit structure block diagram of DDS.
Fig. 4 is the system data processing module FB(flow block) in Fig. 3.
Fig. 5 is that the digital communication clock system circuit structure block diagram based on DDS for controlling is made of single-chip microcomputer.
Fig. 6 is the single-chip data process flow block diagram in Fig. 5.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is described in further detail.
Embodiment 1：
With reference to Fig. 3, baseband signal is input to signal pre-processing module, and signal pre-processing module carries out the shaping of signal, non-
Linear transformation process, shaping, process after signal input to phase discriminator an input, phase discriminator compare input shaping,
Baseband signal after process and feed back phase differential of the signal between both, phase discriminator from DDS waveform generation modules
Output signal size correspond to the two input signal phase differences.The effect of prefilter is by phase detector output signal
High fdrequency component filter, the data processing after being conducive to.The signal of prefilter output is through data processing module process
Afterwards, the frequency control word for generating DDS is controlled to DDS waveform generation modules, and the output signal of DDS waveform generators is again anti-
Another input of phase discriminator is fed to, the feedback control of closed loop is realized, DDS waveform generation module output signals are constantly adjusted
Frequency so that the frequency and phase place of output signal is synchronous with the baseband signal of input, recovers synchronous clock signal and exports.
DDS initial values can be arranged by external connection keyboard or I/O devices, and predetermined frequency control word highest,
Minimum threshold（And highest, minimum threshold are decided by DDS module parameter）So that system can very easily work
In different communication data rates, the clock synchronous task under various transfer rates is completed.
Fig. 4 is the block diagram of system data processing module.The frequency that initialization module is connected to transfinites judge module, FREQUENCY CONTROL
Word setup module, highest, the minimum threshold of the judge module feeding predetermined frequency control word that transfinites to frequency, to frequency control word
Setup module sends into frequency initial value, make DDS module output frequency identical with the nominal value of system data transfer rate.Initially
System enters normal mode of operation after change.The output valve of prefilter is obtained by value module, and is input to mathematic interpolation mould
Block, difference calculating module subtracts each other the output valve of prefilter and numerical benchmark, obtains their difference.Difference calculating module
Output signal send into loop filtering module, be integrated computing.Loop filter exports the signal through Integral Processing, this letter
Number it is re-fed into frequency adjustment computing module.Input signal is multiplied by voltage-controlled COEFFICIENT K by frequency adjustment computing module, is calculated
The numerical value of change, voltage-controlled COEFFICIENT K is needed to be equivalent voltage controlled gain to DDS output signal frequencies.Frequency adjustment calculates mould
The output signal of block sends into frequency control word computing module, and from following calculating formulas the calculating of frequency control word is carried out：
。
The frequency control word of frequency control word computing module output sends into the frequency judging module that transfinites and carries out high-low threshold
Judgement, when frequency control word is not above preset highest, minimum threshold, frequency transfinites judging module will input frequency
Rate control word is directly sent to DDS frequency control word setup modules, and the output signal frequency of DDS waveform generators is adjusted,
When frequency control word has exceeded preset highest, minimum threshold, frequency control word is only taken corresponding highest, minimum threshold
Value, removes beyond part, and output is entered to DDS frequency control word setup modules to the output signal frequency of DDS waveform generators
Row adjustment.
Embodiment 2：
Fig. 5, Fig. 6 are the use of the single-chip microcomputer with analog-digital converter and do the digital communication clock synchronization based on DDS for controlling
Circuit system structured flowchart and data process flow block diagram.The system contrast realized with embodiment 1, its difference is loop filtering
Module circuit realiration, equally completes the function of integrating, and the input of phase detector output linkloop filtration module, ring
Road filtration module output end connects the analog-digital converter input of single-chip microcomputer, and the analog-digital converter completes to take as value module
Value.
The data handling procedure of single-chip microcomputer comprises the steps：
（1）The frequency that DDS initialization modules is connected to transfinites judge module, frequency control word setup module, transfinites to frequency
Judge module sends into highest, the minimum threshold of predetermined frequency control word, sends into frequency to frequency control word setup module initial
ValueCorresponding frequency control word；
（2）Analog-digital converter take out loop filtering module voltage output value, by its with numerical benchmark in mathematic interpolation mould
Carry out difference operation in block, its operation result is made a gift to someone frequency adjustment computing module；Numerical benchmark therein is loop filter
The highest of output, the arithmetic mean of instantaneous value of minimum voltage value；
（3）Result data is multiplied by voltage-controlled coefficient by frequency adjustment computing module, it is calculated DDS output signal frequencies
The variable of needs, frequency control word computing module of then making a gift to someone；
（4）Frequency control word computing module carries out the calculating of frequency control word, and calculating formula is：
,
The frequency control word exported after calculating sends into the frequency judging module that transfinites and carries out the judgement of high-low threshold；
（5）When frequency control word is not above preset highest, minimum threshold, frequency transfinites judging module will input
Frequency control word is directly sent to frequency control word setup module, and the output signal frequency of DDS waveform generators is adjusted；
（6）When frequency control word has exceeded preset highest, minimum threshold, frequency control word is only taken accordingly most
High, minimum threshold, removes beyond part, and output is to frequency control word setup module, the output letter to DDS waveform generators
Number frequency is adjusted.
Claims (4)
1. a kind of digital communication clock system based on DDS, including waveform preprocessor, phase discriminator, DDS waveforms produce mould
Block；Waveform preprocessor output end connects an input of phase discriminator, phase detector output connection DDS waveform generation modules
Frequency control word input, DDS waveform generation modules output end connects another input of phase discriminator, while when exporting synchronous
Clock signal；The grafting prefilter between phase discriminator and the DDS waveform generation modules, phase detector output connection pre-filtering
The input of device, prefilter output end connects the frequency control word input of DDS waveform generation modules；In prefilter
Grafting system data processing module, prefilter output end connection system data processing and DDS waveform generation modules between
The input of module, system data processing module output end connects the frequency control word input of DDS waveform generation modules；
It is characterized in that：Described system data processing module includes value module, difference calculating module, loop according to the order of connection
Filtration module, frequency adjustment computing module, frequency control word computing module, frequency transfinite judging module and frequency control word sets
Put module；The data handling procedure of system data processing module comprises the steps：
(1) DDS initialization modules are connected to frequency and transfinite judging module, frequency control word setup module, transfinite judgement to frequency
Module sends into highest, the minimum threshold of predetermined frequency control word, and to frequency control word setup module frequency initial value f is sent into0
Corresponding frequency control word；
(2) prefilter voltage output value is obtained by value module, it is carried out with numerical benchmark in difference calculating module
Difference operation；Numerical benchmark therein is highest, the arithmetic mean of instantaneous value of minimum voltage value of prefilter output；
(3) difference data sends into loop filtering module and is integrated computing, and its operation result sends into frequency adjustment computing module；
(4) result data is multiplied by voltage-controlled coefficient k by frequency adjustment computing module, is calculated DDS output signal frequency needs
Variable, be then fed into frequency control word computing module；
(5) frequency control word computing module carries out the calculating of frequency control word, and the frequency control word exported after calculating sends into frequency
The judging module that transfinites carries out the judgement of high-low threshold；
(6) when frequency control word is not above preset highest, minimum threshold, frequency transfinites judging module by incoming frequency
Control word is directly sent to frequency control word setup module, and the output signal frequency of DDS waveform generators is adjusted；
(7) when frequency control word has exceeded preset highest, minimum threshold, frequency control word is only taken corresponding highest,
Minimum threshold, removes beyond part, output to frequency control word setup module, the output signal frequency to DDS waveform generators
Rate is adjusted.
2. clock system according to claim 1, it is characterised in that the frequency control word described in step (5) is calculated
The computational methods of module are one of following two：
(1)
(2)
3. a kind of digital communication clock system based on DDS, including waveform preprocessor, phase discriminator, DDS waveforms produce mould
Block；Waveform preprocessor output end connects an input of phase discriminator, phase detector output connection DDS waveform generation modules
Frequency control word input, DDS waveform generation modules output end connects another input of phase discriminator, while when exporting synchronous
Clock signal；Grafting loop filtering module and the monolithic of analog-digital converter is carried between phase discriminator and DDS waveform generation modules
Machine；The input of phase detector output linkloop filtration module, the modulus of loop filtering module output end connection single-chip microcomputer turns
Parallel operation input, single-chip microcomputer output connects the frequency control word input of DDS waveform generation modules, it is characterised in that：It is described
The data handling procedure of single-chip microcomputer comprises the steps：
(1) DDS initialization modules are connected to frequency and transfinite judging module, frequency control word setup module, transfinite judgement to frequency
Module sends into highest, the minimum threshold of predetermined frequency control word, and to frequency control word setup module frequency initial value f is sent into0
Corresponding frequency control word；
(2) analog-digital converter takes out the voltage output value of loop filter, and it is entered with numerical benchmark in difference calculating module
Row difference operation, its operation result sends into frequency adjustment computing module；Numerical benchmark therein is loop filter output
The arithmetic mean of instantaneous value of highest, minimum voltage value；
(3) result data is multiplied by voltage-controlled coefficient k by frequency adjustment computing module, is calculated DDS output signal frequency needs
Variable, be then fed into frequency control word computing module；
(4) frequency control word computing module carries out the calculating of frequency control word, and the frequency control word exported after calculating sends into frequency
The judging module that transfinites carries out the judgement of high-low threshold；
(5) when frequency control word is not above preset highest, minimum threshold, frequency transfinites judging module by incoming frequency
Control word is directly sent to frequency control word setup module, and the output signal frequency of DDS waveform generators is adjusted；
(6) when frequency control word has exceeded preset highest, minimum threshold, frequency control word is only taken corresponding highest,
Minimum threshold, removes beyond part, output to frequency control word setup module, the output signal frequency to DDS waveform generators
Rate is adjusted.
4. clock system according to claim 3, it is characterised in that the frequency control word described in step (4) is calculated
The computational methods of module are one of following two：
(1)
(2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310246147.4A CN103346874B (en) | 2013-06-20 | 2013-06-20 | Digital communication clock synchronization system based on DDS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310246147.4A CN103346874B (en) | 2013-06-20 | 2013-06-20 | Digital communication clock synchronization system based on DDS |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103346874A CN103346874A (en) | 2013-10-09 |
| CN103346874B true CN103346874B (en) | 2017-04-19 |
Family
ID=49281650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310246147.4A Active CN103346874B (en) | 2013-06-20 | 2013-06-20 | Digital communication clock synchronization system based on DDS |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103346874B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811139B (en) * | 2015-04-20 | 2018-06-05 | 浙江科技学院 | Vector network analysis method based on the application of DDS spurious frequencies |
| CN106301658B (en) * | 2016-09-26 | 2018-11-09 | 湖南基石通信技术有限公司 | A kind of Extraction of Bit Synchronization Signal method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
| CN203340091U (en) * | 2013-06-20 | 2013-12-11 | 桂林电子科技大学 | DDS-based digital communication clock synchronization system |
-
2013
- 2013-06-20 CN CN201310246147.4A patent/CN103346874B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
| CN203340091U (en) * | 2013-06-20 | 2013-12-11 | 桂林电子科技大学 | DDS-based digital communication clock synchronization system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103346874A (en) | 2013-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103297041B (en) | Phase-locked loop circuit | |
| CN104539285B (en) | Data clock recovery circuit | |
| CN101170399B (en) | A clock synchronization method in distributed base station and the distributed base station | |
| CN103957007B (en) | Random waveform weak signal detection method and system under low signal to noise ratio | |
| CN100563222C (en) | A kind of method of clock and data recovery and circuit | |
| CN105680851A (en) | Clock data recovery system | |
| CN103427830B (en) | A kind of half-blindness type over-sampling clock data recovery circuit with high lock-in range | |
| CN104521175A (en) | Clock recovery, receiver, and communication system for multiple channels | |
| CN101420294B (en) | Time clock phase locking loop controlling method and apparatus | |
| CN103346874B (en) | Digital communication clock synchronization system based on DDS | |
| CN103414464A (en) | Half-speed clock data recovery circuit based on phase selection interpolation type | |
| CN109314520A (en) | Method and circuit for phaselocked loop | |
| CN203340091U (en) | DDS-based digital communication clock synchronization system | |
| CN1770633B (en) | Clock phase-locked loop and clock phase-locking control method | |
| CN211606514U (en) | High-speed serial clock data recovery circuit | |
| CN109714046B (en) | All-digital phase-locked loop with variable phase accumulator circuit structure and phase-locked control method | |
| CN207150565U (en) | A kind of high speed delay phase-locked loop | |
| CN101114179A (en) | Phase adjusting method and device thereof | |
| CN104065360B (en) | The nearly sinusoidal carrier generator that a kind of wide temperature is applied and frequency stable is controlled | |
| CN104410409B (en) | A kind of adaptive multi-clock generation device and method | |
| CN103825611B (en) | Deaccentuator and method | |
| CN207884576U (en) | A kind of digital frequency multiplier | |
| CN205407759U (en) | Clock duty cycle adjusting device | |
| CN106716292A (en) | Generation of high-rate sinusoidal sequences | |
| WO2022077987A1 (en) | Clock synchronization circuit, control method, printed circuit board and communication device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |