CN103346874A - Digital communication clock synchronization system based on DDS - Google Patents

Abstract

The invention discloses a DDS-based digital communication clock synchronization system, comprising a waveform preprocessor, a phase detector, a pre-filter, a system data processing module, and a DDS waveform generation module; the waveform preprocessor is connected to one of the phase detectors The input terminal, the output terminal of the phase detector is connected to the input terminal of the pre-filter, the output terminal of the pre-filter is connected to the input terminal of the system data processing module, the output terminal of the system data processing module is connected to the frequency control word input terminal of the DDS waveform generation module, The output end of the DDS waveform generation module is connected to the other input end of the phase detector, and simultaneously outputs a synchronous clock signal. The invention controls the output of DDS through the control algorithm with the highest frequency and the lowest threshold value, fully utilizes the characteristics of wide frequency range covered by DDS, flexible output frequency control, and high resolution, and realizes no adjustable components and low debugging difficulty , It is easy to set the working frequency, and it is suitable for digital communication clock synchronization system with multi-rate work.

Description

A Digital Communication Clock Synchronization System Based on DDS

technical field

The invention relates to the technical field of clock synchronization in a data transmission system, in particular to a digital communication clock synchronization system based on DDS.

Background technique

The current communication system is developing in the direction of multi-system and multi-mode. For a communication system compatible with multi-system, its information transmission rate is various, and the clock synchronization system for clock recovery at the receiving end must adapt to various rates. The clock synchronization technology in the current communication system mainly includes the clock synchronization technology using the analog phase-locked loop, the all-digital phase-locked loop clock synchronization technology realized by methods such as buckle pulse, variable mode frequency division, etc. There are corresponding difficulties in realizing clock synchronization under the circumstances.

The analog phase-locked loop (PLL) clock synchronization extraction circuit uses a voltage-controlled oscillator (VCO). Figure 1 is a functional block diagram of the PLL circuit for clock synchronization extraction. The phase-locked loop controls the frequency and phase changes of the VCO, so that the clock output by the VCO is synchronized with the symbol rate of the received data. However, the center frequency and frequency range of the VCO are greatly affected by component parameters, and are also greatly affected by environmental factors such as temperature and humidity, making debugging difficult. It is also difficult for the VCO to cover a wide range of frequencies, and the analog phase-locked loop clock synchronization circuit is difficult to adapt to the task of clock synchronization at various transmission rates.

The all-digital phase-locked loop clock synchronization extraction circuit uses a numerically controlled oscillator. Figure 2 is a schematic block diagram of an all-digital phase-locked loop for clock synchronization extraction. The commonly used methods of numerically controlled oscillators are high-frequency clock plus pulse type numerically controlled oscillators, or high-frequency clock variable mode frequency division type numerically controlled oscillators. The phase detector obtains the information that the phase of the input signal is ahead or behind the phase of the local signal in each cycle, and performs pulse addition control, or performs modulus frequency division control, changes the phase state of the output clock, and makes the local clock and the received data synchronization. Due to the use of high-frequency clocks for frequency division, it is complex to generate a variety of high-frequency clocks with different frequencies; similarly, to make the clock output by the clock synchronization circuit meet the needs of various transmission rates, fractional ratio frequency division is required , Flexible control of the frequency division coefficient can be realized, so this method also has greater complexity.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a system that utilizes a direct digital frequency synthesizer (DDS) module to realize a clock synchronous phase-locked loop. DDS is used as a controllable frequency source, and the output of DDS is controlled by a control algorithm with the highest frequency and the lowest threshold value, making full use of the characteristics of wide frequency coverage, flexible output frequency control, and high resolution of DDS to achieve no Adjustable components, low debugging difficulty, easy to set operating frequency, suitable for multi-rate digital communication clock synchronization system.

The present invention realizes through following technical scheme:

A digital communication clock synchronization system based on DDS, including a waveform preprocessor, a phase detector, and a DDS waveform generation module; the output terminal of the waveform preprocessor is connected to an input terminal of the phase detector, and the output terminal of the phase detector is connected to the DDS waveform generator The input terminal of the frequency control word of the module and the output terminal of the DDS waveform generation module are connected to the other input terminal of the phase detector, and a synchronous clock signal is output at the same time.

In order to facilitate data processing, a pre-filter is inserted between the phase detector and the DDS waveform generation module; the output of the phase detector is connected to the input of the pre-filter, and the output of the pre-filter is connected to the DDS waveform generation module The frequency control word input terminal.

In order to obtain a better technical effect, a system data processing module is inserted between the output end of the pre-filter and the input end of the DDS waveform generation module; the output end of the pre-filter is connected to the input end of the system data processing module, and the system data processing module The module output terminal is connected to the frequency control word input terminal of the DDS waveform generation module.

The system data processing module includes a value acquisition module, a difference calculation module, a loop filter module, a frequency adjustment calculation module, a frequency control word calculation module, a frequency overrun judgment module and a frequency control word setting module. The above-mentioned modules are in order connect. The data processing process of the data processing module includes the following steps:

对应的频率控制字； (1) The DDS initialization module is connected to the frequency overrun judgment module and the frequency control word setting module, and sends the highest and lowest threshold values of the preset frequency control word to the frequency overrun judgment module, and sends the frequency to the frequency control word setting module initial value

Corresponding frequency control word;

(2) Obtain the voltage output value of the pre-filter from the value-taking module, and perform difference calculation between it and the reference value in the difference calculation module; the reference value is the arithmetic of the highest and lowest voltage values output by the pre-filter average value;

(3) The difference data is sent to the loop filter module for integral calculation, and the calculation result is sent to the frequency adjustment calculation module;

，计算得到DDS输出信号频率需要的变量，然后送人频率控制字计算模块； (4) The frequency adjustment calculation module multiplies the result data by the voltage control coefficient

, calculate the variables required by the DDS output signal frequency, and then send it to the frequency control word calculation module;

(5) The frequency control word calculation module calculates the frequency control word, and the frequency control word output after calculation is sent to the frequency overrun judgment module for high and low threshold judgment;

(6) When the frequency control word does not exceed the preset maximum and minimum threshold values, the frequency overrun judgment module sends the input frequency control word directly to the frequency control word setting module to adjust the output signal frequency of the DDS waveform generator ;

(7) When the frequency control word exceeds the preset maximum and minimum threshold values, the frequency control word only takes the corresponding maximum and minimum threshold values, removes the excess part, and outputs it to the frequency control word setting module. The output signal frequency of the waveform generator is adjusted.

Among them, the calculation method of the frequency control word calculation module described in step (5) can choose one of the following two:

； (1)

;

。 (2)

.

Description of drawings

Figure 1 is a block diagram of the analog phase-locked loop bit synchronization extraction circuit.

Figure 2 is a block diagram of the digital phase-locked loop bit synchronization extraction circuit.

Figure 3 is a block diagram of the circuit structure of the digital communication clock synchronization system based on DDS.

FIG. 4 is a flow diagram of the system data processing module in FIG. 3 .

Figure 5 is a block diagram of the circuit structure of the DDS-based digital communication clock synchronization system controlled by a single-chip microcomputer.

FIG. 6 is a block diagram of the data processing flow of the single-chip microcomputer in FIG. 5 .

Detailed ways

Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.

Example 1:

Referring to Figure 3, the baseband signal is input to the signal preprocessing module, and the signal preprocessing module performs signal shaping and nonlinear transformation processing, and the shaping and processed signal is input to an input terminal of the phase detector, and the phase detector compares the input shaping 1. The phase difference between the processed baseband signal and the signal fed back from the DDS waveform generation module. The output signal of the phase detector corresponds to the phase difference between the two input signals. The function of the pre-filter is to filter out the high-frequency components in the output signal of the phase detector, which is beneficial to the subsequent data processing. After the signal output by the pre-filter is processed by the data processing module, the DDS frequency control word is generated to control the DDS waveform generation module, and the output signal of the DDS waveform generator is fed back to the other input terminal of the phase detector to realize the closed-loop Feedback control continuously adjusts the frequency of the output signal of the DDS waveform generation module, so that the frequency and phase of the output signal are synchronized with the input baseband signal, and a synchronized clock signal is recovered and output.

及最高、最低门限值均决定于DDS模块参数），使得系统能够非常方便的工作于不同的通信数据率，完成多种传输速率下的时钟同步任务。 DDS initial value can be set through an external keyboard or I/O device , and the highest and lowest thresholds of the preset frequency control word (

And the highest and lowest thresholds are determined by the DDS module parameters), which makes the system very convenient to work at different communication data rates, and complete clock synchronization tasks under various transmission rates.

Figure 4 is a block diagram of the system data processing module. The initialization module is connected to the frequency overrun judging module and the frequency control word setting module, and sends the highest and lowest threshold values of the preset frequency control word to the frequency overrun judging module, and sends the frequency initial value to the frequency control word setting module , so that the output frequency of the DDS module is the same as the nominal value of the system data transmission rate. After initialization, the system enters the normal working mode. The output value of the pre-filter is obtained by the value acquisition module, and is input to the difference calculation module, and the difference calculation module subtracts the output value of the pre-filter from the reference value to obtain their difference. The output signal of the difference calculation module is sent to the loop filter module for integral operation. The loop filter outputs the integrated signal, which is then sent to the frequency adjustment calculation module. The frequency adjustment calculation module multiplies the input signal by the voltage control coefficient K to calculate the value that the DDS output signal frequency needs to change, and the voltage control coefficient K is the equivalent voltage control gain. The output signal of the frequency adjustment calculation module is sent to the frequency control word calculation module, and the following calculation formula is used to calculate the frequency control word:

.

The frequency control word output by the frequency control word calculation module is sent to the frequency overrun judgment module to judge the high and low thresholds. When the frequency control word does not exceed the preset maximum and minimum thresholds, the frequency overrun judgment module will input the frequency control The word is directly sent to the DDS frequency control word setting module to adjust the output signal frequency of the DDS waveform generator. When the frequency control word exceeds the preset highest and lowest threshold values, the frequency control word only takes the corresponding highest and lowest Threshold value, remove the excess part, output to the DDS frequency control word setting module, and adjust the output signal frequency of the DDS waveform generator.

Example 2:

Figure 5 and Figure 6 are a block diagram of the circuit structure and a data processing flow diagram of a DDS-based digital communication clock synchronization system controlled by a single-chip microcomputer with an analog-to-digital converter. Compared with the system realized in embodiment 1, the difference is that the loop filter module is implemented with a circuit, which also completes the function of integration, and the output end of the phase detector is connected to the input end of the loop filter module, and the output end of the loop filter module is connected to the single chip microcomputer. The input terminal of the analog-to-digital converter, the analog-to-digital converter is used as a value acquisition module to complete the value acquisition.

The data processing process of the single-chip microcomputer includes the following steps:

(1) The DDS initialization module is connected to the frequency overrun judgment module and the frequency control word setting module, and sends the highest and lowest threshold values of the preset frequency control word to the frequency overrun judgment module, and sends the frequency to the frequency control word setting module initial value Corresponding frequency control word;

(2) The analog-to-digital converter takes out the voltage output value of the loop filter module, and performs difference calculation between it and the reference value in the difference calculation module, and the calculation result is sent to the frequency adjustment calculation module; the reference value is the loop The arithmetic mean of the highest and lowest voltage values output by the filter;

，计算得到DDS输出信号频率需要的变量，然后送人频率控制字计算模块； (3) The frequency adjustment amount calculation module multiplies the result data by the voltage control coefficient

, calculate the variables required by the DDS output signal frequency, and then send it to the frequency control word calculation module;

(4) The frequency control word calculation module calculates the frequency control word, and the calculation formula is:

，

,

The frequency control word output after calculation is sent to the frequency overrun judgment module to judge the high and low thresholds;

(5) When the frequency control word does not exceed the preset maximum and minimum thresholds, the frequency overrun judgment module sends the input frequency control word directly to the frequency control word setting module to adjust the output signal frequency of the DDS waveform generator ;

(6) When the frequency control word exceeds the preset maximum and minimum threshold values, the frequency control word only takes the corresponding maximum and minimum threshold values, removes the excess part, and outputs it to the frequency control word setting module. For DDS The output signal frequency of the waveform generator is adjusted.

Claims (8)

1. the digital communication clock system based on DDS comprises the waveform preprocessor, and phase discriminator is characterized in that: also comprise the DDS waveform generation module; Waveform preprocessor output connects an input of phase discriminator, and the phase discriminator output connects the frequency control word input of DDS waveform generation module, and DDS waveform generation module output connects another input of phase discriminator, exports synchronizing clock signals simultaneously.

2. clock system according to claim 1 is characterized in that: the prefilter of having pegged graft between phase discriminator and DDS waveform generation module; The phase discriminator output connects the input of prefilter, and the prefilter output connects the frequency control word input of DDS waveform generation module.

3. clock system according to claim 2 is characterized in that: the system data processing module of having pegged graft between prefilter and DDS waveform generation module; The input of prefilter output connected system data processing module, system data processing module output connects the frequency control word input of DDS waveform generation module.

4. clock system according to claim 3 is characterized in that described system data processing module comprises that according to the order of connection transfinite judging module and frequency control word of value module, difference calculating module, loop filtering module, frequency adjustment amount computing module, frequency control word computing module, frequency arranges module; The data handling procedure of system data processing module comprises the steps:

(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value

Corresponding frequency control word;

(2) obtain the prefilter voltage output value by the value module, itself and benchmark numerical value are carried out the difference computing in difference calculating module; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of prefilter output;

(3) difference data is sent into the loop filtering module and is carried out integral operation, and its operation result is sent into frequency adjustment amount computing module;

(4) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data

, calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;

(5) the frequency control word computing module carries out the calculating of frequency control word, and the frequency control word that calculates back output is sent into the frequency judging module that transfinites and carried out the judgement of high low threshold;

(6) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;

(7) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.

5. clock system according to claim 4, the computational methods that it is characterized in that the frequency control word computing module described in the step (5) are one of following two kinds:

（1）

；

（2）

。

6. clock system according to claim 1 is characterized in that: the loop filtering module of having pegged graft between phase discriminator and DDS waveform generation module and the single-chip microcomputer that carries analog to digital converter; The input of phase discriminator output linkloop filtration module, loop filtering module output connects the analog to digital converter input of single-chip microcomputer, and the single-chip microcomputer output connects the frequency control word input of DDS waveform generation module.

7. clock system according to claim 6 is characterized in that the data handling procedure of single-chip microcomputer comprises the steps:

(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value Corresponding frequency control word;

(2) analog to digital converter takes out the voltage output value of loop filter, and itself and benchmark numerical value are carried out the difference computing in difference calculating module, its operation result frequency adjustment amount computing module of making a gift to someone; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of loop filter output;

(3) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data , calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;

(4) the frequency control word computing module carries out the calculating of frequency control word, and the frequency control word that calculates back output is sent into the frequency judging module that transfinites and carried out the judgement of high low threshold;

(5) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;

(6) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.

8. clock system according to claim 7, the computational methods that it is characterized in that the frequency control word computing module described in the step (4) are one of following two kinds:

（1）

；

（2）

。

Images