CN103346874A - Digital communication clock synchronization system based on DDS - Google Patents
Digital communication clock synchronization system based on DDS Download PDFInfo
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Abstract
The invention discloses a digital communication clock synchronization system based on a DDS. The digital communication clock synchronization system based on the DDS comprises a waveform preprocessor, a phase discriminator, a prefilter, a system data processing module and a DDS waveform generating module. The waveform preprocessor is connected with one input end of the phase discriminator, the output end of the phase discriminator is connected with the input end of the prefilter, the output end of the prefilter is connected with the input end of the system data processing module, the output end of the system data processing module is connected with the frequency control word input end of the DDS waveform generating module, the output end of the DDS waveform generating module is connected with the other input end of the phase discriminator, and meanwhile synchronous clock signals are output. The digital communication clock synchronization system controls the output of the DDS through a control algorithm with a highest frequency and a lowest threshold value, the DDS characteristics of being wide in covered frequency range, flexible in output frequency control and high in resolution ratio are fully utilized, and the digital communication clock synchronization system is not provided with an adjustable element, is low in debugging difficulty, enables working frequency to be easily set, and is suitable for multi-rate work.
Description
Technical field
The present invention relates to the Clock Synchronization Technology field in the data transmission system, be specifically related to a kind of digital communication clock system based on DDS.
Background technology
Current communication system just develops towards many systems, multimodal direction, and for the communication system of the many systems of compatibility, its rate of information throughput is varied, and receiving terminal realizes that the clock system of clock recovery will adapt to diversified speed.Clock Synchronization Technology mainly contains the Clock Synchronization Technology of utilizing analog phase-locked look, the all-digital phase-locked loop Clock Synchronization Technology of utilizing methods such as adding button pulse, change mould frequency division to realize in the current communication system, and these technology will realize that under multiple communications speed clock has corresponding difficulty synchronously.
Analog phase-locked look (PLL) clock synchronous extraction circuit uses voltage controlled oscillator (VCO), and Fig. 1 realizes the theory diagram that clock extracts synchronously for the PLL circuit.Frequency and the phase place of phase-locked loop control VCO change, and make the clock of VCO output with synchronous to the chip rate that receives data.It is very big that but the centre frequency of VCO, frequency range are influenced by component parameters, is subjected to Effect of Environmental such as temperature, humidity also bigger, and debugging difficulty is bigger.The VCO also difficult frequency of wide region of accomplishing covers, and the analog phase-locked look clock synchronization circuit is difficult to adapt to the synchronous task of multiple transmission rate clock.
All-digital phase-locked loop clock synchronous extraction circuit uses digital controlled oscillator, and Fig. 2 realizes the schematic diagram block diagram that clock extracts synchronously for all-digital phase-locked loop.The mode that digital controlled oscillator is commonly used has high frequency clock to add button pulsed digital controlled oscillator or high frequency clock becomes mould frequency division formula digital controlled oscillator.Phase discriminator obtains phase of input signals in each cycle and the local signal phase place is leading or the information of hysteresis, adds button pulse control, perhaps becomes the control of mould frequency division, changes the clock phase state of exporting, and makes the data sync of local clock and reception.Because use high frequency clock and carry out frequency division, the high frequency clock that produce multiple different frequency has certain complexity; Equally, the clock of enable clock synchronous circuit output to satisfy the demand of multiple transmission rate, carry out the fraction scale frequency division, control divide ratio neatly and could realize, so the method also has bigger complexity.
Summary of the invention
At the deficiencies in the prior art, the invention provides a kind of system that utilizes Direct Digital Synthesizer (DDS) module to realize the clock synchronous phase-locked loop road.With DDS as the controllable frequency source, and by having frequency is the highest, the control algolithm of minimum threshold is controlled the output of DDS, take full advantage of DDS covering frequence wide ranges, output frequency control flexibly, the characteristic that resolution is high, realized there is not adjustable element, debugging difficulty is low, it is easy that operating frequency is set, and is suitable for the digital communication clock system of many speed work.
The present invention is achieved through the following technical solutions:
A kind of digital communication clock system based on DDS comprises the waveform preprocessor, phase discriminator, DDS waveform generation module; Waveform preprocessor output connects an input of phase discriminator, and the phase discriminator output connects the frequency control word input of DDS waveform generation module, and DDS waveform generation module output connects another input of phase discriminator, exports synchronizing clock signals simultaneously.
Handle the prefilter of between phase discriminator and DDS waveform generation module, having pegged graft for being conducive to data; The phase discriminator output connects the input of prefilter, and the prefilter output connects the frequency control word input of DDS waveform generation module.
In order to obtain better technique effect, the system data processing module of between prefilter output and DDS waveform generation module input, having pegged graft; The input of prefilter output connected system data processing module, system data processing module output connects the frequency control word input of DDS waveform generation module.
Described system data processing module comprises that transfinite judging module and frequency control word of value module, difference calculating module, loop filtering module, frequency adjustment amount computing module, frequency control word computing module, frequency arranges module, and above-mentioned each module is docile and obedient order and is connected.The data handling procedure of data processing module comprises the steps:
(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value
Corresponding frequency control word;
(2) obtain the prefilter voltage output value by the value module, itself and benchmark numerical value are carried out the difference computing in difference calculating module; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of prefilter output;
(3) difference data is sent into the loop filtering module and is carried out integral operation, and its operation result is sent into frequency adjustment amount computing module;
(4) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data
, calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;
(5) the frequency control word computing module carries out the calculating of frequency control word, and the frequency control word that calculates back output is sent into the frequency judging module that transfinites and carried out the judgement of high low threshold;
(6) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;
(7) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.
Wherein, the computational methods of the frequency control word computing module described in the step (5) can be selected for use one of following two kinds:
（1）
；
（2）
。
Description of drawings
Fig. 1 extracts the circuit structure block diagram for the analog phase-locked look bit synchronization.
Fig. 2 extracts the circuit structure block diagram for the digital phase-locked loop bit synchronization.
Fig. 3 is the digital communication clock system circuit structure block diagram based on DDS.
Fig. 4 is the system data processing module FB(flow block) among Fig. 3.
Fig. 5 is for making the digital communication clock system circuit structure block diagram based on DDS of control of single-chip microcomputer.
Fig. 6 is the single-chip data process flow block diagram among Fig. 5.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Embodiment 1:
With reference to Fig. 3, baseband signal is input to signal pre-processing module, signal pre-processing module carries out shaping, the nonlinear transformation of signal to be handled, signal after shaping, the processing is input to an input of phase discriminator, the shaping that phase discriminator is relatively imported, the baseband signal after handling and feed back their phase place difference between the two of signal from the DDS waveform generation module, the output signal size of phase discriminator is corresponding to these two input signal phase differences.The effect of prefilter is that the high fdrequency component in the phase discriminator output signal is filtered, and the data after being conducive to are handled.After the signal of prefilter output is handled through data processing module, the frequency control word that generates DDS is controlled the DDS waveform generation module, the output signal of DDS waveform generator feeds back to another input of phase discriminator again, realize the FEEDBACK CONTROL of closed loop, constantly adjust DDS waveform generation module output signal frequency, make that the baseband signal of output signal frequency and phase place and input is synchronous, recover clock signal synchronous and output.
By external connection keyboard or I/O device the DDS initial value can be set
, and the highest, the minimum threshold of predetermined frequency control word (
And the highest, minimum threshold all is decided by the DDS module parameter), the system that makes can work in different communication data rate very easily, finishes the clock synchronous task under the multiple transmission rate.
Fig. 4 is the block diagram of system data processing module.Transfinite judge module, frequency control word of the frequency that is connected to initialization module arranges module, sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value
, make DDS module output frequency identical with the nominal value of system data transmission rate.System enters normal mode of operation after the initialization.Obtain the output valve of prefilter by the value module, and be input to difference calculating module, difference calculating module is subtracted each other output valve and the benchmark numerical value of prefilter, obtains their difference.The output signal of difference calculating module is sent into the loop filtering module, carries out integral operation.Loop filter output is through the signal of integral processing, and this signal is sent to frequency adjustment amount computing module again.Frequency adjustment amount computing module multiply by voltage-controlled COEFFICIENT K with input signal, calculates the numerical value that the DDS output signal frequency need change, and voltage-controlled COEFFICIENT K is the voltage controlled gain of equivalence.The output signal of frequency adjustment amount computing module is sent into the frequency control word computing module, selects for use following calculating formula to carry out the calculating of frequency control word:
。
The frequency control word of frequency control word computing module output is sent into the frequency judging module that transfinites and is carried out the judgement of high low threshold, when frequency control word does not surpass preset the highest, in the time of minimum threshold, the frequency judging module that transfinites is directly delivered to the DDS frequency control word with the incoming frequency control word module is set, output signal frequency to the DDS waveform generator is adjusted, when frequency control word has surpassed preset the highest, minimum threshold, only get frequency control word the highest accordingly, minimum threshold, remove and exceed part, output to the DDS frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.
Embodiment 2:
Fig. 5, Fig. 6 have been to use the single-chip microcomputer of band analog to digital converter to do digital communication clock system circuit structure block diagram and the flow chart of data processing block diagram based on DDS of control.The system that realizes with embodiment 1 contrasts, its difference is that the loop filtering module realizes with circuit, finish the function of integration equally, and the input of phase discriminator output linkloop filtration module, loop filtering module output connects the analog to digital converter input of single-chip microcomputer, and this analog to digital converter is finished value as the value module.
The data handling procedure of single-chip microcomputer comprises the steps:
(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value
Corresponding frequency control word;
(2) analog to digital converter takes out the voltage output value of loop filtering module, and itself and benchmark numerical value are carried out the difference computing in difference calculating module, its operation result frequency adjustment amount computing module of making a gift to someone; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of loop filter output;
(3) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data
, calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;
(4) the frequency control word computing module carries out the calculating of frequency control word, and calculating formula is:
The frequency control word that calculates back output is sent into the frequency judging module that transfinites and is carried out the judgement of high low threshold;
(5) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;
(6) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.
Claims (8)
1. the digital communication clock system based on DDS comprises the waveform preprocessor, and phase discriminator is characterized in that: also comprise the DDS waveform generation module; Waveform preprocessor output connects an input of phase discriminator, and the phase discriminator output connects the frequency control word input of DDS waveform generation module, and DDS waveform generation module output connects another input of phase discriminator, exports synchronizing clock signals simultaneously.
2. clock system according to claim 1 is characterized in that: the prefilter of having pegged graft between phase discriminator and DDS waveform generation module; The phase discriminator output connects the input of prefilter, and the prefilter output connects the frequency control word input of DDS waveform generation module.
3. clock system according to claim 2 is characterized in that: the system data processing module of having pegged graft between prefilter and DDS waveform generation module; The input of prefilter output connected system data processing module, system data processing module output connects the frequency control word input of DDS waveform generation module.
4. clock system according to claim 3 is characterized in that described system data processing module comprises that according to the order of connection transfinite judging module and frequency control word of value module, difference calculating module, loop filtering module, frequency adjustment amount computing module, frequency control word computing module, frequency arranges module; The data handling procedure of system data processing module comprises the steps:
(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value
Corresponding frequency control word;
(2) obtain the prefilter voltage output value by the value module, itself and benchmark numerical value are carried out the difference computing in difference calculating module; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of prefilter output;
(3) difference data is sent into the loop filtering module and is carried out integral operation, and its operation result is sent into frequency adjustment amount computing module;
(4) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data
, calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;
(5) the frequency control word computing module carries out the calculating of frequency control word, and the frequency control word that calculates back output is sent into the frequency judging module that transfinites and carried out the judgement of high low threshold;
(6) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;
(7) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.
5. clock system according to claim 4, the computational methods that it is characterized in that the frequency control word computing module described in the step (5) are one of following two kinds:
（1）
；
（2）
。
6. clock system according to claim 1 is characterized in that: the loop filtering module of having pegged graft between phase discriminator and DDS waveform generation module and the single-chip microcomputer that carries analog to digital converter; The input of phase discriminator output linkloop filtration module, loop filtering module output connects the analog to digital converter input of single-chip microcomputer, and the single-chip microcomputer output connects the frequency control word input of DDS waveform generation module.
7. clock system according to claim 6 is characterized in that the data handling procedure of single-chip microcomputer comprises the steps:
(1) the DDS initialization module is connected to transfinite judge module, frequency control word of frequency module is set, and sends into the highest, the minimum threshold of predetermined frequency control word to the frequency judge module that transfinites, and to frequency control word module is set and sends into the frequency initial value
Corresponding frequency control word;
(2) analog to digital converter takes out the voltage output value of loop filter, and itself and benchmark numerical value are carried out the difference computing in difference calculating module, its operation result frequency adjustment amount computing module of making a gift to someone; Benchmark numerical value wherein is the arithmetic mean of the highest, the minimum voltage value of loop filter output;
(3) frequency adjustment amount computing module multiply by voltage-controlled coefficient with result data
, calculate the variable that the DDS output signal frequency needs, the frequency control word computing module of making a gift to someone then;
(4) the frequency control word computing module carries out the calculating of frequency control word, and the frequency control word that calculates back output is sent into the frequency judging module that transfinites and carried out the judgement of high low threshold;
(5) when frequency control word does not surpass preset the highest, minimum threshold, the frequency judging module that transfinites is directly delivered to frequency control word with the incoming frequency control word module is set, and the output signal frequency of DDS waveform generator is adjusted;
(6) when frequency control word has surpassed preset the highest, minimum threshold, frequency control word is only got the highest, minimum threshold accordingly, remove and exceed part, output to frequency control word module is set, the output signal frequency of DDS waveform generator is adjusted.
8. clock system according to claim 7, the computational methods that it is characterized in that the frequency control word computing module described in the step (4) are one of following two kinds:
（1）
；
（2）
。
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811139A (en) * | 2015-04-20 | 2015-07-29 | 浙江科技学院 | Vector network analysis method based on DDS spurious frequency application |
| CN106301658A (en) * | 2016-09-26 | 2017-01-04 | 湖南基石通信技术有限公司 | A kind of Extraction of Bit Synchronization Signal method and device |
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| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
| CN203340091U (en) * | 2013-06-20 | 2013-12-11 | 桂林电子科技大学 | DDS-based digital communication clock synchronization system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847992A (en) * | 2009-12-31 | 2010-09-29 | 南京国睿安泰信科技股份有限公司 | Frequency synthesis system for enhancing spectrum purity of direct digital frequency synthesizer |
| CN102201819A (en) * | 2011-03-07 | 2011-09-28 | 武汉理工大学 | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design |
| CN203340091U (en) * | 2013-06-20 | 2013-12-11 | 桂林电子科技大学 | DDS-based digital communication clock synchronization system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811139A (en) * | 2015-04-20 | 2015-07-29 | 浙江科技学院 | Vector network analysis method based on DDS spurious frequency application |
| CN104811139B (en) * | 2015-04-20 | 2018-06-05 | 浙江科技学院 | Vector network analysis method based on the application of DDS spurious frequencies |
| CN106301658A (en) * | 2016-09-26 | 2017-01-04 | 湖南基石通信技术有限公司 | A kind of Extraction of Bit Synchronization Signal method and device |
| CN106301658B (en) * | 2016-09-26 | 2018-11-09 | 湖南基石通信技术有限公司 | A kind of Extraction of Bit Synchronization Signal method and device |
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