CN101170399B - A clock synchronization method in distributed base station and the distributed base station - Google Patents
A clock synchronization method in distributed base station and the distributed base station Download PDFInfo
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Abstract
The invention provides a distributed base station and a clock synchronization method in the distributed base station. The distributed base station comprises a base-band unit and a RF remote unit; wherein, the RF remote unit comprises a phase-locked loop unit which is used to receive and recover a clock signal input by the base-band unit and generate a local basic clock synchronized with the clocksignal by locking phase to the clock signal. The method comprises the steps that the RF remote unit receives and recovers the clock signal input by the base-band unit; the RF remote unit locks phase to the clock signal and generates the local basic clock synchronized with the clock signal. The invention realizes the clock synchronization between the distributed base station BBU and PPU, saves theproduct development cost, has good universality and is applied in a plurality of communications systems such as GSM, WCDMA, etc.
Description
Technical field
The present invention relates to communication field, particularly relate to clock synchronizing method and distributed base station in a kind of distributed base station.
Background technology
Enhancing, the more high reason of dense city site resource the engineering cost day by day rare and traditional base station along with people's environmental consciousness, distributed base station based on BBU+RRU after 2005 is convenient to rapid construction, is saved cost with it, progressively become the main flow of base station of new generation, and obtain to use as far back as the WCDMA field.Different with traditional base station is, distributed base station has been divided into two independent parts: RF remote unit (RRU, Remote Radio Unit) with Base Band Unit (BBU, Base band Unit), and by long-distance transmissions means such as optical fiber or cable both are connected, then radio frequency unit is placed on the place of various needs.
When utilizing traditional macro base station networking mode to build wireless network such as gsm wireless network in the high traffic area; usually can there be problems such as station for acquiring difficulty, engineering construction complexity, equipment utilization be insufficient, make operator be difficult to effectively reduce networking and operation cost.The distributed base station solution of BBU+RRU produces under this background just.Yet when adopting this scheme of BBU+RRU, BBU communicates by optical fiber or cable and RRU, and this just certainly exists the clock synchronization issue between BBU and the RRU.
Summary of the invention
The purpose of this invention is to provide clock synchronizing method and distributed base station in a kind of distributed base station, with the Base Band Unit realizing being separated in the distributed base station and the clock synchronization between the RF remote unit.
To achieve these goals, the invention provides a kind of distributed base station, comprise interconnective Base Band Unit and RF remote unit, wherein, described RF remote unit comprises:
Phase locked-loop unit is used to receive and recover the clock signal that described Base Band Unit is imported, and described clock signal is carried out the phase-locked local basis clock synchronous with described clock signal that produce;
Described phase locked-loop unit comprises: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for the aanalogvoltage according to described D/A conversion unit output, produces the local basis clock, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
Described base station, wherein, described clock phase discrimination unit is the programmable logic array device.
Described base station, wherein, described VCO unit comprises: temperature compensating crystal oscillator, constant temperature quartz oscillator or VCXO.
The invention also discloses a kind of RF remote unit, wherein, comprising: phase locked-loop unit is used to receive and recover the clock signal that Base Band Unit is imported, and described clock signal is carried out the phase-locked local basis clock synchronous with described clock signal that produce;
Described phase locked-loop unit comprises: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports described voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for producing the local basis clock according to the aanalogvoltage of described D/A conversion unit output, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
The invention also discloses a kind of phase-locked loop apparatus, wherein, comprising: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports described voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for producing the local basis clock according to the aanalogvoltage of described D/A conversion unit output, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
The invention also discloses the clock synchronizing method in a kind of distributed base station, wherein, comprise the steps:
Step 1, RF remote unit receives and recovers the clock signal of Base Band Unit input;
Step 2, RF remote unit carries out phase-locked to described clock signal, and generation and the synchronous local basis clock of described clock signal.
Described step 2 comprises:
Step a, the clock phase discrimination unit carries out phase demodulation to described clock signal and local basis clock signal, and obtains the phase demodulation value;
Step b, the phase locked algorithm unit carries out linearization process to described phase demodulation value, and calculates voltage-controlled voltage;
Step c, D/A conversion unit is an aanalogvoltage with described voltage-controlled voltage transitions;
Steps d, the VCO unit produces the local basis clock according to described aanalogvoltage, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described step b comprises:
Carry out the sampling of phase demodulation value, obtain the phase demodulation value of clock phase discrimination unit output, and described phase demodulation value and the standard phase demodulation value of presetting are compared, obtain the phase demodulation difference;
The phase demodulation difference that obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
According to the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain;
Carry out the judgement of phase locked state switch condition according to the voltage-controlled voltage that calculates.
Described method, wherein, described step a comprises:
The local basis clock is carried out frequency division, and the clock signal of described Base Band Unit input is carried out frequency multiplication;
Gather local basis clock behind the described frequency division with described doubled clock;
Calculate the distance of the rising edge pulse of the local basis clock behind the described frequency division with described doubled clock, calculate and once just produce an interruption, and obtain the phase demodulation value, described phase demodulation value is the counter value that obtains.
Technique effect of the present invention is:
The present invention realizes the BBU of distributed base station and the clock synchronization between the RRU by phase locked-loop unit is set in RRU, saved product development cost, and versatility is better, uses and GSM plurality of communication systems such as WCDMA.
Description of drawings
Fig. 1 is the structural representation of the distributed base station of one embodiment of the invention;
Fig. 2 is the structural representation of the distributed base station of another embodiment of the present invention;
Fig. 3 is the structural representation of the distributed base station of further embodiment of this invention;
Fig. 4 is in one embodiment of the invention, a kind of specific implementation of phase locked-loop unit;
Fig. 5 is the schematic flow sheet of the clock synchronizing method of one embodiment of the invention;
Fig. 6 is in one embodiment of the invention, and RF remote unit carries out phase-locked schematic flow sheet.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
The present invention utilizes the phase-locked BBU of distributed base station and the clock synchronization between the RRU of realizing of software.
Fig. 1 is the structural representation of the distributed base station of one embodiment of the invention.As Fig. 1, the distributed base station 100 of one embodiment of the invention comprises: Base Band Unit 101 and RF remote unit 102; RF remote unit 102 comprises again: phase locked-loop unit 103 is used to receive and recover the clock signal that Base Band Unit is imported, and the clock signal that recovers is carried out phase-locked local basis clock with the synchronous RF remote unit of generation and clock signal.Wherein, Base Band Unit is connected by the long-distance transmissions means with RF remote unit.Exemplarily, BBU is connected by optical fiber with RRU, and BBU can be configured to its optical interface the REC pattern, and RRU can be configured to its optical interface the RE pattern.
Fig. 2 is the structural representation of the distributed base station of another embodiment of the present invention.As Fig. 2, in this embodiment of the present invention, phase locked-loop unit 103 comprises: clock phase discrimination unit 201, phase locked algorithm unit 202, D/A conversion unit (D/A converting unit) 203 and VCO unit 204.The clock phase discrimination unit, mainly finish the phase discriminator function in the phase-locked loop, be used to obtain external reference clock and local basis clock, and these two clocks are carried out phase demodulation, and a phase demodulation value that obtains outputs to the phase locked algorithm unit, wherein, the said external reference clock is clock signal BBU input, that recover at the RRU optical interface; The phase locked algorithm unit, be the phase-locked key link of software, this unit obtains the phase demodulation value from the clock phase discrimination unit, described phase demodulation value is carried out linearization process, and finish the calculating of voltage-controlled voltage, and export the voltage-controlled voltage of digital voltage form to D/A conversion unit according to the phase demodulation value; D/A conversion unit is used to finish digital-to-analogue conversion, and the voltage-controlled voltage transitions that is about to the output of phase locked algorithm unit is an aanalogvoltage, and exports aanalogvoltage the frequency of VCO unit with control VCO unit to; The VCO unit is used for producing the local basis clock according to the aanalogvoltage of D/A conversion unit output, and exports the local basis clock that produces to the clock phase discrimination unit; The VCO unit is controlled by aanalogvoltage, and the frequency of the local basis clock that it produces can change along with the variation of aanalogvoltage; So just formed a closed-loop control system.
Fig. 3 is in one embodiment of this invention, the structural representation of phase locked algorithm unit.As Fig. 3, this phase locked algorithm unit 202 comprises: phase demodulation value sampling unit 301, and the phase demodulation value is sampled with the phase demodulation value of acquisition clock phase discrimination unit output, and phase demodulation value that obtains and the standard phase demodulation value of presetting are compared, obtain the phase demodulation difference, and preserve the phase demodulation difference; Filter unit 302, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, wherein, phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, deduct first the phase demodulation value by current phase demodulation value and obtain, phase increment be current phase increment accumulative total with last time phase increment accumulative total poor, deduct last time phase increment accumulative total by current phase increment accumulative total and obtain; Voltage-controlled voltage computing unit 303 is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit; Phase-locked processing unit 304 is used for carrying out according to voltage-controlled voltage the judgement of phase locked state switch condition.
Fig. 4 is in one embodiment of the invention, a kind of specific implementation of phase locked-loop unit.As Fig. 4, in this specific implementation, the phase discrimination function of clock phase discrimination unit is realized by programmable logic array FPGA device, the phase locked algorithm unit is realized by corresponding phase-locked control algolithm is set in CPU, D/A conversion unit is realized by analog-digital chip, as the AD5541 chip, the VCO unit is realized by the brilliant battle array of temperature-compensating TCXO.In this specific implementation, what lock out is the local basis clock of a 10M.The reference clock 61.44M that FPGA recovers the RRU optical interface and the output clock 10M of the brilliant battle array of local 10M carry out phase demodulation, export one 21 phase demodulation value, and this phase demodulation value is sent to CPU calculate a magnitude of voltage to utilize phase-locked control algolithm; If this magnitude of voltage with last time magnitude of voltage different, then give FPGA this magnitude of voltage, send to D/A chip AD5541 by FPGA, AD5541 is converted to aanalogvoltage to digital voltage, control local brilliant battle array with this aanalogvoltage and obtain the 10M clock, that the brilliant battle array of local 10M adopts is the brilliant battle array of temperature-compensating TCXO, and 10M local basis clock sends to FPGA again, thereby forms closed control circuit.
Fig. 5 is the schematic flow sheet of the clock synchronizing method of one embodiment of the invention.As Fig. 5, the method for one embodiment of the invention comprises:
Further, referring to Fig. 6, it is that step 502 comprises that one embodiment of the invention radio frequency unit carries out phase-locked step:
Step 601 is carried out clock phase discrimination, phase demodulation be exactly comparison external reference clock be that input clock and the TCXO output clock of the BBU that recovers of RRU is the phase place or the difference on the frequency of local basis clock; Particularly, can carry out clock phase discrimination by clock phase discrimination unit such as FPGA.
Exemplarily, BBU sends to the light mouth chip that RRU holds to the clock of 61.4Mhz by optical fiber, and RRU end light mouth chip recovers the 61.4Mhz clock, and sends to clock phase discrimination unit such as FPGA, then, FPGA receives simultaneously from local brilliant gust 10Mhz clock and carries out the clock phase discrimination function.Phase demodulation has two important parameters: precision of phase discrimination and phase demodulation time, precision of phase discrimination is relevant with the phase demodulation clock, and the phase demodulation clock adopts the inner frequency multiplication of FPGA to draw, and the phase demodulation time is relevant with the local basis clock.
Further, this phase demodulation step comprises:
Steps A is carried out frequency division to the local basis clock, and outside reference clock is carried out frequency multiplication;
Step B adopts local basis clock behind the frequency division with the external reference clock of frequency multiplication;
Step C calculates the distance of the rising edge pulse of the local clock behind the frequency division with the reference clock after the frequency multiplication, calculates and once just produces an interruption, obtains a counter value, and promptly the phase demodulation value sends to the phase locked algorithm unit with this value, as CPU.
Provide the instantiation that the phase demodulation value obtains below.
1) 10MHz local basis clock division is become the 5Hz clock, the 61.44MHz clock multiplier is the 245.76Mhz clock;
2) get the rising edge of 5Hz clock with the 245.76MHz clock, pulse duration is a 245.76MHz clock cycle;
3) distance of the rising edge pulse of usefulness 245.76MHz clock calculation 5Hz clock calculates and once just produces an interruption, obtains a counter value, gives the phase locked algorithm unit with this value.
In this example, the phase demodulation clock frequency is 245.76MHz just, and the phase demodulation cycle is 200ms.And go number 5hz to obtain counter value about 491512000 with 245.76Mhz, because it is limited that the frequency of TCXO is adjusted, the counter that calculates the rising edge pulse distance of 5Hz in the FPGA can only keep low level, the high position of the distance of the rising edge pulse of 5Hz all is the same under normal situation, only pays close attention to low 21 here.The maximum of 21 figure places represents that scope is 2097152, and 917504+2097152*23=491512000 is arranged again, so the standard phase demodulation value that we see is exactly 917503.
Step 602, phase locked algorithm unit such as CPU carry out linearization process to the phase demodulation value, and calculate voltage-controlled voltage;
This step specifically comprises:
Step a1, the sampling of phase demodulation value, the every 200ms of FPGA gives CPU a phase demodulation value, produces once to interrupt, and CPU obtains this phase demodulation value, compares with standard phase demodulation value, obtains the phase demodulation difference, and preserves the phase demodulation difference;
Step b1, linearization phase demodulation difference is finished filter function; Remove repeatly by the phase demodulation difference that phase demodulation value sampling the is obtained phase demodulation difference of suddenling change, then, calculate current phase demodulation value, and preserve the first time that calculates current phase demodulation value as phase demodulation value first; Voltage-controlled voltage needs two control coefrficients to obtain from the linearization process process, and one is phase increment, and one is phase increment accumulative total; Phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, deducts by current phase demodulation value that phase demodulation value first obtains; Phase increment be current phase increment accumulative total with last time phase increment accumulative total poor, obtain by deduct last time phase increment accumulative total with current phase increment accumulative total.Like this, just finished the function of filtering.
Step c1 calculates voltage-controlled voltage.The calculating of voltage-controlled voltage is that the formula according to the phase-locked control principle of clock obtains.Formula is as follows:
delt＝Ka*phase+Kd*dphase
Wherein delt is the control voltage increment of VCO unit, and phase is the phase place of clock, and dphase is the variation of clock phase, and Ka, Kd is a weight coefficient.In the present invention, phase is the phase demodulation increment size, and dphase is a phase demodulation increment aggregate-value.In addition, there are five states in the state of phase-locked loop, and quadruplet Ka is arranged accordingly, the Kd value, and it is out-of-lock condition that a state is arranged.
Steps d 1, phase-locked processing is carried out mode switch and is judged; Phase locked state comprises five states, be respectively heating, fast seizure, quick lock in, lock at a slow speed and keep.At first, carry out clock signal and whether detect normally, undesiredly then need alarm.Then, exactly the state exchange of phase-locked loop is carried out condition judgment.Normal starting state conversion is: catch fast lock soon, be locked into lock slowly soon.TCXO does not need preheating.And hold mode is an out-of-lock condition, and phase-locked loop just jumps to hold mode when losing lock.
(1) heating
For constant temperature quartz oscillator OCXO, need a heating time, temperature compensating crystal oscillator TCXO and common VCXO VCXO do not need heating, under the prerequisite that guarantees whole phase-locked framework, this time can be very short, Ka under this state, Kd is 0, and the input voltage of TCXO is a definite value.In the present invention, this input voltage value is a default voltage 0X8000, and this value corresponds to the intermediate voltage of AD5541, and theoretical value is 2.5V, in addition, under preheat mode, is not need to regulate and control the brilliant battle array of voltage control.The purpose of this state is exactly the brilliant battle array of preheating, makes brilliant battle array enter normal operating conditions rapidly.
(2) catch fast
Owing to be in phase-locked initial condition this moment, the local clock frequency can be bigger with the frequency departure of expection lock-out state, so, at this moment Kd plays a decisive role, the big and Kd of Kd＞＞Ka, TCXO draws close when acquiring a certain degree to target frequency rapidly, is indifferent to for the time being as for phase place.When the phase demodulation difference Phdelt in regular hour T just can enter next state quick lock in less than certain value.This stage is can consumable time ratio more.And it also is the previous stage that phase-locked loop arrives tracking mode.
Each coefficient reference value under the quick trap state:
Ka＝0.00001；Kd＝33；T＝100s；Phdelt＝500；
(3) quick lock in
When phase locked state reached this state, TCXO was near target frequency, and phase-locked loop has entered tracking mode.At this moment Ka, Kd works, and relatively and preceding state, it is big that Ka becomes, and Kd diminishes.But Kd is still greater than Ka, and the effect of Ka is to prevent that TCXO from producing overshoot when target frequency is adjusted, and guarantees that the adjustment of TCXO is slow more the closer to the target frequency adjustment, that is to say to the close speed of target frequency slow.When just can entering next state less than certain value, phase demodulation difference Phdelt in regular hour T locks at a slow speed.In this case, if the phase demodulation difference is excessive, just the phase demodulation value is shaken, and phase-locked loop will return back to quick trap state.
Each coefficient reference value under the quick lock in state:
Ka＝1.4；Kd＝20；T＝100s；Phdelt＝150；
(4) locking at a slow speed
This state is phase-locked final steady operation lock-out state.At this moment Ka, Kd works, and the value of Kd is all little during than quick lock in, and the bigger stability that at this moment mainly will keep phase place of the value of Ka guarantees the PLL steady operation, is the long-term stable operation state of PLL.If the phase demodulation difference is excessive, just the phase demodulation value is shaken in this case, and PLL will return back to the quick lock in state, but this all belongs to normal condition.
Each coefficient reference value under the lock-out state at a slow speed:
Ka＝2；Kd＝5；Phdelt＝150；
(5) keep
This state is to be out-of-lock condition.Phase-locked loop will jump to this state from normal condition under the situation that relevant phase-locked condition can't satisfy.If condition has been recovered again, phase-locked loop just again can be phase-locked again, until locked clock.In addition, under this state, the DA value when regulation and control voltage can remain to last lock-out state.At this moment, the variation of phase demodulation value can not produce any influence to phase-locked loop.
In above-mentioned state, to catch soon, lock and lock soon slowly need compare voltage-controlled voltage that calculates and the voltage of last time, if the two difference, the frequency of then this voltage being given DA adjusting TCXO.And the Rule of judgment of the state exchange of phase-locked loop is in the regular hour scope, and whether the phase demodulation increment surpasses certain limit, and when the phase demodulation increment size was in limited range in meeting limiting time, phase-locked loop just jumped to another state from a state, up to locking.
The voltage-controlled voltage transitions that step 603, D/A conversion unit will calculate is an aanalogvoltage.
Step 604, the VCO unit produces the local basis clock according to aanalogvoltage, and exports the local basis clock that produces to the clock phase discrimination unit, to form closed-loop control system.
In the method for this embodiment of the invention, each step can realize by the function corresponding unit.
Compare with traditional hardware lock ring, software phase-lock loop can be achieved as follows the requirement that hardware phase-locked-loop is difficult to realize based on superiority:
(1) can utilize computer flexible processing ability to realize optimizing filtering or adaptive-filtering.
Filtering can form infinitely-great DC current gain with the form of digital integration, regulates to realize complete indifference.If wish the frequency multiplication composition that multiplier produces is filtered, can design a kind of digital filtering algorithm, making its frequency multiplication part at filtering voltage is zero point, and can remove to revise filtering algorithm according to actual measurement filtering voltage value when signal changes, and also and then changed to satisfy test request its zero point.This is to be difficult to realize in hardware is phase-locked;
(2) can change integrated value by force to realize quick lock in;
The electric current of the integrated value in the hardware circuit such as the voltage of electric capacity, inductance etc. can not suddenly change.But the data in the program can be according to actual needs assignment by force, can realize step locking like this.
(3) act on the theory that BBU+RRU saves cost, software is phase-locked with respect to the phase-locked Products Development cost of also having saved greatly of hardware.
By above-mentioned argumentation as can be known, to be applied in the BBU+RRU product be extraordinary selection to the phase-locked scheme of software.Adopt the method for the invention, compared with prior art, reached the effect of the clock synchronization between Base Band Unit and the RF remote unit, saved product development cost, and versatility is better, use and GSM plurality of communication systems such as WCDMA.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. a distributed base station comprises interconnective Base Band Unit and RF remote unit, it is characterized in that, described RF remote unit comprises:
Phase locked-loop unit is used to receive and recover the clock signal that described Base Band Unit is imported, and described clock signal is carried out the phase-locked local basis clock synchronous with described clock signal that produce;
Described phase locked-loop unit comprises: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for the aanalogvoltage according to described D/A conversion unit output, produces the local basis clock, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
2. base station according to claim 1 is characterized in that, described clock phase discrimination unit is the programmable logic array device.
3. base station according to claim 1 is characterized in that, described VCO unit comprises: temperature compensating crystal oscillator, constant temperature quartz oscillator or VCXO.
4. a RF remote unit is characterized in that, comprising: phase locked-loop unit is used to receive and recover the clock signal that Base Band Unit is imported, and described clock signal is carried out the phase-locked local basis clock synchronous with described clock signal that produce;
Described phase locked-loop unit comprises: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports described voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for producing the local basis clock according to the aanalogvoltage of described D/A conversion unit output, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
5. a phase-locked loop apparatus is characterized in that, comprising: clock phase discrimination unit, phase locked algorithm unit, D/A conversion unit and VCO unit,
The clock phase discrimination unit is used for described clock signal and local basis clock are carried out phase demodulation, and exports the phase demodulation value that obtains to the phase locked algorithm unit;
The phase locked algorithm unit is used for described phase demodulation value is carried out linearization process, and calculates voltage-controlled voltage, and exports described voltage-controlled voltage to D/A conversion unit;
D/A conversion unit, the voltage-controlled voltage transitions that is used for the output of described phase locked algorithm unit is an aanalogvoltage, and exports described aanalogvoltage to the VCO unit;
The VCO unit is used for producing the local basis clock according to the aanalogvoltage of described D/A conversion unit output, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described phase locked algorithm unit comprises:
Phase demodulation value sampling unit is used to obtain the phase demodulation value that the clock phase discrimination unit is exported, and described phase demodulation value and the standard phase demodulation value of presetting are compared, and obtains the phase demodulation difference;
Filter unit, be used for the phase demodulation difference that described phase demodulation value sampling unit obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
Voltage-controlled voltage computing unit is used for the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain according to filter unit;
Phase-locked processing unit is used for carrying out the judgement of phase locked state switch condition according to described voltage-controlled voltage.
6. the clock synchronizing method in the distributed base station is characterized in that, comprises the steps:
Step 1, RF remote unit receives and recovers the clock signal of Base Band Unit input;
Step 2, RF remote unit carries out phase-locked to described clock signal, and generation and the synchronous local basis clock of described clock signal;
Described step 2 comprises:
Step a, the clock phase discrimination unit carries out phase demodulation to described clock signal and local basis clock signal, and obtains the phase demodulation value;
Step b, the phase locked algorithm unit carries out linearization process to described phase demodulation value, and calculates voltage-controlled voltage;
Step c, D/A conversion unit is an aanalogvoltage with described voltage-controlled voltage transitions;
Steps d, the VCO unit produces the local basis clock according to described aanalogvoltage, and exports the local basis clock of described generation to described clock phase discrimination unit;
Described step b comprises:
Carry out the sampling of phase demodulation value, obtain the phase demodulation value of clock phase discrimination unit output, and described phase demodulation value and the standard phase demodulation value of presetting are compared, obtain the phase demodulation difference;
The phase demodulation difference that obtains is carried out linearization process, and acquisition phase increment and phase increment accumulative total, described phase increment accumulative total is poor for current phase demodulation value and phase demodulation value first, described phase increment be current phase increment accumulative total with last time phase increment accumulative total poor;
According to the phase increment and the voltage-controlled voltage of phase increment cumulative calculation that obtain;
Carry out the judgement of phase locked state switch condition according to the voltage-controlled voltage that calculates.
7. method according to claim 6 is characterized in that, described step a comprises:
The local basis clock is carried out frequency division, and the clock signal of described Base Band Unit input is carried out frequency multiplication;
Gather local basis clock behind the described frequency division with described doubled clock;
Calculate the distance of the rising edge pulse of the local basis clock behind the described frequency division with described doubled clock, calculate and once just produce an interruption, and obtain the phase demodulation value, described phase demodulation value is the counter value that obtains.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854631B (en) * | 2009-03-31 | 2012-12-26 | 中国移动通信集团公司 | Method for realizing wireless signal coverage and base station system |
| CN102469571B (en) * | 2010-11-12 | 2014-07-02 | 中兴通讯股份有限公司 | Method and system for realizing delay compensation in distributed base station system |
| CN102725994B (en) * | 2011-01-26 | 2016-01-20 | 华为技术有限公司 | A kind of method and apparatus realizing time synchronized |
| CN103916198B (en) * | 2012-12-29 | 2016-04-06 | 重庆重邮信科通信技术有限公司 | Timing Synchronization evaluated error method of testing and system |
| CN103384194B (en) * | 2013-07-11 | 2016-08-10 | 浙江大学 | The phase-locked system of spatial distribution unit |
| WO2017096557A1 (en) * | 2015-12-09 | 2017-06-15 | 华为技术有限公司 | Method, device, and system for clock synchronization among base band units |
| WO2018098815A1 (en) * | 2016-12-02 | 2018-06-07 | 华为技术有限公司 | Phase correction method and device |
| CN108259035B (en) * | 2016-12-29 | 2022-03-25 | 国家无线电监测中心检测中心 | Reference clock determining method and device |
| CN109525381B (en) * | 2018-12-11 | 2020-12-29 | 中国电子科技集团公司第五十四研究所 | Clock synchronization device suitable for auxiliary multiplexer/demultiplexer |
| CN110518934B (en) * | 2019-08-13 | 2021-06-04 | 广州广电计量检测股份有限公司 | Synchronization method of optical transport network |
| CN110445573B (en) * | 2019-08-20 | 2020-09-25 | 广州粒子微电子有限公司 | NB-IoT terminal verification platform and clock synchronization method thereof |
| CN111162862B (en) * | 2019-12-31 | 2021-09-24 | 京信网络系统股份有限公司 | Distributed multi-network element clock transmission system |
| CN111181680A (en) * | 2019-12-31 | 2020-05-19 | 京信通信系统（中国）有限公司 | System for transmitting clock |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1484888A (en) * | 2001-01-10 | 2004-03-24 | ADC��ɫ�е��Ź�˾ | Phase locked loop |
| CN2807620Y (en) * | 2005-06-22 | 2006-08-16 | 上海和广通信技术有限公司 | Repeater in mobile communications system |
| CN2836382Y (en) * | 2005-09-09 | 2006-11-08 | 华为技术有限公司 | Baseband unit of distributed base station |
| CN1867119A (en) * | 2005-12-02 | 2006-11-22 | 华为技术有限公司 | Clock recovery method and apparatus in RF far-end module |
-
2007
- 2007-11-28 CN CN200710178274XA patent/CN101170399B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1484888A (en) * | 2001-01-10 | 2004-03-24 | ADC��ɫ�е��Ź�˾ | Phase locked loop |
| CN2807620Y (en) * | 2005-06-22 | 2006-08-16 | 上海和广通信技术有限公司 | Repeater in mobile communications system |
| CN2836382Y (en) * | 2005-09-09 | 2006-11-08 | 华为技术有限公司 | Baseband unit of distributed base station |
| CN1867119A (en) * | 2005-12-02 | 2006-11-22 | 华为技术有限公司 | Clock recovery method and apparatus in RF far-end module |
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