CN118199621A - Clock data recovery circuit and clock data recovery method based on phase-locked loop - Google Patents

Clock data recovery circuit and clock data recovery method based on phase-locked loop Download PDF

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CN118199621A
CN118199621A CN202410274018.4A CN202410274018A CN118199621A CN 118199621 A CN118199621 A CN 118199621A CN 202410274018 A CN202410274018 A CN 202410274018A CN 118199621 A CN118199621 A CN 118199621A
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phase
signal
module
locked loop
phase error
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胡远冰
宋飞
朱立平
陈阔
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Shanghai Anlu Information Technology Co ltd
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Shanghai Anlu Information Technology Co ltd
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Abstract

The invention discloses a clock data recovery circuit and a clock data recovery method based on a phase-locked loop, wherein the clock data recovery circuit comprises: the phase-locked loop module, the phase discriminator module, the loop filter module and the gain equalization module; the phase-locked loop module is used for generating a sampling clock signal based on the current clock frequency and the acquired reference clock signal; the phase discriminator module is used for comparing the phase of the acquired sampling clock signal with the phase of the input data to obtain a phase error signal; the loop filter module is used for carrying out filtering processing on the obtained phase error signal to obtain a phase error filtering signal; the gain equalization module is used for performing feedforward compensation processing on the obtained phase error filtering signal to obtain a phase-locked loop frequency division ratio; the phase-locked loop module is also used for adjusting the clock frequency based on the acquired phase-locked loop frequency division ratio; compared with the prior art, the technical scheme of the invention eliminates the limitation of the phase-locked loop bandwidth on the stability of the clock data recovery loop by adding the gain equalization module.

Description

Clock data recovery circuit and clock data recovery method based on phase-locked loop
Technical Field
The present invention relates to the field of digital communications, and in particular, to a clock data recovery circuit and a clock data recovery method based on a phase locked loop.
Background
The clock recovery (Clock Data Recovery, CDR) module at the receiving end of the serial-to-parallel converter (Ser ial ization & De-ser ial izatio, serDes) is one of the crucial parts, in high-speed data transmission, the sending end does not directly transmit the sampling clock, but generates a local clock signal at the receiving end through a phase-locked loop (Phase Locked Loop, PLL), and the CDR functions to dynamically adjust the phase of the local clock according to the phase relationship between the received data and the local clock signal, so as to achieve correct sampling and timing of the data.
The general CDR structure includes a Phase Detector (PD) and a Proportional-integral controller (PI), where the Phase Detector is configured to compare a Phase difference between input data and a local clock signal, output a signal indicating an advance or delay condition of the clock relative to the data, and the PI adjusts a Phase of the local clock according to the signal to implement a clock recovery and data retiming function; to extend the frequency tracking range, the phase discrimination result of the phase discriminator is typically integrated to control the PLL divide ratio.
In the prior art, in order to simplify the design and improve the performance, it is considered to remove the PI part, and directly use the output signal of the phase detector to control the frequency division ratio of the PLL; the method can reduce complexity and improve the stability and performance of the system; however, to ensure the stability of the system, the bandwidth of the PLL is usually greater than 10 times of the bandwidth of the CDR, but cannot exceed 1/10 of the bandwidth of the reference clock, which places a limitation on the design of the PLL, so how to eliminate the limitation of the influence of the bandwidth of the PLL on the stability of the system in the design to ensure the normal operation of the system is a technical problem that needs to be solved at present.
Disclosure of Invention
The invention aims to solve the technical problems that: the clock data recovery circuit and the clock data recovery method based on the phase-locked loop are provided, and the limitation of the phase-locked loop bandwidth on the stability of the clock data recovery loop is eliminated by adding a gain equalization module.
In order to solve the above technical problems, the present invention provides a clock data recovery circuit based on a phase locked loop, comprising: the phase-locked loop module, the phase discriminator module, the loop filter module and the gain equalization module;
the phase-locked loop module is used for acquiring a reference clock signal, generating a sampling clock signal based on the current clock frequency and the reference clock signal, and inputting the sampling clock signal into the phase discriminator module;
The phase discriminator module is used for acquiring the sampling clock signal and input data, comparing the phase of the sampling clock signal with that of the input data to obtain a phase error signal, and inputting the phase error signal into the loop filter module;
The loop filter module is used for acquiring the phase error signal, filtering the phase error signal to obtain a phase error filtered signal, and inputting the phase error filtered signal into the gain equalization module;
the gain equalization module is used for acquiring the phase error filtering signal, performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio, and inputting the phase-locked loop frequency division ratio into the phase-locked loop module;
The phase-locked loop module is further configured to obtain the phase-locked loop frequency division ratio, and adjust the clock frequency based on the phase-locked loop frequency division ratio.
The invention provides a clock data recovery circuit based on a phase-locked loop, which further comprises:
the output end of the phase-locked loop module is connected with the input end of the phase discriminator module, the output end of the phase discriminator module is connected with the input end of the loop filter module, the output end of the loop filter module is connected with the input end of the gain equalization module, and the output end of the gain equalization module is connected with the input end of the phase-locked loop module.
In one possible implementation manner, the loop filter module is configured to perform filtering processing on the phase error signal to obtain a phase error filtered signal, and includes:
the loop filter module comprises a loop filter proportional path and a loop filter integral path;
the loop filter proportional path is used for carrying out scaling processing on the phase error signal based on proportional path gain to obtain a first filtering signal;
The loop filter integrating path is used for integrating the phase error signal based on the gain of the integrating path to obtain a second filtering signal;
the loop filter module is used for summing the first filtering signal and the second filtering signal to obtain a phase error filtering signal.
In one possible implementation manner, the gain equalization module is configured to perform feedforward compensation processing on the phase error filtered signal to obtain a pll frequency division ratio, and includes:
The gain equalization module is used for obtaining a first historical phase filtering signal of the previous period, performing scaling processing on the first historical phase filtering signal based on a gain factor to obtain a second historical phase filtering signal, performing data summation processing on the second historical phase filtering signal and the phase error filtering signal to obtain an output filtering signal, and obtaining a phase-locked loop frequency division ratio based on the output filtering signal.
In one possible implementation manner, the phase detector module is configured to perform phase comparison on the sampling clock signal and the input data to obtain a phase error signal, and includes:
the phase discriminator module is configured to perform left exclusive-or processing on the sampling clock signal and the input data to obtain a left exclusive-or signal, perform right exclusive-or processing on the sampling clock signal and the input data to obtain a right exclusive-or signal, perform exclusive-or processing on the left exclusive-or signal and the right exclusive-or signal to obtain an exclusive-or signal, and obtain a phase error signal based on the exclusive-or signal and the left exclusive-or signal.
In one possible implementation, the phase-locked loop module is configured to generate a sampling clock signal based on a current clock frequency and the reference clock signal, and includes:
The phase-locked loop module is used for carrying out frequency multiplication processing on the reference clock signal to obtain a frequency multiplication clock signal, and carrying out frequency division processing on the frequency multiplication clock signal based on the current clock frequency to obtain a sampling clock signal.
The invention provides a clock data recovery circuit based on a phase-locked loop, which further comprises:
Generating a transfer function of a clock data recovery circuit based on the phase-locked loop module, the phase detector module, the loop filter module, and the gain equalization module; wherein the transfer function is as follows:
In the formula, loop_gain is loop gain, e is natural logarithm, n del is loop delay, S is a parameter of an S domain, f ref is a reference clock frequency of a phase-locked loop, f cdr is an operating frequency of a clock data recovery circuit, kpd is phase discriminator gain, kp is proportional path gain of a proportional path of a loop filter, ki is integral path gain of an integral path of the loop filter, a is a gain factor, and omega pll is a first-order bandwidth approximate pole of a phase-locked loop module.
The invention also provides a clock data recovery method based on the phase-locked loop, which is applicable to the clock data recovery circuit based on the phase-locked loop, and comprises the following steps:
acquiring a reference clock signal, and generating a sampling clock signal based on a current clock frequency and the reference clock signal;
Acquiring input data, and performing phase comparison on the sampling clock signal and the input data to obtain a phase error signal;
filtering the phase error signal to obtain a phase error filtered signal;
performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio;
The clock frequency is adjusted based on the phase-locked loop divide ratio.
In one possible implementation manner, filtering the phase error signal to obtain a phase error filtered signal includes:
Respectively inputting the received phase error signals into a loop filter proportional path, so that the loop filter proportional path performs scaling processing on the phase error signals based on proportional path gain to obtain a first filtering signal;
Respectively inputting the received phase error signals into an integral path of a loop filter, so that the integral path of the loop filter integrates the phase error signals based on the gain of the integral path to obtain a second filter signal;
and summing the first filtering signal and the second filtering signal to obtain a phase error filtering signal.
In one possible implementation manner, performing feedforward compensation processing on the phase error filtered signal to obtain a phase-locked loop frequency division ratio, including:
And obtaining a first historical phase filtering signal of the previous period, performing scaling processing on the first historical phase filtering signal based on a gain factor to obtain a second historical phase filtering signal, performing data summation processing on the second historical phase filtering signal and the phase error filtering signal to obtain an output filtering signal, and obtaining a phase-locked loop frequency division ratio based on the output filtering signal.
In one possible implementation, the phase comparing the sampling clock signal and the input data to obtain a phase error signal includes:
And respectively performing left exclusive-or processing on the sampling clock signal and the input data to obtain a left exclusive-or signal, respectively performing right exclusive-or processing on the sampling clock signal and the input data to obtain a right exclusive-or signal, performing exclusive-or processing on the left exclusive-or signal and the right exclusive-or signal to obtain an exclusive-or signal, and obtaining a phase error signal based on the exclusive-or signal and the left exclusive-or signal.
In one possible implementation, generating a sampling clock signal based on a current clock frequency and the reference clock signal includes:
and performing frequency multiplication processing on the reference clock signal to obtain a frequency multiplication clock signal, and performing frequency division processing on the frequency multiplication clock signal based on the current clock frequency to obtain a sampling clock signal.
Compared with the prior art, the clock data recovery circuit and the clock data recovery method based on the phase-locked loop have the following beneficial effects:
The clock data recovery circuit comprises a phase-locked loop module, a phase discriminator module, a loop filter module and a gain equalization module; the phase-locked loop module is used for acquiring a reference clock signal, generating a sampling clock signal based on the current clock frequency and the reference clock signal, and inputting the sampling clock signal into the phase discriminator module; the phase discriminator module is used for acquiring the sampling clock signal and input data, comparing the phase of the sampling clock signal with that of the input data to obtain a phase error signal, and inputting the phase error signal into the loop filter module; the loop filter module is used for acquiring the phase error signal, filtering the phase error signal to obtain a phase error filtered signal, and inputting the phase error filtered signal into the gain equalization module; the gain equalization module is used for acquiring the phase error filtering signal, performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio, and inputting the phase-locked loop frequency division ratio into the phase-locked loop module; the phase-locked loop module is further configured to obtain the phase-locked loop frequency division ratio, and adjust the clock frequency based on the phase-locked loop frequency division ratio; compared with the prior art, the technical scheme of the invention can carry out finer processing and adjustment on the phase error signal by introducing the gain equalization module, so that the system is more stable when locking the clock frequency; the bandwidth requirement of the phase-locked loop system can be reduced to a certain extent by accurately adjusting the frequency division ratio of the phase-locked loop; the limit of the phase-locked loop bandwidth to the stability of the clock data recovery loop is eliminated.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a PLL-based clock data recovery circuit according to the present invention;
FIG. 2 is a schematic diagram illustrating an embodiment of a phase locked loop based clock data recovery method according to the present invention;
FIG. 3 is a schematic diagram of a clock data recovery circuit based on a phase locked loop according to another embodiment of the present invention
A schematic structural diagram of still another embodiment of a clock data recovery circuit based on a phase-locked loop according to this embodiment of the present embodiment is provided;
fig. 4 is a schematic diagram of a data processing manner of a phase detector module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a data processing mode of a loop filter module according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a data processing manner of a gain equalization module according to an embodiment of the present invention;
fig. 7 is a small signal model of a phase locked loop based clock data recovery circuit provided by the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a pll-based clock data recovery circuit provided in the present invention, and as shown in fig. 1, the circuit structure includes a pll module 101, a phase detector module 102, a loop filter module 103, and a gain equalization module 104, specifically as follows:
The phase-locked loop module 101 is configured to obtain a reference clock signal, generate a sampling clock signal based on a current clock frequency and the reference clock signal, and input the sampling clock signal to the phase detector module 102.
The phase detector module 102 is configured to obtain the sampling clock signal and input data, perform phase comparison on the sampling clock signal and the input data to obtain a phase error signal, and input the phase error signal to the loop filter module 103.
The loop filter module 103 is configured to obtain the phase error signal, filter the phase error signal to obtain a phase error filtered signal, and input the phase error filtered signal to the gain equalization module 104.
The gain equalization module 104 is configured to obtain the phase error filtered signal, perform feedforward compensation processing on the phase error filtered signal, obtain a pll frequency division ratio, and input the pll frequency division ratio into the pll module 101.
The phase-locked loop module 101 is further configured to obtain the phase-locked loop frequency division ratio, and adjust the clock frequency based on the phase-locked loop frequency division ratio.
In an embodiment, the output end of the phase-locked loop module 101 is connected to the input end of the phase detector module 102, the output end of the phase detector module 102 is connected to the input end of the loop filter module 103, the output end of the loop filter module 103 is connected to the input end of the gain equalization module 104, and the output end of the gain equalization module 104 is connected to the input end of the phase-locked loop module 101, as shown in fig. 3, fig. 3 is a schematic diagram of still another embodiment of a clock data recovery circuit based on a phase-locked loop; PD is the phase detector module 102 of the clock data recovery circuit, outputs the phase lead or lag result, loop filter module 103loop filter is the filter of the clock recovery loop, is formed by proportional path and integral path, loop filter module 103 filters according to the output result of phase detector module 102PD, outputs to gain equalization module 104EQ Boost, and then controls the frequency division ratio of PLL module 101PLL, finally achieves the purpose of adjusting the frequency and phase of the sampling clock.
In an embodiment, the phase-locked loop module 101 is configured to, when generating the sampling clock signal based on the current clock frequency and the reference clock signal, perform frequency multiplication processing on the reference clock signal to obtain a frequency-multiplied clock signal, and perform frequency division processing on the frequency-multiplied clock signal based on the current clock frequency to obtain the sampling clock signal.
Specifically, the pll module 101 first receives a reference clock signal from the outside, where the reference clock signal is usually a stable clock source and is used as a reference for adjusting clock frequency and phase of the pll, where the pll module 101 processes the reference clock signal according to the current clock frequency and the reference clock signal, and performs frequency multiplication and frequency division processing on the reference clock signal through circuits such as an internal frequency multiplier and a frequency divider, so as to generate a required sampling clock signal; thus, the generated sampling clock signal and the reference clock signal can be ensured to be synchronous, and the time sequence requirement of the system is met.
In an embodiment, the phase discriminator module 102 is configured to perform phase comparison on the sampling clock signal and the input data to obtain a phase error signal, and perform left exclusive-or processing on the sampling clock signal and the input data respectively to obtain a left exclusive-or signal, perform right exclusive-or processing on the sampling clock signal and the input data respectively to obtain a right exclusive-or signal, perform exclusive-or processing on the left exclusive-or signal and the right exclusive-or signal to obtain an exclusive-or signal, and obtain the phase error signal based on the exclusive-or signal and the left exclusive-or signal.
Specifically, the phase detector module 102 is an important component in a digital communication system, and is configured to detect a phase deviation of a signal, and by comparing a sampling clock signal with input data in phase, a phase error signal can be obtained, so as to instruct a phase-locked loop to adjust the phase and frequency of the sampling clock signal, so as to achieve synchronization.
Specifically, for sampling clock signals and input data at different moments, performing left exclusive-OR and right exclusive-OR respectively; the left exclusive-or refers to that two inputs are subjected to exclusive-or operation, the right exclusive-or refers to that one of the inputs is subjected to inversion and then is subjected to exclusive-or operation, and the obtained left exclusive-or signal and the right exclusive-or signal are subjected to exclusive-or processing to obtain a new exclusive-or signal; obtaining a phase error signal based on the exclusive-or signal and the left exclusive-or signal: finally, the exclusive-or signal and the left exclusive-or signal are processed to obtain a final phase error signal; the phase error signal is fed back to the pll module 101 for adjusting parameters inside the pll to synchronize the sampling clock signal with the phase of the input data; as shown in fig. 4, fig. 4 is a schematic diagram of a data processing manner of the phase detector module.
Preferably, the phase error signal includes a phase lead, a phase lag and a phase invariant.
In one embodiment, the loop filter module 103 includes a loop filter proportional path and a loop filter integral path.
In an embodiment, the loop filter module 103 is configured to perform a filtering process on the phase error signal to obtain a phase error filtered signal, and scale the phase error signal based on a proportional path gain through the proportional path of the loop filter to obtain a first filtered signal; integrating the phase error signal based on an integral path gain through the loop filter integral path to obtain a second filtered signal; finally, the loop filter module 103 performs a summation process on the first filtered signal and the second filtered signal to obtain a phase error filtered signal.
Specifically, the function of the loop filter proportional path in the loop filter module 103 is to adjust the output signal according to the set proportional path gain and the magnitude of the current phase error, so as to play a role of quick response; the function of the loop filter integrating path in the loop filter module 103 is to integrate the phase error, so as to eliminate static error or deviation in the system and stabilize the system; finally, the loop filter module 103 performs summation processing on the first filtering signal and the second filtering signal to obtain a phase error filtering signal; the rapid response and stability performance of the system can be balanced better by comprehensively utilizing the signals processed by the proportional path and the integral path, so that an ideal phase error filtering signal is obtained; as shown in fig. 5, fig. 5 is a schematic diagram of a data processing manner of the loop filter module, where a is a proportional path gain and b is an integral path gain.
In an embodiment, the gain equalization module 104 is configured to perform feedforward compensation processing on the phase error filtered signal to obtain a pll frequency division ratio, perform scaling processing on the first historical phase filtered signal based on a gain factor to obtain a second historical phase filtered signal, perform data summation processing on the second historical phase filtered signal and the phase error filtered signal to obtain an output filtered signal, and obtain the pll frequency division ratio based on the output filtered signal.
Specifically, when the phase-locked loop frequency division ratio is obtained based on the output filtering signal, the output filtering signal is obtained by filtering the phase error signal, and contains phase difference information between the clock signal and the reference clock signal, so that the deviation condition of the current clock signal can be reflected; by analyzing the characteristics of the output filtered signal, the deviation condition of the current clock signal relative to the reference clock signal can be obtained, so that the phase-locked loop frequency division ratio to be adjusted is determined.
Specifically, the last cycle refers to the last complete cycle in the periodic variation of the clock or the signal; the period may be the period of a clock or the period of a signal waveform, depending on the specific application scenario and system design.
In an embodiment, after the gain equalization module 104 outputs the pll frequency division ratio to the pll module 101, the pll module 101 may adjust an internal frequency division ratio parameter based on the received pll frequency division ratio, and by adjusting the frequency division ratio, accurate control of the output clock frequency may be achieved; the phase-locked loop module 101 can gradually eliminate the phase difference between the input clock and the reference clock, and finally realize the recovery and synchronization of the clock signals; when the frequency and phase of the output clock are consistent with those of the reference clock, the phase-locked loop module 101 reaches a steady state, and the clock recovery process is completed.
In one embodiment, as shown in fig. 6, fig. 6 is a schematic diagram of a data processing manner of the gain equalization module, and one implementation of the transfer function of the gain equalization module 104 is 1-az -1, that is, after the input data of the previous period is multiplied by the gain factor-a, the input data is summed with the phase error filtered signal currently input, and the filtered signal is output.
In one embodiment, since transfer function 1-az -1 describes a transfer function of a discrete-time system, where z -1 represents a discrete-time delay, the transfer function describes the way the system processes an input signal and generates an output signal.
In control system design, it is important to analyze the stability of the system; the S-domain is a frequency domain representation for analyzing a continuous time system, in which information of pole locations can be more conveniently used to judge the stability of the system, e.g., to evaluate the stability of the system in terms of pole locations of the transfer function; therefore, by converting Z-domain data into S-domain, conversion of a discrete-time system into an equivalent form of a continuous-time system can be achieved for frequency domain analysis.
Specifically, the conversion of the Z domain and the S domain is Z -1＝e―sT.
In an embodiment, as shown in fig. 7, fig. 7 is a small signal model of the pll-based clock data recovery circuit provided in this embodiment, where Kpd is a phase detector gain in the phase detector module 102PD, kp is a proportional path gain of a proportional path of the loop filter, ki is an integral path gain of an integral path of the loop filter, and 1/(1-z -1) is an expression of an integrator; the phase-locked loop module 101 is reduced to a digitally controlled oscillator DCO, with a first order approximation of bandwidthI.e. lpf in small signal model diagram, frequency to phase conversion to/>Wherein fref is the reference clock frequency of the phase-locked loop module 101, ω pll is the approximate pole of the first-order bandwidth of the phase-locked loop module 101; thus, the transfer function of the clock data recovery circuit without the gain equalization module 104 is:
In one embodiment, as can be seen from the transfer function, there are two poles at the origin, the values of Kp and Ki in the loop filter block 103 determine a zero point, and the first order approximation in the phase-locked loop block 101 A pole exists; for stability reasons, the bandwidth ω pll of the phase-locked loop module 101 must be greater than 10 times the bandwidth of the clock data recovery circuit, which limitation is severe.
Based on this, a gain equalization module 104 is additionally added on the path of the clock data recovery circuit for controlling the frequency division ratio of the phase-locked loop module, and a transfer function of the clock data recovery circuit is generated based on the phase-locked loop module 101, the phase detector module 102, the loop filter module 103 and the gain equalization module 104; wherein the transfer function is as follows:
Where loop_gain is loop gain, e is natural logarithm, n del is loop delay, S is a parameter of S domain, f ref is a reference clock frequency of the phase-locked loop, f cdr is an operating frequency of the clock data recovery circuit, kpd is phase discriminator gain, kp is a proportional path gain of a proportional path of the loop filter, ki is an integral path gain of an integral path of the loop filter, a is a gain factor, ω pll is a first-order bandwidth approximation pole of the phase-locked loop module 101.
By an additional factor in the gain equalization module 104 added to the transfer functionA left half-plane zero is generated where a is a gain factor that counteracts the bandwidth limit of the pll module 101 to the stability of the clock data recovery loop.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a pll-based clock data recovery method according to the present invention, as shown in fig. 2, the method is applicable to the pll-based clock data recovery circuit described in embodiment 1, and includes steps 201 to 205, specifically as follows:
Step 201: a reference clock signal is acquired and a sampling clock signal is generated based on a current clock frequency and the reference clock signal.
In one embodiment, generating the sampling clock signal based on the current clock frequency and the reference clock signal includes: and performing frequency multiplication processing on the reference clock signal based on the phase-locked loop module to obtain a frequency multiplication clock signal, and performing frequency division processing on the frequency multiplication clock signal based on the current clock frequency to obtain a sampling clock signal.
Step 202: and acquiring input data, and comparing the phase of the sampling clock signal with that of the input data to obtain a phase error signal.
In one embodiment, performing phase comparison on the sampling clock signal and the input data to obtain a phase error signal includes: and respectively carrying out left exclusive-or processing on the sampling clock signal and the input data based on a phase discriminator module to obtain a left exclusive-or signal, respectively carrying out right exclusive-or processing on the sampling clock signal and the input data to obtain a right exclusive-or signal, carrying out exclusive-or processing on the left exclusive-or signal and the right exclusive-or signal to obtain an exclusive-or signal, and obtaining a phase error signal based on the exclusive-or signal and the left exclusive-or signal.
Step 203: and filtering the phase error signal to obtain a phase error filtered signal.
In one embodiment, the filtering processing is performed on the phase error signal to obtain a phase error filtered signal, which includes: the received phase error signals are respectively input into a loop filter proportional path based on a loop filter module, so that the loop filter proportional path performs scaling processing on the phase error signals based on proportional path gain to obtain first filtering signals; respectively inputting the received phase error signals into an integral path of a loop filter, so that the integral path of the loop filter integrates the phase error signals based on the gain of the integral path to obtain a second filter signal; and summing the first filtering signal and the second filtering signal to obtain a phase error filtering signal.
Step 204: and performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio.
In one embodiment, performing feedforward compensation processing on the phase error filtered signal to obtain a pll frequency division ratio, including: and obtaining a first historical phase filtering signal of the previous period based on the gain equalization module, performing scaling processing on the first historical phase filtering signal based on a gain factor to obtain a second historical phase filtering signal, performing data summation processing on the second historical phase filtering signal and the phase error filtering signal to obtain an output filtering signal, and obtaining a phase-locked loop frequency division ratio based on the output filtering signal.
Step 205: the clock frequency is adjusted based on the phase-locked loop divide ratio.
In an embodiment, after the gain equalization module outputs the pll frequency division ratio to the pll module, the pll module may adjust an internal frequency division ratio parameter based on the received pll frequency division ratio, and by adjusting the frequency division ratio, accurate control of the output clock frequency may be achieved.
The clock data recovery method based on the phase-locked loop in this embodiment is further provided with a transfer function based on clock data recovery, and based on the transfer function, the gain in the loop is adjusted, that is, a zero point is added to compensate the pole of the phase-locked loop module, so that the performance and stability of the system can be optimized, the frequency response characteristic of the system can be improved, and the requirement on the bandwidth of the phase-locked loop module can be reduced.
It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding process in the foregoing circuit embodiment for the specific working process of the above-described method, which is not described in detail herein.
In summary, the clock data recovery circuit and the clock data recovery method based on the phase locked loop provided by the invention comprise the following steps: the phase-locked loop module, the phase discriminator module, the loop filter module and the gain equalization module; the phase-locked loop module is used for generating a sampling clock signal based on the current clock frequency and the acquired reference clock signal; the phase discriminator module is used for comparing the phase of the acquired sampling clock signal with the phase of the input data to obtain a phase error signal; the loop filter module is used for carrying out filtering processing on the obtained phase error signal to obtain a phase error filtering signal; the gain equalization module is used for performing feedforward compensation processing on the obtained phase error filtering signal to obtain a phase-locked loop frequency division ratio; the phase-locked loop module is also used for adjusting the clock frequency based on the acquired phase-locked loop frequency division ratio; compared with the prior art, the technical scheme of the invention eliminates the limitation of the phase-locked loop bandwidth on the stability of the clock data recovery loop by adding the gain equalization module.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.

Claims (10)

1. A phase locked loop based clock data recovery circuit comprising: the phase-locked loop module, the phase discriminator module, the loop filter module and the gain equalization module;
the phase-locked loop module is used for acquiring a reference clock signal, generating a sampling clock signal based on the current clock frequency and the reference clock signal, and inputting the sampling clock signal into the phase discriminator module;
The phase discriminator module is used for acquiring the sampling clock signal and input data, comparing the phase of the sampling clock signal with that of the input data to obtain a phase error signal, and inputting the phase error signal into the loop filter module;
The loop filter module is used for acquiring the phase error signal, filtering the phase error signal to obtain a phase error filtered signal, and inputting the phase error filtered signal into the gain equalization module;
the gain equalization module is used for acquiring the phase error filtering signal, performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio, and inputting the phase-locked loop frequency division ratio into the phase-locked loop module;
The phase-locked loop module is further configured to obtain the phase-locked loop frequency division ratio, and adjust the clock frequency based on the phase-locked loop frequency division ratio.
2. A phase locked loop based clock data recovery circuit as claimed in claim 1, comprising:
the output end of the phase-locked loop module is connected with the input end of the phase discriminator module, the output end of the phase discriminator module is connected with the input end of the loop filter module, the output end of the loop filter module is connected with the input end of the gain equalization module, and the output end of the gain equalization module is connected with the input end of the phase-locked loop module.
3. The phase locked loop based clock data recovery circuit of claim 1, wherein the loop filter module is configured to filter the phase error signal to obtain a phase error filtered signal, and comprises:
the loop filter module comprises a loop filter proportional path and a loop filter integral path;
the loop filter proportional path is used for carrying out scaling processing on the phase error signal based on proportional path gain to obtain a first filtering signal;
The loop filter integrating path is used for integrating the phase error signal based on the gain of the integrating path to obtain a second filtering signal;
the loop filter module is used for summing the first filtering signal and the second filtering signal to obtain a phase error filtering signal.
4. The phase-locked loop based clock data recovery circuit of claim 1, wherein the gain equalization module is configured to perform feedforward compensation processing on the phase error filtered signal to obtain a phase-locked loop frequency division ratio, and comprises:
The gain equalization module is used for obtaining a first historical phase filtering signal of the previous period, performing scaling processing on the first historical phase filtering signal based on a gain factor to obtain a second historical phase filtering signal, performing data summation processing on the second historical phase filtering signal and the phase error filtering signal to obtain an output filtering signal, and obtaining a phase-locked loop frequency division ratio based on the output filtering signal.
5. The phase locked loop based clock data recovery circuit of claim 1, wherein the phase detector module for phase comparing the sampling clock signal with the input data to obtain a phase error signal comprises:
The phase discriminator module is used for performing left exclusive-or processing on the sampling clock signal and the input data respectively to obtain a left exclusive-or signal, and performing right exclusive-or processing on the sampling clock signal and the input data respectively to obtain a right exclusive-or signal; and performing exclusive-or processing on the left exclusive-or signal and the right exclusive-or signal to obtain an exclusive-or signal, and obtaining a phase error signal based on the exclusive-or signal and the left exclusive-or signal.
6. The phase-locked loop based clock data recovery circuit of claim 1, wherein the phase-locked loop module for generating a sampling clock signal based on a current clock frequency and the reference clock signal comprises:
The phase-locked loop module is used for carrying out frequency multiplication processing on the reference clock signal to obtain a frequency multiplication clock signal, and carrying out frequency division processing on the frequency multiplication clock signal based on the current clock frequency to obtain a sampling clock signal.
7. A phase locked loop based clock data recovery circuit as claimed in claim 1, further comprising:
Generating a transfer function of a clock data recovery circuit based on the phase-locked loop module, the phase detector module, the loop filter module, and the gain equalization module; wherein the transfer function is as follows:
In the formula, loop_gain is loop gain, e is natural logarithm, n del is loop delay, S is a parameter of an S domain, f ref is a reference clock frequency of a phase-locked loop, f cdr is an operating frequency of a clock data recovery circuit, kpd is phase discriminator gain, kp is proportional path gain of a proportional path of a loop filter, ki is integral path gain of an integral path of the loop filter, a is a gain factor, and omega pll is a first-order bandwidth approximate pole of a phase-locked loop module.
8. A phase locked loop based clock data recovery method, suitable for use in the phase locked loop based clock data recovery circuit of any one of claims 1-7, comprising:
acquiring a reference clock signal, and generating a sampling clock signal based on a current clock frequency and the reference clock signal;
Acquiring input data, and performing phase comparison on the sampling clock signal and the input data to obtain a phase error signal;
filtering the phase error signal to obtain a phase error filtered signal;
performing feedforward compensation processing on the phase error filtering signal to obtain a phase-locked loop frequency division ratio;
The clock frequency is adjusted based on the phase-locked loop divide ratio.
9. The phase-locked loop based clock data recovery method of claim 8, wherein filtering the phase error signal to obtain a phase error filtered signal comprises:
Respectively inputting the received phase error signals into a loop filter proportional path, so that the loop filter proportional path performs scaling processing on the phase error signals based on proportional path gain to obtain a first filtering signal;
Respectively inputting the received phase error signals into an integral path of a loop filter, so that the integral path of the loop filter integrates the phase error signals based on the gain of the integral path to obtain a second filter signal;
and summing the first filtering signal and the second filtering signal to obtain a phase error filtering signal.
10. The phase-locked loop based clock data recovery method of claim 8, wherein performing feed-forward compensation processing on the phase error filtered signal to obtain a phase-locked loop frequency division ratio comprises:
And obtaining a first historical phase filtering signal of the previous period, performing scaling processing on the first historical phase filtering signal based on a gain factor to obtain a second historical phase filtering signal, performing data summation processing on the second historical phase filtering signal and the phase error filtering signal to obtain an output filtering signal, and obtaining a phase-locked loop frequency division ratio based on the output filtering signal.
CN202410274018.4A 2024-03-11 2024-03-11 Clock data recovery circuit and clock data recovery method based on phase-locked loop Pending CN118199621A (en)

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