KR102525786B1 - PLL including Adaptive loop bandwidth gain booster - Google Patents

Abstract

The present invention relates to a phase-locked loop having an adaptive booster of loop bandwidth gain, and more particularly, a phase-locked loop that adjusts a loop bandwidth by comparing a phase edge of a reference frequency with a phase edge of an output frequency. It is about the loop (PLL). The present invention compares the phase edge of the reference frequency with the phase edge obtained by dividing the output frequency by N, and outputs an error value (TDC: Time to Digital Converter); a digital loop filter (DLF) for outputting a control value for adjusting the frequency difference by receiving the error value and performing low-pass filtering; and a digital controlled oscillator (DC0) for controlling the output frequency by receiving the control value and controlling the output frequency of the PMOS array. .

Description

Phase locked loop with adaptive loop bandwidth gain booster {PLL including Adaptive loop bandwidth gain booster}

The present invention relates to a phase-locked loop having an adaptive booster of loop bandwidth gain, and more particularly, a phase-locked loop (PLL) that adjusts a loop bandwidth by comparing a phase edge of a reference frequency with a phase edge of an output frequency. It is about.

In general, in a digital system, a phase-locked loop device (PLL) is widely used to generate a high-frequency operation clock using a low-frequency input clock signal. A PLL (Phase Locked Loop) refers to a device that generates a required frequency by synchronizing the phase of the output frequency to the reference frequency through phase comparison between the reference frequency and the output frequency. At this time, in the negative feedback structure of the PLL, various noise components are added or subtracted to create frequency components other than the original signal called phase noise. This phase noise appears as a phase fluctuation called jitter in time.

The operating frequency of high-performance digital systems is increasing day by day, and accordingly, the design of a phase-locked loop device with minimum jitter and fast clock recovery time against external noise is essential. is being given importance. In order to have minimum jitter and fast clock recovery time against external noise, the loop bandwidth should be designed as large as possible. However, when the loop bandwidth is set large, a stability problem is caused.

In this regard, Korean Patent Laid-open Publication No. 2002-0042032 discloses a charge pump circuit-related technology having a fixed pump gain among phase-locked loop circuits, and a phase/frequency detection circuit-related technology of a phase-locked loop circuit. .

However, the content of the conventional phase-locked loop has a problem in that accurate and stable synchronization between the input clock and the operating clock cannot be guaranteed. Compared to the analog PLL, the noise characteristics are poor and there are many areas to be improved, so a lot of research on the digital PLL is required. It is necessary.

Korean Patent Publication No. 2002-0042032

The present invention is a type of adaptive bandwidth phase-locked loop device (Adaptive Bandwidth PLL) to solve the above-mentioned problems, and an adaptive type of loop bandwidth gain that monitors the output value of BBPD in real time and adjusts the digital gain according to the current situation. It is an object to provide a phase locked loop with a booster.

In order to achieve the above object, the present invention compares the phase edge of an output frequency output in real time with the phase edge of a reference frequency to adjust the frequency difference. In a phase-locked loop having an adaptive booster of loop bandwidth gain, the a time-to-digital converter (TDC) for outputting an error value by comparing a phase edge of a reference frequency with a phase edge obtained by dividing the output frequency by N; a digital loop filter (DLF) for outputting a control value for adjusting the frequency difference by receiving the error value and performing low-pass filtering; and a digital controlled oscillator (DC0) for controlling the output frequency by receiving the control value and controlling the output frequency of the PMOS array. .

Preferably, the time digital converter (TDC) may further include a bang bang TDC (BBTDC) that outputs a positive error value when the phase edge of the output frequency is ahead of the reference frequency and calculates a negative error value when it lags behind the reference frequency. can

Preferably, the digital loop filter may further include a loop bandwidth boost (LBW boost) for adjusting the loop bandwidth gain by receiving the error value.

Preferably, the loop bandwidth boost (LBW) increases a digital gain and increases a loop bandwidth when the phase error is large at the time the loop starts, and increases the bandwidth gain when the phase error is small at the time the loop is completed. You can reduce the loop bandwidth by reducing the (digital gain).

Preferably, the adaptive booster adjusts the digital gain from the start of the loop to the point of completion to adjust the loop bandwidth adaptively according to operating environments of the reference frequency and the output frequency. can change

[ It is characterized in that it satisfies the formula of output frequency = reference frequency * N].

In addition, the present invention may also include a computer-readable recording medium on which a program for implementing a method executed by the above device as a program is recorded so that the above-described embodiments can be implemented.

According to the present invention having the configuration as described above, there is an advantage overcoming the limitations of the digital PLL that is behind in speed compared to the analog PLL.

In addition, the present invention has an advantage of improving performance degradation due to quantization noise generated in a digital circuit and adaptively changing the loop bandwidth according to operation.

In addition, the present invention provides an important indicator for research and development of digital frequency synthesizers, and the content of the conventional phase-locked loop provides an adaptive bandwidth phase-locked loop device that guarantees accurate and stable synchronization between an input clock and an operating clock. There is an advantage.

1 shows a block diagram of the entire digital PLL based on a conventional time to digital converter (TDC).
2 shows a detailed block diagram of a conventional time to digital converter (TDC).
3 shows an overall block diagram of a digital PLL based on a conventional Bang Bang phase detector.
4 shows a detailed block diagram of a conventional Bang Bang Phase Detector (BBPD).
5 shows a block diagram of a BBTDC Digital PLL including an adaptive booster of loop bandwidth gain according to an embodiment of the present invention.
6 shows a detailed block diagram of an adaptive booster of loop bandwidth gain according to an embodiment of the present invention.
FIG. 7 shows an operating principle (left) and a flowchart (right) of the adaptive booster of FIG. 7 according to the present invention.

Hereinafter, terms used in this specification will be briefly described, and the configuration and operation of a preferred embodiment of the present invention will be described in detail as specific contents for carrying out the present invention.

The terms used in this specification have been selected from general terms that are currently widely used as much as possible while considering the functions in the present invention, but these may vary depending on the intention of a person skilled in the art, precedent, or the emergence of new technologies. In addition, in a specific case, there is also a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the invention. Therefore, the term used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, not simply the name of the term.

When it is said that a certain part "includes" a certain component throughout the specification, it means that it may further include other components without excluding other components unless otherwise stated. In addition, terms such as "...unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software or a combination of hardware and software. . In addition, when a part is said to be "connected" to another part throughout the specification, this includes not only the case of being "directly connected" but also the case of being connected "with another component in between".

Hereinafter, embodiments of the present invention will be described in detail so that those skilled in the art can easily practice with reference to the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

In the present invention, general English names are mixed with Korean names, and in the case of each term, Time to Digital Converter (TDC), Digital Loop Filter (DLF), Digital Controlled Oscillator (DC0) ), and can be used in the form of a loop bandwidth boost (LBW boost).

1 shows a block diagram of the entire digital PLL based on a conventional time to digital converter (TDC).

Referring to FIG. 1, a time to digital converter (TDC) compares a phase edge of a reference frequency with a phase edge of an N-divided output frequency and outputs an error value. DLF (Digital loop filter) is a low pass filter and outputs a control value that adjusts the frequency of the DCO by filtering the input error value.

2 shows a detailed block diagram of a conventional time to digital converter (TDC).

Referring to FIG. 2, after detecting the phase edge of the divided output frequency with an inverter chain, sampling is performed as a reference frequency through DFF. At this time, the resolution of the digital LSB is one inverter delay time.

의 수식을 통해 TDC resolution (Tres)가 크면 In-band phase noise가 증가하여 PLL의 성능이 나빠진다. 이 경우, Loop bandwidth가 과도하게 커 Loop gain 주변에서의 발진을 유발하는 noise peaking이 발생할 수 있는 Limit cycle oscillation 문제가 발생할 수 있다.here,

Through the formula of , if the TDC resolution (Tres) is large, the in-band phase noise increases and the performance of the PLL deteriorates. In this case, a limit cycle oscillation problem may occur, which may cause noise peaking that causes oscillation around the loop gain due to excessively large loop bandwidth.

3 shows an overall block diagram of a digital PLL based on a conventional Bang Bang phase detector.

Referring to FIG. 3, the BBPD compares the phase edge of the reference frequency with the phase edge of the N-divided output frequency and outputs an error value. Outputs a control value that adjusts the frequency of

4 shows a detailed block diagram of a conventional Bang Bang Phase Detector (BBPD).

Referring to Fig. 4, it is a detailed block diagram of BBPD. Unlike the traditional TDC-based Digital PLL, the input and sampling frequency of the phase detector are metastable, such as Sense amplifier D flip-flop, so that a value of 1 or -1 is output without meaning of resolution.

This operation is called Bang bang. As shown in the timing diagram, -1 is output when the phase edge of the reference frequency precedes the phase edge of the output frequency, and 1 is output when the phase edge of the reference frequency lags behind the phase edge of the output frequency. outputs

의 수식을 통해 Phase detector의 resolution(Tres)는 Phase noise에 전혀 영향을 미치지 않음을 알 수 있다. 그러나 BBPD는 한 번 루프가 돌 때 1 또는 -1의 값만 출력하게 되므로 Loop의 속도가 느려 Slew rate limitation 문제가 생길 수 있다. 또한, Loop bandwidth가 낮은 주파수 대역폭에 있어, Out-band에 spur가 생기고 phase noise가 나빠질 수 있다.In the case of Figure 4,

Through the formula of , it can be seen that the resolution (Tres) of the phase detector does not affect the phase noise at all. However, since BBPD outputs only 1 or -1 when the loop runs once, the loop speed is slow, which can cause slew rate limitation. Also, in the frequency bandwidth where the loop bandwidth is low, spurs may occur in the out-band and phase noise may deteriorate.

The present invention is to solve the above-described problems of FIGS. 1 to 4, and the present invention will be described below with reference to FIGS. 5 to 7.

5 shows a block diagram of a BBTDC Digital PLL including an adaptive booster of loop bandwidth gain according to an embodiment of the present invention.

In the case of the present invention, a phase-locked loop having an adaptive booster of loop bandwidth gain that adjusts a frequency difference by comparing a phase edge of an output frequency outputted in real time with a phase edge of a reference frequency is provided.

The present invention compares the phase edge of the reference frequency with the phase edge obtained by dividing the output frequency by N, and outputs an error value (TDC: Time to Digital Converter); a digital loop filter (DLF) for outputting a control value for adjusting the frequency difference by receiving the error value and performing low-pass filtering; and a digital controlled oscillator (DC0) for controlling the output frequency by receiving the control value and controlling the current of the PMOS array.

Referring to FIG. 5, an adaptive loop bandwidth booster is included. The BBTDC compares the phase edge of the reference frequency and the phase edge of the output frequency, and if the phase edge of the output frequency leads, a positive error value and a lag If it is, it outputs a negative error value.

The time digital converter TDC may further include a bang bang TDC (BBTDC) outputting a positive error value when the phase edge of the output frequency leads ahead of the reference frequency and calculating a negative error value when it lags behind the reference frequency. .

In addition, the digital loop filter may further include a loop bandwidth boost (LBW boost) for adjusting the loop bandwidth gain by receiving the error value.

The loop bandwidth boost (LBW boost) increases the bandwidth gain (digital gain) and increases the loop bandwidth when the phase error is large at the time the loop starts, and when the phase error is small at the time the loop is completed, the bandwidth gain ( It is characterized by reducing the loop bandwidth by reducing the digital gain).

The LBW booster receives these output values and adjusts the loop bandwidth by multiplying the digital gain according to the current loop situation. The adjusted value is output as a low pass filtered control value through a proportional path with a gain of α and an integral path with a gain of β. This control value controls the frequency of the DCO to align the phase edge of the output frequency with the phase edge of the reference frequency.

DCO (Digital Controlled Oscillator) controls the frequency by adjusting the current of the PMOS array through digital control. Since the reference frequency and output frequency usually differ by more than 50 to 100 times, the N divider performs frequency division to adjust the output frequency to be similar to the reference frequency. Therefore, when the PLL is phase locked, [output frequency = reference frequency * N].

6 shows a detailed block diagram of an adaptive booster of loop bandwidth gain according to an embodiment of the present invention.

Referring to Figure 6, the output of the BBTDC goes into the input of the adaptive gain boost algorithm. The output of BBTDC is phase information, which is differentiated and converted into frequency information, and the current and past information are compared with the changed frequency information to output E _DIFF .

This value adjusts the control value that controls the accumulator's adaptive gain barrel shifter. This control value is G _ADP , and according to this value, the gain of the barrel shifter can be changed from 2 ^-3 to 2 ⁴ . The changed gain is multiplied by the output of BBPD and input to DLF, and after low pass filtering, DCO can be controlled.

FIG. 7 shows an operating principle (left) and a flowchart (right) of the adaptive booster of FIG. 7 according to the present invention.

The adaptive booster adjusts the bandwidth gain (digital gain) from the start of the loop to the point of completion to adaptively change the loop bandwidth according to the operating environment of the reference frequency and the output frequency. characterized by

Referring to FIG. 7, as can be seen from the Gain adaptation during Startup figure, E _DIF0 is created by differentiating the past output value X[n] and the current output value X[n+1] of BBTDC. This is frequency information.

After obtaining the frequency information in real time in this way, comparing the past frequency information E _DIF0 and E _DIF1 , if the frequency difference is large, G _ADP can be increased and if the frequency difference is small, G _ADP can be decreased. As you can see, when the PLL is locked, G _ADP is fixed.

According to the present invention, it is possible to overcome the limitations of the digital PLL, which is behind in speed compared to the analog PLL, to improve the performance degradation due to quantization noise generated in the digital circuit, and to adaptively change the loop bandwidth according to the operation. there is

Although the present invention has been described in detail through representative embodiments, those skilled in the art will understand that various modifications are possible to the above-described embodiments without departing from the scope of the present invention. will be. Therefore, the scope of the present invention should not be limited to the described embodiments and should not be defined, and should be defined by all changes or modifications derived from the claims and equivalent concepts as well as the claims to be described later.

Claims (7)

In a phase-locked loop having an adaptive booster of loop bandwidth gain that adjusts a frequency difference by comparing a phase edge of an output frequency output in real time with a phase edge of a reference frequency,
a Time to Digital Converter (TDC) for outputting an error value by comparing a phase edge of the reference frequency with a phase edge obtained by dividing the output frequency by N;
a digital loop filter (DLF) for outputting a control value for adjusting the frequency difference by receiving the error value and performing low-pass filtering; and
A digital controlled oscillator (DC0) for controlling the output frequency by receiving the control value and controlling the current of the PMOS array;
The time digital converter (TDC),
A Bang Bang TDC (BBTDC) outputting a positive error value when the phase edge of the output frequency leads the reference frequency and calculating a negative error value when it lags behind the reference frequency;
The digital loop filter (DLF),
A loop bandwidth boost for adjusting the loop bandwidth gain by receiving the error value,
The loop bandwidth boost,
Differentiates the output of the BBTDC, which is phase information, and changes it to frequency information, compares current information and past information in the frequency information to output an E _DIFF value, and takes the E _DIFF value as G _ADP , a barrel shifter (Adaptive gain barrel shifter) to change the bandwidth gain (digital gain) from 2 ^-3 to 2 ⁴ ,
The loop bandwidth boost,
The loop bandwidth is adaptively changed according to the operating environment of the reference frequency and the output frequency by adjusting the digital gain from the start of the loop to the point of completion, but the adjusted gain of α Outputting the control value low pass filtered through a proportional path with and an integral path with a gain of β,
The control value controls the frequency of the DCO to align the phase edge of the output frequency with the phase edge of the reference frequency;
Further comprising an N divider for adjusting the output frequency of the digitally controlled oscillator to a bandwidth of the reference frequency,
When the N divider performs a phase loop,
A phase-locked loop with an adaptive booster of loop bandwidth gain, which satisfies the formula [output frequency = reference frequency * N].
delete delete According to claim 1,
The loop bandwidth boost (LBW),
When the phase error is large at the start of the loop, increase the digital gain and increase the loop bandwidth,
A phase-locked loop having an adaptive booster of loop bandwidth gain, characterized in that to reduce the loop bandwidth by reducing the bandwidth gain (digital gain) when the phase error is small at the time the loop is completed.
delete delete delete

Images