CN101615905A - Phase-locked loop with power scaling prescaler and multimode bandwidth loop filter - Google Patents
Phase-locked loop with power scaling prescaler and multimode bandwidth loop filter Download PDFInfo
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Abstract
The invention discloses a kind of phase-locked loop with power scaling prescaler and multimode bandwidth loop filter, the pre-divider of this phase-locked loop is made of a plurality of frequency divider cascades, the transistor size difference of frequency dividers at different levels, therefore the electric current of frequency dividers at different levels is directly proportional with the frequency of frequency dividers at different levels, thereby realizes the optimised power consumption of pre-divider; The loop filter of this phase-locked loop adopts the loop filter of different bandwidth to carry out the Bandwidth Dynamic switching, this phase-locked loop is used for the half-duplex radio frequency transceiver, when transceiver is receiving mode, phase-locked loop is arranged on low bandwidth model, reduce the in-band noise of phase-locked loop and spuious, improve the adjacent rank channel selectivity of receiver; When transceiver was emission mode, phase-locked loop was arranged on middle bandwidth mode, realized the normal transmission of frequcny modulation data, and reduced the Error Vector Magnitude of transmitter, improved adjacent rank channel rejection ratio; When phase-locked loop is in when setting up state, transceiver is arranged on high bandwidth mode, accelerates phase-locked loop and sets up speed.
Description
Technical field
The present invention relates to the PHASE-LOCKED LOOP PLL TECHNIQUE field, particularly a kind of phase-locked loop with power scaling prescaler and multimode bandwidth loop filter, this phase-locked loop is particularly useful for the half-duplex radio frequency transceiver.
Background technology
In charge pump phase lock loop commonly used at present, pre-divider is because reason such as operating frequency height, complex structure, parasitic effects be big, its power consumption has occupied the overwhelming majority of whole phase-locked loop power consumption usually, so it is most important for the power consumption that reduces whole phase-locked loop to reduce the power consumption of pre-divider.In addition, the bandwidth of phase-locked loop intermediate ring road filter has determined the settling time and the response speed of phase-locked loop, and influences the noise profile of phase-locked loop and spuious.
For pre-divider, the method for traditional reduction power consumption all is to improve on the local circuit of pre-divider, reduces internal node, reduces parasitism, thereby reduce power consumption.For example, " A 13.5-mW 5-GHz frequency synthesizer withdynamic-logic frequency divider " literary grace is with the circuit design of true single phase clock in the 378th～383 page of " IEEE Journal of Solid-State Circuits " the 39th the 2nd phase of volume of publishing in 2004, when but true single phase clock circuit makes the floating sky of output node at clock, be subject to the influence of other signal coupling.Again for example, " A 21-GHz 8-Modulus Prescaler and a20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS " literary composition reduces parasitism by reducing transistorized size in the 1240th～1249 page of " IEEE Journal of Solid-State Circuits " the 42nd the 6th phase of volume of publishing in 2007, but its driving force also weakens when transistor size reduces, can not guarantee the circuit operate as normal.
For the loop filter of phase-locked loop, guaranteeing have under the situation of enough phase margins, the bandwidth of filter is wide more, and the settling time of phase-locked loop is short more, but phase noise and spuious also big more in the band of phase-locked loop; The bandwidth of filter is low more, phase noise and spuious more little in the band of phase-locked loop, but the settling time of phase-locked loop is long more.The loop bandwidth of traditional phase-locked loop is a fixed value, and of short duration settling time and little in-band noise and spuious can't get both." A 1.8-GHz Spur-Cancelled Fractional-N FrequencySynthesizer With LMS-Based DAC Gain Calibration " literary composition is provided with the bandwidth of loop filter to such an extent that compare broad in the 2842nd～2851 page of " IEEE Journal of Solid-State Circuits " the 42nd the 12nd phase of volume of publishing in 2006, to obtain to set up faster speed, adopt spuious cancellation technology or noise cancellation technique simultaneously, but this technology increases complexity, power consumption and the chip area of circuit greatly.Phase-locked loop is usually used in the half-duplex radio frequency transceiver, and under receiving mode, phase-locked loop generally is used to provide local oscillation signal, the phase noise of pll output signal and the spuious adjacent rank channel selectivity that has directly determined receiver; And under emission mode, transmitter for frequency shift keying or Gaussian Frequency Shift Keying, can realize the signal emission by the mode of phase-locked loop direct frequency modulation, but the FM signal rate of emission must be less than the loop bandwidth of phase-locked loop, and " A 27-mW CMOS fractional-N synthesizer using digitalcompensation or 2.5-Mb/s GFSK modulation " literary composition has draped over one's shoulders leak this technology in the 2048th～2060 page of " IEEE Journal of Solid-State Circuits " the 32nd the 12nd phase of volume of publishing in 1997.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of phase-locked loop with power scaling prescaler and multimode bandwidth loop filter, can not effectively reduce pre-divider power consumption and the fixing defective of loop filter bandwidth pattern in the prior art to overcome.
For solving the problems of the technologies described above, technical scheme of the present invention is for providing a kind of phase-locked loop with power scaling prescaler and multimode bandwidth loop filter, and this phase-locked loop comprises:
Pre-divider, this pre-divider comprise two-stage frequency divider at least, frequency divider cascades at different levels, and transistor arrangement difference in the frequency dividers at different levels is used for the power consumption convergent-divergent of pre-divider;
Loop filter, this loop filter comprises the loop filter of at least three different bandwidths, is used for Bandwidth Dynamic and switches;
Voltage controlled oscillator, the output of the input linkloop filter of this voltage controlled oscillator, the output of this voltage controlled oscillator connects an input of pre-divider;
The low frequency frequency divider, an input of this described low frequency frequency divider connects the output of pre-divider;
Modulator receives the frequency dividing ratio control word, and the output of this modulator connects another input of pre-divider and another input of low frequency frequency divider;
Phase frequency detector, the output of low frequency frequency divider and phase-locked loop reference frequency source are connected two inputs of this phase frequency detector respectively;
Charge pump, the input of this charge pump connects the output of phase frequency detector, the input of this electric charge delivery side of pump linkloop filter.
Wherein, transistor arrangement in the described frequency divider at different levels, be specially: the transistorized channel length of same position is identical in the frequency dividers at different levels, in the back one-level frequency divider transistorized width be in the previous stage frequency divider same position transistor width divided by the frequency dividing ratio of previous stage frequency divider, the electric current of back one-level frequency divider is the frequency dividing ratio of the electric current of previous stage frequency divider divided by the previous stage frequency divider, and the frequency input signal of back one-level frequency divider is the frequency dividing ratio of the frequency input signal of previous stage frequency divider divided by the previous stage frequency divider.
Wherein, described pre-divider specifically comprises:
The above frequency divider of two-stage, frequency divider cascades at different levels, the output of previous stage frequency divider connects the input of back one-level frequency divider, and the input of first order frequency divider is the input of pre-divider;
Phase selector, the output of the afterbody frequency divider of the above frequency divider of described two-stage connects the input of described phase selector;
The Fractional-N frequency device, the output of phase selector connects the input of Fractional-N frequency device, and the output of Fractional-N frequency device is the output of pre-divider;
NAND gate, the output of Fractional-N frequency device and pattern control word are connected two inputs of NAND gate respectively;
The phase control module, the output of NAND gate connects the input of phase control module, and the output of phase control module connects the control word input of phase selector.
Wherein, the frequency divider in the described pre-divider can adopt 2 frequency dividers, and 2 frequency dividers specifically comprise:
Two PMOS pipes, the source electrode of two PMOS pipes connects the power supply positive voltage, the grounded-grid of two PMOS pipes, the drain electrode of a PMOS pipe connects first output port, and the drain electrode of the 2nd PMOS pipe connects second output port;
Six NMOS pipes, the grid of the one NMOS pipe connects first signal input part, the grid of the 2nd NMOS pipe connects the secondary signal input, the drain electrode of the one NMOS pipe connects first output port, the drain electrode of the 2nd NMOS pipe connects second output port, after linking to each other, the source electrode of the source electrode of the one NMOS pipe and the 2nd NMOS pipe is connected the drain electrode of the 3rd NMOS pipe, the grid of the 3rd NMOS pipe connects an input end of clock, the source ground of the 3rd NMOS pipe, the drain electrode of the 4th NMOS pipe connects first output port, the drain electrode of the 5th NMOS pipe connects second output port, the drain electrode of the 4th NMOS pipe connects the grid of the 5th NMOS pipe, the grid of the 4th NMOS pipe connects the drain electrode of the 5th NMOS pipe, after linking to each other, the source electrode of the source electrode of the 4th NMOS pipe and the 5th NMOS pipe is connected the drain electrode of the 6th NMOS pipe, the grid of the 6th NMOS pipe connects another input end of clock, the source ground of the 6th NMOS pipe.
Wherein, described loop filtering implement body comprises:
High bandwidth loop filter, middle bandwidth loop filter, low bandwidth loop filter and two signal path selectors;
The control end connecting band wide mode control word of two signal path selectors, the first signal path selector has an input and three outputs, the input of the first signal path selector connects the electric charge delivery side of pump, first output of the first signal path selector connects the input of high bandwidth loop filter, the input of bandwidth loop filter during second output of the first signal path selector connects, the 3rd output of the first signal path selector connects the input of low bandwidth loop filter, secondary signal path selector has three inputs and an output, the first input end of secondary signal path selector connects the output of high bandwidth loop filter, the output of bandwidth loop filter during second input of secondary signal path selector connects, the 3rd input of secondary signal path selector connects the output of low bandwidth loop filter, and the output of secondary signal path selector connects the input of voltage controlled oscillator.
Wherein, described Bandwidth Dynamic switching is specially:
The bandwidth of loop filter is switched with the difference of the mode of operation of half-duplex radio frequency transceiver, when transceiver is receiving mode, loop filter is set to low bandwidth model, reduces the in-band noise of loop filter and spuious, improves the adjacent rank channel selectivity of receiver; When transceiver was emission mode, loop filter was set to middle bandwidth mode, realized the normal transmission of FM signal, and reduced the Error Vector Magnitude of transmitter, improved adjacent rank channel rejection ratio; When phase-locked loop is in when setting up state, loop filter is arranged on high bandwidth mode, accelerates phase-locked loop and sets up speed.
Compared with prior art, technical scheme of the present invention has following advantage: adopt power scaling prescaler can effectively reduce the power consumption of pre-frequency division, thereby reduce the power consumption of phase-locked loop, adopt the multimode bandwidth loop filter, overcome the defective of fixed-bandwidth pattern, satisfied the index request of half-duplex radio frequency transceiver under the different operating state.
Description of drawings
Fig. 1 is the phase-locked loop circuit block diagram with power scaling prescaler and multimode loop filter of the embodiment of the invention;
Fig. 2 is the power scaling prescaler circuit block diagram of the embodiment of the invention;
Fig. 3 is 2 divider unit circuit diagrams of the embodiment of the invention;
Fig. 4 is the multimode bandwidth loop filter circuit figure of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
The phase-locked loop circuit block diagram with power scaling prescaler and multimode loop filter of the embodiment of the invention as shown in Figure 1; the output of phase frequency detector connects the input of charge pump; the electric charge delivery side of pump connects the input of multimode bandwidth loop filter; the output of multimode bandwidth loop filter connects the input of voltage controlled oscillator; the output of voltage controlled oscillator connects an input of power scaling prescaler; the output of power scaling prescaler connects an input of low frequency frequency divider; the frequency dividing ratio control word is input to the input of sigma-delta modulator; the output of sigma-delta modulator connects another input of power scaling prescaler and another input of low frequency frequency divider, and the output of low frequency frequency divider and reference clock are connected two inputs of phase frequency detector respectively.
The phase-locked loop of present embodiment adopts power scaling prescaler can effectively reduce the power consumption of pre-frequency division, thereby reduce the power consumption of phase-locked loop, adopt the multimode bandwidth loop filter, overcome the defective of fixed-bandwidth pattern, satisfy the index request of half-duplex radio frequency transceiver under the different operating state.
The loop filter of present embodiment phase-locked loop has three kinds of bandwidth mode: for the half-duplex radio frequency transceiver, transceiver is under receiving mode, loop filter is set to low bandwidth model, reduces the in-band noise of phase-locked loop and spuious, and that improves receiver faces the rank channel selectivity; Set up in the process at phase-locked loop, loop filter is set to high bandwidth mode, because at this moment phase-locked loop is not in normal operating conditions, and high phase noise and spuious to not influence of transceiver system, high bandwidth has accelerated to set up speed; Transceiver is under emission mode, and loop filter is arranged on middle bandwidth mode, and loop bandwidth is more than or equal to the data transfer rate that transmits.
The power scaling prescaler circuit block diagram of the embodiment of the invention as shown in Figure 2, this power scaling prescaler has three grade of 2 frequency divider Div1, Div2, Div3,2 frequency divider Div1 at different levels, Div2, the Div3 cascade, the input of 2 frequency divider Div1 is the input of whole pre-divider, the output of 2 frequency divider Div1 connects the input of 2 frequency divider Div2, the output of 2 frequency divider Div2 connects the input of 2 frequency divider Div3, the output of 2 frequency divider Div3 connects the input of phase selector, the output of phase selector connects the input of Fractional-N frequency device, the output Fout of Fractional-N frequency device is the output of pre-divider, the output Fout of Fractional-N frequency device and pattern control word are connected two inputs of NAND gate respectively, the output of NAND gate connects the input of phase control module, and the output of phase control module connects the control word input of phase selector.
2 frequency divider Div1, the circuit structure of Div2 and Div3 is identical, but used transistor arrangement difference, 2 frequency divider Div1, Div2 is identical with the transistorized channel length of same position among the Div3, among the 2 frequency divider Div2 transistorized width be among the 2 frequency divider Div1 same position transistor width 1/2, among the 2 frequency divider Div3 transistorized width be among the 2 frequency divider Div2 same position transistor width 1/2, institutes at different levels consumed current is directly proportional with the frequency of the input signal of corresponding stage, 2 frequency divider Div1, Div2, the operating frequency of Div3 is respectively Fin, Fin/2, Fin/4, the size of current of 2 frequency divider Div1 is I, the size of current of 2 frequency divider Div2 is I/2, and the size of current of 2 frequency divider Div3 is I/4.In this power scaling prescaler, the power consumption of 2 frequency divider Div1, Div2 and Div3 is occupied an leading position, 2 frequency divider Div1, the Div2 of present embodiment and Div3 consumed current altogether are 2I, and 2 frequency dividers of traditional pre-divider adopt identical circuit structure and transistor, consumed current is 4I altogether, so compare with traditional structure, the current drain of present embodiment can reduce half, can effectively reduce the power consumption of pre-divider.
2 divider unit circuit diagrams of present embodiment as shown in Figure 3, PMOS manages M1, the source electrode of M2 connects the power supply positive voltage, PMOS manages M1, the grounded-grid of M2, the drain electrode of PMOS pipe M1 connects output port IN, the drain electrode of PMOS pipe M2 connects output port IP, the grid of NMOS pipe M3 connects signal input part DP, the grid of NMOS pipe M6 connects signal input part DN, the drain electrode of NMOS pipe M3 connects output port IN, the drain electrode of NMOS pipe M6 connects output port IP, after linking to each other, the source electrode of the source electrode of NMOS pipe M3 and NMOS pipe M6 is connected the drain electrode of NMOS pipe M7, the grid of NMOS pipe M7 connects input end of clock CLKP, the source ground of NMOS pipe M7, the drain electrode of NMOS pipe M4 connects output IN, the drain electrode of NMOS pipe M5 connects output IP, the drain electrode of NMOS pipe M4 connects the grid of NMOS pipe M5, the grid of NMOS pipe M4 connects the drain electrode of NMOS pipe M5, after linking to each other, the source electrode of the source electrode of NMOS pipe M4 and NMOS pipe M5 is connected the drain electrode of NMOS pipe M8, the grid of NMOS pipe M8 connects input end of clock CLKN, the source ground of NMOS pipe M8.
The multimode bandwidth loop filter circuit figure of the embodiment of the invention as shown in Figure 4, pattern control word Lfsw0 is connected to signal path selector Mux1, the control end S0 of Mux2, pattern control word Lfsw1 is connected to signal path selector Mux1, the control end S1 of Mux2, the input I of signal path selector Mux1 is the input Lin of loop filter, the output O2 of signal path selector Mux1 connects the input of high bandwidth loop filter, the input of bandwidth loop filter during the output O1 of signal path selector Mux1 connects, the output O0 of signal path selector Mux1 connects the input of low bandwidth loop filter, the output of high bandwidth loop filter connects the input I2 of signal path selector Mux2, the output of middle bandwidth loop filter connects the input I1 of signal path selector Mux2, and the output of low bandwidth loop filter connects the input I0 of signal path selector Mux2.The output O of signal path selector Mux2 is the output Lout of loop filter.
The operation principle of the multimode bandwidth loop filter of present embodiment is that for signal path selector Mux1, when control end S0, S1 input low level, conducting between input I and the output O0 disconnects between input I and output O1, the O2; When control end S1 input low level, control end S0 input high level, conducting between input I and the output O1 disconnects between input I and output O0, the O2; When control input end S1 input high level, control end S0 input low level, conducting between input I and the output O2 disconnects between input I and output O0, the O1.For signal path selector Mux2, when control end S0, S1 input low level, conducting between input I0 and the output O disconnects between input I1, I2 and the output O; When control end S1 input low level, control end S0 input high level, conducting between input I1 and the output O disconnects between input I0, I2 and the output O; When control end S1 input high level, control end S0 input low level, conducting between input I2 and the output O disconnects between input I0, I1 and the output O.The bandwidth of high bandwidth loop filter is the wideest in 3 loop filters, is applicable to setting up under the state of phase-locked loop; The bandwidth of low bandwidth loop filter is minimum, is applicable under the receiving mode of half-duplex transceiver; The bandwidth of middle bandwidth loop filter more than or equal to the rate of transmitting, is applicable under the emission mode of half-duplex transceiver between high bandwidth loop filter and low bandwidth loop filter.When the half-duplex radio frequency transceiver is operated in receiving mode following time, loop filter pattern control word Lfsw1, Lfsw0 put low level, input signal Lin is through signal path selector Mux1, low bandwidth loop filter and signal path selector Mux2 output, the loop bandwidth of phase-locked loop is lower like this, in-band noise and spuious little, the adjacent channel selectivity of receiver is good; When the half-duplex radio frequency transceiver is operated in emission mode following time, loop filter pattern control word Lfsw1 puts low level, pattern control word Lfsw0 puts high level, input signal Lin is through signal path selector Mux1, middle bandwidth loop filter, signal path selector Mux2 output, like this under the situation of the requirement of satisfying the transmitter signal rate, make in-band noise and the spuious minimum that remains on, the Error Vector Magnitude of transmitter is little, and it is good to face rank channel rejection ratio; Phase-locked loop in the half-duplex radio frequency transceiver is when setting up state, loop filter pattern control word Lfsw1 puts high level, pattern control word Lfsw0 puts low level, input signal Lin is through signal path selector Mux1, high bandwidth loop filter, signal path selector Mux2 output, the loop bandwidth of phase-locked loop is the wideest like this, accelerates to set up speed.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1, a kind of phase-locked loop with power scaling prescaler and multimode bandwidth loop filter is characterized in that described phase-locked loop comprises:
Pre-divider, described pre-divider comprise two-stage frequency divider at least, frequency divider cascades at different levels, and transistor arrangement difference in the frequency dividers at different levels is used for the power consumption convergent-divergent of pre-divider;
Loop filter, described loop filter comprises the loop filter of at least three different bandwidths, is used for Bandwidth Dynamic and switches;
Voltage controlled oscillator, the input of described voltage controlled oscillator connects the output of described loop filter, and the output of described voltage controlled oscillator connects an input of described pre-divider;
The low frequency frequency divider, input of described low frequency frequency divider and the output that is connected described pre-divider;
Modulator receives the frequency dividing ratio control word, and the output of described modulator connects another input of described pre-divider and another input of described low frequency frequency divider;
Phase frequency detector, the output of described low frequency frequency divider and phase-locked loop reference frequency source are connected two inputs of described phase frequency detector respectively;
Charge pump, the input of described charge pump connects the output of described phase frequency detector, and described electric charge delivery side of pump connects the input of described loop filter.
2, the phase-locked loop with power scaling prescaler and multimode bandwidth loop filter as claimed in claim 1 is characterized in that, transistor arrangement in the described frequency dividers at different levels is specially:
The transistorized channel length of same position is identical in the frequency dividers at different levels, in the back one-level frequency divider transistorized width be in the previous stage frequency divider the transistorized width of same position divided by the frequency dividing ratio of previous stage frequency divider, the electric current of back one-level frequency divider is the frequency dividing ratio of the electric current of previous stage frequency divider divided by the previous stage frequency divider, and the frequency input signal of back one-level frequency divider is the frequency dividing ratio of the frequency input signal of previous stage frequency divider divided by the previous stage frequency divider.
3, the phase-locked loop with power scaling prescaler and multimode bandwidth loop filter as claimed in claim 2 is characterized in that described pre-divider specifically comprises:
The above frequency divider of two-stage, the output of previous stage frequency divider connects the input of back one-level frequency divider, and the input of first order frequency divider is the input of pre-divider;
Phase selector, the output of the afterbody frequency divider of the above frequency divider of described two-stage connects the input of described phase selector;
The Fractional-N frequency device, the output of described phase selector connects the input of described Fractional-N frequency device, and the output of described Fractional-N frequency device is the output of described pre-divider;
NAND gate, the output of described Fractional-N frequency device and pattern control word are connected two inputs of described NAND gate respectively;
The phase control module, the output of described NAND gate connects the input of described phase control module, and the output of described phase control module connects the control word input of described phase selector.
4, as each described phase-locked loop of claim 1 to 3, it is characterized in that described frequency divider is specially 2 frequency dividers with power scaling prescaler and multimode bandwidth loop filter.
5, the phase-locked loop with power scaling prescaler and multimode bandwidth loop filter as claimed in claim 4 is characterized in that, described 2 frequency dividers specifically comprise:
Two PMOS pipes, the source electrode of two PMOS pipes connects the power supply positive voltage, the grounded-grid of two PMOS pipes, the drain electrode of a PMOS pipe connects first output port, and the drain electrode of the 2nd PMOS pipe connects second output port;
Six NMOS pipes, the grid of the one NMOS pipe connects first signal input part, the grid of the 2nd NMOS pipe connects the secondary signal input, the drain electrode of the one NMOS pipe connects first output port, the drain electrode of the 2nd NMOS pipe connects second output port, after linking to each other, the source electrode of the source electrode of the one NMOS pipe and the 2nd NMOS pipe is connected the drain electrode of the 3rd NMOS pipe, the grid of the 3rd NMOS pipe connects an input end of clock, the source ground of the 3rd NMOS pipe, the drain electrode of the 4th NMOS pipe connects first output port, the drain electrode of the 5th NMOS pipe connects second output port, the drain electrode of the 4th NMOS pipe connects the grid of the 5th NMOS pipe, the grid of the 4th NMOS pipe connects the drain electrode of the 5th NMOS pipe, after linking to each other, the source electrode of the source electrode of the 4th NMOS pipe and the 5th NMOS pipe is connected the drain electrode of the 6th NMOS pipe, the grid of the 6th NMOS pipe connects another input end of clock, the source ground of the 6th NMOS pipe.
6, the phase-locked loop with power scaling prescaler and multimode bandwidth loop filter as claimed in claim 1 is characterized in that, described loop filtering implement body comprises:
High bandwidth loop filter, middle bandwidth loop filter, low bandwidth loop filter and two signal path selectors;
The control end connecting band wide mode control word of two signal path selectors, the first signal path selector has an input and three outputs, the input of the first signal path selector connects the electric charge delivery side of pump, first output of the first signal path selector connects the input of high bandwidth loop filter, the input of bandwidth loop filter during second output of the first signal path selector connects, the 3rd output of the first signal path selector connects the input of low bandwidth loop filter, secondary signal path selector has three inputs and an output, the first input end of secondary signal path selector connects the output of high bandwidth loop filter, the output of bandwidth loop filter during second input of secondary signal path selector connects, the 3rd input of secondary signal path selector connects the output of low bandwidth loop filter, and the output of secondary signal path selector connects the input of voltage controlled oscillator.
7, the phase-locked loop with power scaling prescaler and multimode bandwidth loop filter as claimed in claim 6 is characterized in that, described Bandwidth Dynamic switching is specially:
The bandwidth of loop filter is switched with the difference of the mode of operation of half-duplex radio frequency transceiver, when transceiver is receiving mode, loop filter is set to low bandwidth model, reduces the in-band noise of loop filter and spuious, improves the adjacent rank channel selectivity of receiver; When transceiver was emission mode, loop filter was set to middle bandwidth mode, realized the normal transmission of FM signal, and reduced the Error Vector Magnitude of transmitter, improved adjacent rank channel rejection ratio; When phase-locked loop is in when setting up state, loop filter is arranged on high bandwidth mode, accelerates phase-locked loop and sets up speed.
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| CN102122957A (en) * | 2011-03-31 | 2011-07-13 | 海能达通信股份有限公司 | Phase-locking loop rapid locking circuit and method |
| CN102946249A (en) * | 2012-12-10 | 2013-02-27 | 北京中科飞鸿科技有限公司 | Frequency synthesizer |
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| JP3119205B2 (en) * | 1997-07-18 | 2000-12-18 | 日本電気株式会社 | PLL circuit |
| WO2006137031A2 (en) * | 2005-06-21 | 2006-12-28 | Nxp B.V. | Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops |
| CN1767391B (en) * | 2005-11-25 | 2010-05-05 | 清华大学 | Frequency divider for 8 phase output in phase switching type pre-divider |
| EP2009796A1 (en) * | 2007-06-28 | 2008-12-31 | Alcatel Lucent | Method for filtering a signal in a phase-locked loop, phase locked loop, base station and communication network therefor |
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| CN102122957A (en) * | 2011-03-31 | 2011-07-13 | 海能达通信股份有限公司 | Phase-locking loop rapid locking circuit and method |
| CN102122957B (en) * | 2011-03-31 | 2016-01-06 | 海能达通信股份有限公司 | A kind of circuit of phase locked loop fast lock and method |
| CN102946249A (en) * | 2012-12-10 | 2013-02-27 | 北京中科飞鸿科技有限公司 | Frequency synthesizer |
| CN103869158B (en) * | 2012-12-10 | 2017-12-22 | 北京普源精电科技有限公司 | A kind of spectrum analyzer |
| CN106533460A (en) * | 2016-11-01 | 2017-03-22 | 全球能源互联网研究院 | Wireless transmitter and control method thereof |
| CN111464182A (en) * | 2020-04-29 | 2020-07-28 | 四川玖越机器人科技有限公司 | Inspection robot |
| RU2810530C1 (en) * | 2023-09-28 | 2023-12-27 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Томский государственный университет систем управления и радиоэлектроники" | Method of digital compensation for system interference in full-duplex data transmission systems over power circuits |
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| CN101615905B (en) | 2012-10-10 |
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