CN108599759B - Clock CDR circuit based on embedded clock bit and control device - Google Patents
Clock CDR circuit based on embedded clock bit and control device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Abstract
The invention belongs to the technical field of electronic circuits, and provides a clock CDR circuit and a control device based on embedded clock bits, which perform frequency discrimination and phase discrimination on embedded clock serial data and a feedback signal output by a voltage-controlled oscillator array under the condition that a frequency divider performs frequency division action, output a control signal to drive a first charge pump and a second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signal exceeds a preset threshold value, so that the voltage-controlled oscillator array is provided with initial voltage and frequency conversion is performed, and then parallel data are output through a multi-edge sampling module, thereby realizing data clock recovery without additionally increasing a reference frequency signal line, reducing the system cost, simultaneously ensuring that CDR can not be locked at a harmonic wave part, and solving the problem that the existing clock CDR circuit technology needs additionally increasing the reference frequency signal line, leading to a problem of a messy line and an increase in system cost.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a clock CDR circuit based on embedded clock bits and a control device.
Background
Among the data transmission lines, the CDR line is an indispensable one component. Currently, the main CDR structure is a phase difference value-based Proportional Integral (PI) structure, which needs to provide an additional reference clock to avoid the problem of CDR locking on harmonics, so a clock line should be additionally introduced to provide the reference clock. However, in the long-distance data transmission, it is hard to accept to add one extra transmission line, and there is a problem that the line is messy.
As shown in fig. 1, a CDR structure based on phase interpolation commonly used in the prior art needs to add a reference frequency signal (indicated by FREF in fig. 1) in addition to necessary data signals to ensure that the CDR does not lock on harmonic frequencies, which has an impact on system cost and reliability.
Therefore, the conventional clock CDR circuit technology has the problems of additional reference frequency signal lines, resulting in a messy circuit and increased system cost.
Disclosure of Invention
The invention aims to provide a clock CDR circuit and a control device based on embedded clock bits, and aims to solve the problems that in the existing clock CDR circuit technology, a reference frequency signal line needs to be additionally added, so that the circuit is messy and the system cost is increased.
A first aspect of the invention provides a clock CDR circuit based on embedded clock bits, the clock CDR circuit comprising:
the device comprises a phase frequency and phase discrimination module, a first charge pump, a second charge pump, an initial frequency setting module, a voltage-controlled oscillator array, a frequency divider and a multi-edge sampling module;
the receiving end of the frequency and phase discrimination module is connected with embedded clock serial data, the first input end of the frequency and phase discrimination module is connected with the output end of the frequency divider, the second input end of the frequency and phase discrimination module is connected with the first output end of the voltage-controlled oscillator array, the first output end and the second output end of the frequency and phase discrimination module are simultaneously connected with the first charge pump and the second charge pump, the output end of the first charge pump is connected with the input end of the initial frequency setting module, the output end of the second charge pump is connected with the output end of the initial frequency setting module, the second output end of the voltage-controlled oscillator array is connected with the input end of the frequency divider, and the third output end of the voltage-controlled oscillator array is connected with the multi-edge sampling module;
under the condition that the frequency divider outputs frequency division signals, the frequency and phase discrimination module performs frequency and phase discrimination on the embedded clock serial data and feedback signals output by the voltage-controlled oscillator array, and outputs control signals to drive the first charge pump and the second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signals exceeds a preset threshold value, so that the initial frequency setting module provides initial voltage for the voltage-controlled oscillator array and performs frequency conversion, and then parallel data are output through the multi-edge sampling module.
A second aspect of the invention provides a control apparatus comprising an embedded clock bit and a clock CDR circuit, the clock CDR circuit comprising:
the device comprises a phase frequency and phase discrimination module, a first charge pump, a second charge pump, an initial frequency setting module, a voltage-controlled oscillator array, a frequency divider and a multi-edge sampling module;
the receiving end of the frequency and phase discrimination module is connected with embedded clock serial data, the first input end of the frequency and phase discrimination module is connected with the output end of the frequency divider, the second input end of the frequency and phase discrimination module is connected with the first output end of the voltage-controlled oscillator array, the first output end and the second output end of the frequency and phase discrimination module are simultaneously connected with the first charge pump and the second charge pump, the output end of the first charge pump is connected with the input end of the initial frequency setting module, the output end of the second charge pump is connected with the output end of the initial frequency setting module, the second output end of the voltage-controlled oscillator array is connected with the input end of the frequency divider, and the third output end of the voltage-controlled oscillator array is connected with the multi-edge sampling module;
under the condition that the frequency divider outputs frequency division signals, the frequency and phase discrimination module performs frequency discrimination and phase discrimination on the embedded clock serial data and feedback signals output by the voltage-controlled oscillator array, and outputs control signals to drive the first charge pump and the second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signals exceeds a preset threshold value, so that the initial frequency setting module provides initial voltage for the voltage-controlled oscillator array and performs frequency conversion, and then parallel data are output through the multi-edge sampling module.
The clock CDR circuit and the control device based on the embedded clock bit provided by the invention carry out frequency discrimination and phase discrimination on feedback signals output by embedded clock serial data and a voltage-controlled oscillator array under the condition that a frequency divider carries out frequency division action, and output control signals to drive a first charge pump and a second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signals exceeds a preset threshold value, so that initial voltage is provided for the voltage-controlled oscillator array and frequency conversion is carried out, and then parallel data are output through a multi-edge sampling module, thereby realizing data clock recovery without additionally increasing a reference frequency signal line, reducing the system cost, simultaneously ensuring that CDR can not be locked at a harmonic wave position, solving the problems that the existing clock CDR circuit technology needs to additionally increase the reference frequency signal line, leading to a problem of a messy line and an increase in system cost.
Drawings
Fig. 1 is a schematic diagram of a CDR structure based on phase interpolation commonly used in the prior art.
Fig. 2 is a schematic block diagram of a clock CDR circuit based on embedded clock bits according to the present invention.
Fig. 3 is a circuit diagram of an exemplary phase and frequency detection module in a clock CDR circuit based on embedded clock bits according to the present invention.
FIG. 4 is a schematic diagram of waveforms of signals at various positions in a phase frequency detection module in a clock CDR circuit based on embedded clock bits according to the present invention
Fig. 5 is a circuit diagram of an exemplary initial frequency setting module in the clock CDR circuit based on embedded clock bits according to the present invention.
FIG. 6 is a waveform diagram showing a simulation of an initial frequency setting module in the clock CDR circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The clock CDR circuit and the control device based on the embedded clock bit can realize data clock recovery under the condition of no reference clock by adding the clock bit in the data link and by a specific CDR structure. Therefore, the clock lines which are additionally added in the traditional structure are reduced, the system cost is reduced, and the working reliability is improved. The phase interpolation structure CDR adopts a special circuit structure and a special system structure, solves the problem that the CDR of the commonly used phase interpolation structure at present needs an additional clock line to ensure that the CDR can not be locked at the harmonic frequency, has the advantages of low cost, high reliability and the like, and is very suitable for long-distance data transmission, such as application scenes of an automobile display system, a central information display and the like.
Fig. 2 shows a module structure of the clock CDR circuit based on embedded clock bits provided in the present invention, and for convenience of illustration, only the relevant parts to this embodiment are shown, and the details are as follows:
the clock CDR circuit based on embedded clock bits includes a phase frequency detector 201, a first charge pump 202, a second charge pump 203, an initial frequency setting module 204, a voltage controlled oscillator array (fig. 2 is represented by a VCO) 205, a frequency divider 207, and a multi-edge sampling module 206.
The receiving end of the phase frequency and phase detection module 201 is connected to the embedded clock serial data, the first input end of the phase frequency and phase detection module 201 is connected to the output end of the frequency divider 207, the second input end of the phase frequency and phase detection module 201 is connected to the first output end of the voltage controlled oscillator array 205, the first output end and the second output end of the phase frequency and phase detection module 201 are simultaneously connected to the first charge pump 202 and the second charge pump 203, the output end of the first charge pump 202 is connected to the input end of the initial frequency setting module 204, the output end of the second charge pump 203 is connected to the output end of the initial frequency setting module 204, the second output end of the voltage controlled oscillator array 205 is connected to the input end of the frequency divider 207, and the third output end of the voltage controlled oscillator array 205 is connected to the multi-edge sampling module 206.
Under the condition that the frequency divider 207 outputs a frequency division signal, the phase frequency and phase detection module 201 performs phase frequency and phase detection on the embedded clock serial data and the feedback signal output by the voltage-controlled oscillator array 205, and when detecting that the difference between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signal exceeds a preset threshold, outputs a control signal to drive the first charge pump 202 and the second charge pump 203 to start up, so that the initial frequency setting module 204 provides an initial voltage for the voltage-controlled oscillator array 205 and performs frequency conversion, and then outputs parallel data through the multi-edge sampling module 206.
As an embodiment of the present invention, the clock CDR circuit further includes a first NOT gate NOT1 and a second NOT gate NOT 2; a first output end of the phase frequency and phase detection module 201 is connected with an input end of a first NOT gate NOT1, an output end of the first NOT gate NOT1 is connected with a first input end of the first charge pump 202, a second output end of the phase frequency and phase detection module 201 is connected with an input end of a second NOT gate NOT2, and an output end of the second NOT gate NOT2 is connected with a second input end of the first charge pump 202.
As an embodiment of the present invention, the clock CDR circuit further includes a first capacitor C1, a second capacitor C2, and a first switch Q1; a first terminal of the first capacitor C1 is connected to the reference voltage source, a second terminal of the first capacitor C1 is connected to the input terminal of the initial frequency setting module 204, a first terminal of the second capacitor C2 is connected to the controlled terminal of the first switch Q1 and the output terminal of the initial frequency setting module 204, the input terminal of the first switch Q1 is connected to the vco array 205, and a second terminal of the second capacitor C2 is connected to the ground with the output terminal of the first switch Q1.
Specifically, the first switching transistor Q1 may be a field effect transistor or a triode. The grid electrode, the drain electrode and the source electrode of the field effect transistor respectively correspond to the controlled end, the input end and the output end of the first switch tube Q1; the base electrode, the collector electrode and the emitter electrode of the triode respectively correspond to the controlled end, the input end and the output end of the first switching tube Q1.
As an embodiment of the present invention, the phase frequency detecting module 201 performs phase frequency detection only during a frequency division operation corresponding to a clock bit, converts a frequency/phase difference detected by the phase frequency detecting module 201 into a current difference through the second charge pump 203, and forms a control voltage on the second capacitor C2 to control a current of the first switch transistor Q1. Meanwhile, the first charge pump 202 and the second charge pump 203 work together, but input signals are mutually in opposite phase, the output current of the first charge pump 202 is directly injected into the voltage-controlled oscillator array 205, and the voltage-controlled oscillator array 205 is composed of a plurality of ring oscillators, so that wide-frequency-range output is realized. The frequency divider 207 divides the frequency of the signal output by the vco array 205, and the frequency division ratio corresponds to the ratio of the clock bit to the data amount of the data chain, so as to implement frequency and phase discrimination on the clock bit and ensure that the clock output by the vco array 205 is aligned with the data. In addition, the initial frequency setting module 204 adds an initial voltage to Vtune, so that the frequency of the vco array 205 is shifted from a high frequency to a low frequency, and it is ensured that the vco will not be locked at a harmonic.
Specifically, the clock CDR circuit is based on a self-bias structure, and a Process Flow clock (PFD) structure is adjusted, so that the system performs frequency and phase discrimination only at a clock bit of serial data. Therefore, the alignment of data and clock can be realized by only controlling the proportional relation between the frequency dividing ratio of the frequency divider and the clock bit in the data link, and the recovery of the data clock without the reference clock can be realized.
Fig. 3 shows an exemplary circuit of a phase frequency detection module in a clock CDR circuit based on embedded clock bits, which only shows the relevant parts related to this embodiment for convenience of description, and the details are as follows:
as an embodiment of the present invention, the phase frequency AND phase detecting module 201 includes a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, a first AND gate AND1, AND a delay setting unit 301;
the input end of the first flip-flop D1 is connected to a reference voltage, the clock end of the first flip-flop D1 is connected to the embedded clock serial data, the reset end of the first flip-flop D1 is connected to the reset end of the second flip-flop D2 AND the first end of the delay setting unit 301 in common, the output end of the first flip-flop D1 is connected to the first input end of the first AND gate AND1, the clock end of the second flip-flop D2 is connected to the feedback signal, the output end of the second flip-flop D2 is connected to the second input end of the first AND gate AND1, the output end of the first AND gate AND1 is connected to the reset end of the third flip-flop D3, the clock end of the third flip-flop D3 is connected to the frequency division signal, AND the output end of the third flip-flop D3 is connected to the second end of the delay setting unit 301.
Compared with the conventional phase frequency and phase detection circuit, the phase frequency and phase detection module 201 is additionally provided with a delay setting unit 301 and a third flip-flop D3, and the frequency-divided signal is a frequency-divided clock signal. Fig. 4 shows waveforms of signals at various positions in the phase frequency detection module 201 (when the lead time T1 is greater than the delay time T0), and the operation sequence is as follows:
1. at the beginning, the RESET signal is 0, and the first flip-flop D1 and the second flip-flop D2 form the most basic PFD, and perform phase frequency discrimination on the embedded clock serial data and the feedback signal.
2. After one phase frequency detection operation is completed, the output Q of the first flip-flop D1 and the second flip-flop D2 are combined to generate a RESET signal. The first flip-flop D1 and the second flip-flop D2 are reset. Since the CLK of the third flip-flop D3 is the divided clock signal, the first flip-flop D1 and the second flip-flop D2 will maintain the RESET state until the divided signal is absent.
3. The CLK signal input of the third flip-flop D3, i.e., the divided signal, appears rising, and the output of the third flip-flop D3
Low, RESET to release the first flip-flop D1 and the second flip-flop D2, the PFD consisting of the first flip-flop D1 and the second flip-flop D2 operates again. The delay setting unit 301 may control the RESET time.
4. And (5) repeating the operation of the step (2).
Through the process, the function of frequency discrimination and phase discrimination is realized only when the rising edge of the frequency-divided signal appears.
Fig. 5 and fig. 6 respectively show an exemplary circuit and a circuit simulation waveform of an initial frequency setting module in a clock CDR circuit based on embedded clock bits provided by the present invention, and for convenience of description, only the relevant parts to this embodiment are shown, and detailed descriptions are as follows:
as an embodiment of the present invention, the initial frequency setting module 204 includes a first resistor R1, a second resistor R2, a first transmission gate TG1, a second transmission gate TG2, a second switch Q2, a third switch Q3, and a fourth switch Q4;
an input end of the first transmission gate TG1 is used as an input end of the initial frequency setting module 204, an output end of the first transmission gate TG1 is connected to a controlled end of the second switch tube Q2, an input end of the second switch tube Q2 and an input end of the third switch tube Q3 are connected to a reference voltage, an output end of the second switch tube Q2 is connected to an input end of the fourth switch tube Q4, an output end of the third switch tube Q3 is connected to a first end of a first resistor R1, a second end of a first resistor R1 is connected to a first end of a second resistor R2, an output end of the fourth switch tube Q4 and a second end of the second resistor R2 are grounded, a controlled end of the fourth switch tube Q4 is connected to an input end of the second transmission gate TG2, and an output end of the second transmission gate TG2 is used as an output end of the initial frequency setting module 204.
Specifically, the second switching transistor Q2 may be a field effect transistor or a triode. The grid electrode, the drain electrode and the source electrode of the field effect transistor respectively correspond to the controlled end, the input end and the output end of the second switch tube Q2; the base electrode, the collector electrode and the emitter electrode of the triode respectively correspond to the controlled end, the input end and the output end of the second switching tube Q2. The third switch tube Q3 and the fourth switch tube Q4 have the same structure as the second switch tube Q2.
The operation principle of the initial frequency setting module 204 is as follows: when EN is high and ENB is low, the third switching transistor Q3 is turned on, the first resistor R1 and the second resistor R2 divide VDD, the second transmission gate TG2 is turned on, and the Vtune voltage is pulled to the divided voltage value of the first resistor R1 and the second resistor R2. The fourth switching tube Q4 mirrors an NMOS tuning tube of the vco array 205, and the second switching tube Q2 mirrors a PMOS tuning tube, so that the voltage of the second switching tube Q2 is equal to the voltage of the operating frequency VBP corresponding to the vco array 205, and the first transmission gate TG1 is turned on to transmit the voltage to VBP.
And the magnitude of the voltage division value is set, so that the voltage corresponding to the Vtune point can ensure that the working frequency of the voltage-controlled oscillator array 205 is higher than the required frequency for locking.
When EN is low and ENB is high, the third switching transistor Q3 is turned off, the first transmission gate TG1 and the second transmission gate TG2 are turned off, the initial frequency setting module 204 releases Vtune and VBP, and the voltage Vtune is controlled by the loop. Since the initial value is set higher than the required frequency for locking, the loop will control the CDR to move from high frequency to low frequency, preventing the situation of being locked at harmonics.
The invention also provides a control device comprising an embedded clock bit and a clock CDR circuit as described above.
The operation principle of the clock CDR circuit and the control device based on embedded clock bits is described below with reference to fig. 1 to 6:
first, data recovery is performed based on embedded clock bits, and time bits need to be embedded in a data chain, and assuming that 28 bits of a data packet are used, the first bit and the tail are clock bits, the first bit is always 1, and the tail is always 0, so that the valid data is 26 bits.
The divider ratio is set to divide by 14, depending on the ratio of the data bits to the clock bits. Thus, the phase frequency detection module 201 will perform phase frequency detection at a frequency division of 14 of the input clock frequency. (assuming simultaneous sampling of the upper and lower edges, the required sampling frequency is half the data rate, depending on the sampling part structure, the divider division ratio is as follows:.)
Table-different data bit numbers correspond to frequency divider division ratios
The initial frequency setting module 204 is then designed to make the initial frequency of the vco array 205 higher than the highest frequency required for locking.
Next, the phase frequency detection module 201 operates to control Vtune to move to a lower frequency due to the higher frequency of the vco array 205.
Finally, the frequency of the vco array 205 is gradually decreased, and since the phase frequency detection module 201 performs phase frequency detection only on the clock bit at the frequency division of 14 of the vco array 205, the CDR is finally controlled to lock at the position where the frequency division of 14 of the vco array 205 coincides with the clock bit, and at this time, the frequency of the vco array 205 is 14 times the clock bit frequency. If sampling is performed on the upper edge and the lower edge, each clock edge is exactly aligned with one data, the required phase shift is performed on the output of the voltage-controlled oscillator array 205, and the data is sampled by the multi-edge sampling module 206, so that data recovery is realized.
To sum up, the clock CDR circuit and the control device according to the embodiment of the present invention perform frequency discrimination and phase discrimination on the embedded clock serial data and the feedback signal output by the vco array under the condition that the frequency divider performs frequency division, and output a control signal to drive the first charge pump and the second charge pump to start when detecting that the difference between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signal exceeds the preset threshold, so as to provide an initial voltage and perform frequency conversion on the vco array, and output parallel data through the multi-edge sampling module, thereby achieving data clock recovery without additionally increasing a reference frequency signal line, reducing system cost, and simultaneously ensuring that the CDR is not locked at a harmonic, solving the problem that the existing clock CDR circuit technology needs to additionally increase a reference frequency signal line, resulting in a complicated circuit and an increase in system cost.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A clock CDR circuit based on embedded clock bits, the clock CDR circuit comprising:
the device comprises a frequency and phase discrimination module, a first charge pump, a second charge pump, an initial frequency setting module, a voltage-controlled oscillator array, a frequency divider and a multi-edge sampling module;
the receiving end of the frequency and phase discrimination module is connected with embedded clock serial data, the first input end of the frequency and phase discrimination module is connected with the output end of the frequency divider, the second input end of the frequency and phase discrimination module is connected with the first output end of the voltage-controlled oscillator array, the first output end and the second output end of the frequency and phase discrimination module are simultaneously connected with the first charge pump and the second charge pump, the output end of the first charge pump is connected with the input end of the initial frequency setting module, the output end of the second charge pump is connected with the output end of the initial frequency setting module, the second output end of the voltage-controlled oscillator array is connected with the input end of the frequency divider, and the third output end of the voltage-controlled oscillator array is connected with the multi-edge sampling module;
under the condition that the frequency divider outputs frequency division signals, the frequency and phase discrimination module performs frequency discrimination and phase discrimination on the embedded clock serial data and feedback signals output by the voltage-controlled oscillator array, and outputs control signals to drive the first charge pump and the second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signals exceeds a preset threshold value, so that the initial frequency setting module provides initial voltage for the voltage-controlled oscillator array and performs frequency conversion, and then parallel data are output through the multi-edge sampling module;
the frequency and phase discrimination module comprises:
the trigger circuit comprises a first trigger, a second trigger, a third trigger, a first AND gate and a delay setting unit;
the input end of the first trigger is connected with a reference voltage, the clock end of the first trigger is connected with the embedded clock serial data, the reset end of the first trigger is connected with the reset end of the second trigger and the first end of the delay setting unit in a common mode, the output end of the first trigger is connected with the first input end of the first AND gate, the clock end of the second trigger is connected with the feedback signal, the output end of the second trigger is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the reset end of the third trigger, the clock end of the third trigger is connected with the frequency division signal, and the output end of the third trigger is connected with the second end of the delay setting unit.
2. The clock CDR circuit of claim 1, wherein the clock CDR circuit further comprises:
a first not gate and a second not gate;
the first output end of the phase frequency and phase demodulation module is connected with the input end of the first NOT gate, the output end of the first NOT gate is connected with the first input end of the first charge pump, the second output end of the phase frequency and phase demodulation module is connected with the input end of the second NOT gate, and the output end of the second NOT gate is connected with the second input end of the first charge pump.
3. The clock CDR circuit of claim 1, wherein the clock CDR circuit further comprises:
the first capacitor, the second capacitor and the first switch tube;
the first end of the first capacitor is connected with a reference voltage source, the second end of the first capacitor is connected with the input end of the initial frequency setting module, the first end of the second capacitor is connected with the controlled end of the first switch tube and the output end of the initial frequency setting module in a common mode, the input end of the first switch tube is connected with the voltage-controlled oscillator array, and the second end of the second capacitor is connected with the output end of the first switch tube in a grounding mode.
4. The clock CDR circuit of claim 1, wherein the initial frequency setting module comprises:
the circuit comprises a first resistor, a second resistor, a first transmission gate, a second switching tube, a third switching tube and a fourth switching tube;
the input end of the first transmission gate is used as the input end of the initial frequency setting module, the output end of the first transmission gate is connected with the controlled end of the second switch tube, the input end of the second switch tube and the input end of the third switch tube are connected with a reference voltage, the output end of the second switch tube is connected with the input end of the fourth switch tube, the output end of the third switch tube is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second resistor, the output end of the fourth switch tube is connected with the second end of the second resistor to the ground, the controlled end of the fourth switch tube is connected with the input end of the second transmission gate, and the output end of the second transmission gate is used as the output end of the initial frequency setting module.
5. A control device comprising an embedded clock bit and clock CDR circuit, the clock CDR circuit comprising:
the device comprises a phase frequency and phase discrimination module, a first charge pump, a second charge pump, an initial frequency setting module, a voltage-controlled oscillator array, a frequency divider and a multi-edge sampling module;
the receiving end of the frequency and phase discrimination module is connected with embedded clock serial data, the first input end of the frequency and phase discrimination module is connected with the output end of the frequency divider, the second input end of the frequency and phase discrimination module is connected with the first output end of the voltage-controlled oscillator array, the first output end and the second output end of the frequency and phase discrimination module are simultaneously connected with the first charge pump and the second charge pump, the output end of the first charge pump is connected with the input end of the initial frequency setting module, the output end of the second charge pump is connected with the output end of the initial frequency setting module, the second output end of the voltage-controlled oscillator array is connected with the input end of the frequency divider, and the third output end of the voltage-controlled oscillator array is connected with the multi-edge sampling module;
under the condition that the frequency divider outputs frequency division signals, the frequency and phase discrimination module performs frequency discrimination and phase discrimination on the embedded clock serial data and feedback signals output by the voltage-controlled oscillator array, and outputs control signals to drive the first charge pump and the second charge pump to start when detecting that the difference value between the frequency/phase of the embedded clock serial data and the frequency/phase of the feedback signals exceeds a preset threshold value, so that the initial frequency setting module provides initial voltage for the voltage-controlled oscillator array and performs frequency conversion, and then parallel data are output through the multi-edge sampling module;
the frequency and phase discrimination module comprises:
the trigger circuit comprises a first trigger, a second trigger, a third trigger, a first AND gate and a delay setting unit;
the input end of the first trigger is connected with a reference voltage, the clock end of the first trigger is connected with the embedded clock serial data, the reset end of the first trigger is connected with the reset end of the second trigger and the first end of the delay setting unit, the output end of the first trigger is connected with the first input end of the first AND gate, the clock end of the second trigger is connected with the feedback signal, the output end of the second trigger is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the reset end of the third trigger, the clock end of the third trigger is connected with the frequency division signal, and the output end of the third trigger is connected with the second end of the delay setting unit.
6. The control apparatus of claim 5, wherein the clock CDR circuit further comprises:
a first not gate and a second not gate;
the first output end of the phase frequency and phase detection module is connected with the input end of the first NOT gate, the output end of the first NOT gate is connected with the first input end of the first charge pump, the second output end of the phase frequency and phase detection module is connected with the input end of the second NOT gate, and the output end of the second NOT gate is connected with the second input end of the first charge pump.
7. The control apparatus of claim 5, wherein the clock CDR circuit further comprises:
the first capacitor, the second capacitor and the first switch tube;
the first end of the first capacitor is connected with a reference voltage source, the second end of the first capacitor is connected with the input end of the initial frequency setting module, the first end of the second capacitor is connected with the controlled end of the first switch tube and the output end of the initial frequency setting module in a common mode, the input end of the first switch tube is connected with the voltage-controlled oscillator array, and the second end of the second capacitor is connected with the output end of the first switch tube in a grounded mode.
8. The control apparatus of claim 5, wherein the initial frequency setting module comprises:
the circuit comprises a first resistor, a second resistor, a first transmission gate, a second switching tube, a third switching tube and a fourth switching tube;
the input end of the first transmission gate is used as the input end of the initial frequency setting module, the output end of the first transmission gate is connected with the controlled end of the second switch tube, the input end of the second switch tube is connected with the reference voltage of the input end of the third switch tube, the output end of the second switch tube is connected with the input end of the fourth switch tube, the output end of the third switch tube is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second resistor, the output end of the fourth switch tube is connected with the second end of the second resistor in the ground, the controlled end of the fourth switch tube is connected with the input end of the second transmission gate, and the output end of the second transmission gate is used as the output end of the initial frequency setting module.
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| JP5363967B2 (en) * | 2009-12-22 | 2013-12-11 | ルネサスエレクトロニクス株式会社 | CLOCK DATA RECOVERY CIRCUIT, DISPLAY DEVICE DATA TRANSFER DEVICE, AND DISPLAY DEVICE DATA TRANSFER METHOD |
| US8284888B2 (en) * | 2010-01-14 | 2012-10-09 | Ian Kyles | Frequency and phase acquisition of a clock and data recovery circuit without an external reference clock |
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| CN106972857B (en) * | 2017-04-28 | 2023-03-21 | 深圳市国微电子有限公司 | Multi-loop self-biased phase-locked loop circuit and clock generator |
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