CN108599759A - Clock ce circuit and control device based on embedded clock position - Google Patents
Clock ce circuit and control device based on embedded clock position Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The invention belongs to electronic circuit technology fields,Provide clock ce circuit and control device based on embedded clock position,By in the case of frequency divider carries out frequency dividing action,Frequency and phase discrimination is carried out to embedding clock string row data and the feedback signal of voltage controlled oscillator array output,And when detecting that the difference of the frequency/phase of embedded clock serial data and the frequency/phase of feedback signal is more than predetermined threshold value,Output control signal is to drive the first charge pump and the second charge pump startup,So that providing initial voltage to voltage controlled oscillator array and carrying out frequency conversion,And then by the way that mostly parallel data is exported along sampling module,Data clock recovery can be realized therefore without the additional reference frequency signal line that increases,Reduce system cost,Ensure that CDR will not be locked at harmonic wave simultaneously,Solving existing clock CDR Line technologies, there is need additional increase reference frequency signal line,The problem of causing circuit mixed and disorderly and increasing system cost.
Description
Technical field
The invention belongs to electronic circuit technology fields, more particularly to based on the clock ce circuit of embedded clock position and control
Device.
Background technology
In data transmission link, CDR circuits are an indispensable component parts.Currently, main CDR structures are
Proportional integration (Proportion Integration, PI) structure based on phase difference value, when needing to provide additional reference
Clock should additionally introduce a clock line to provide reference clock to avoid there is the problem that CDR is locked on harmonic wave.So
And in long-range data transmission, it is more difficult received additionally to increase a transmission line, and can have that circuit is mixed and disorderly to ask
Topic.
If Fig. 1 shows the CDR structures commonly used in the prior art based on phase-interpolation, in addition to necessary data-signal
Outside, it also needs additionally to increase a reference frequency signal (Fig. 1 is indicated using FREF), to ensure that CDR will not be locked in harmonic frequency
On, which can all impact system cost and reliability.
Therefore, existing clock CDR Line technologies cause circuit numerous there is additional increase reference frequency signal line is needed
The problem of disorderly and increasing system cost.
Invention content
The purpose of the present invention is to provide clock ce circuits and control device based on embedded clock position, it is intended to solve existing
There is need additional increase reference frequency signal line, cause circuit mixed and disorderly and increase system for some clock CDR Line technologies
The problem of cost.
First aspect present invention provides the clock ce circuit based on embedded clock position, and the clock ce circuit includes：
Frequency and phase discrimination module, the second charge pump, original frequency setting module, voltage controlled oscillator array, is divided at the first charge pump
Frequency device and mostly along sampling module；
The receiving terminal of the frequency and phase discrimination module accesses embedded clock serial data, and the first of the frequency and phase discrimination module is defeated
Enter the output end for terminating the frequency divider, the second input of the frequency and phase discrimination module terminates the of the voltage controlled oscillator array
One output end, the first output end and second output terminal of the frequency and phase discrimination module connect first charge pump and described the simultaneously
Two charge pumps, the output of first charge pump terminate the input terminal of the original frequency setting module, second charge pump
Output terminate the output end of the original frequency setting module, the second output terminal of the voltage controlled oscillator array connects described point
The third output termination of the input terminal of frequency device, the voltage controlled oscillator array is described mostly along sampling module；
In the case of the frequency divider output frequency division signal, the frequency and phase discrimination module is to the embedded clock serial number
Frequency and phase discrimination is carried out according to the feedback signal exported with the voltage controlled oscillator array, and detects the embedded clock serial data
The difference of frequency/phase of frequency/phase and feedback signal when being more than predetermined threshold value, output control signal is to drive
State the first charge pump and the second charge pump startup so that the original frequency setting module is to the voltage controlled oscillator array
Initial voltage is provided and carries out frequency conversion, and then is mostly exported parallel data along sampling module by described.
Second aspect of the present invention provides control device, including embedded clock position and clock ce circuit, the clock CDR
Circuit includes：
Frequency and phase discrimination module, the second charge pump, original frequency setting module, voltage controlled oscillator array, is divided at the first charge pump
Frequency device and mostly along sampling module；
The receiving terminal of the frequency and phase discrimination module accesses embedded clock serial data, and the first of the frequency and phase discrimination module is defeated
Enter the output end for terminating the frequency divider, the second input of the frequency and phase discrimination module terminates the of the voltage controlled oscillator array
One output end, the first output end and second output terminal of the frequency and phase discrimination module connect first charge pump and described the simultaneously
Two charge pumps, the output of first charge pump terminate the input terminal of the original frequency setting module, second charge pump
Output terminate the output end of the original frequency setting module, the second output terminal of the voltage controlled oscillator array connects described point
The third output termination of the input terminal of frequency device, the voltage controlled oscillator array is described mostly along sampling module；
In the case of the frequency divider output frequency division signal, the frequency and phase discrimination module is to the embedded clock serial number
Frequency and phase discrimination is carried out according to the feedback signal exported with the voltage controlled oscillator array, and detects the embedded clock serial data
The difference of frequency/phase of frequency/phase and feedback signal when being more than predetermined threshold value, output control signal is to drive
State the first charge pump and the second charge pump startup so that the original frequency setting module is to the voltage controlled oscillator array
Initial voltage is provided and carries out frequency conversion, and then is mostly exported parallel data along sampling module by described.
Clock ce circuit and control device provided by the invention based on embedded clock position, by being divided in frequency divider
In the case of frequency acts, frequency and phase discrimination is carried out to embedding clock string row data and the feedback signal of voltage controlled oscillator array output,
And when detecting that the difference of the frequency/phase of embedded clock serial data and the frequency/phase of feedback signal is more than predetermined threshold value,
Output control signal is to drive the first charge pump and the second charge pump startup so that provides initial voltage to voltage controlled oscillator array
And frequency conversion is carried out, and then by mostly exporting parallel data along sampling module, increase reference frequency therefore without additional
Data clock recovery can be realized in signal wire, reduces system cost, while ensuring that CDR will not be locked at harmonic wave, solves
Existing clock CDR Line technologies there is need it is additional increase reference frequency signal line, cause circuit mixed and disorderly and increase
The problem of system cost.
Description of the drawings
Fig. 1 is the CDR structural schematic diagrams commonly used in the prior art based on phase-interpolation.
Fig. 2 is the modular structure schematic diagram of the clock ce circuit provided by the invention based on embedded clock position.
Fig. 3 is the exemplary circuit of frequency and phase discrimination module in the clock ce circuit provided by the invention based on embedded clock position
Figure.
Fig. 4 is the letter in frequency and phase discrimination module everywhere in the clock ce circuit provided by the invention based on embedded clock position
Number waveform diagram
Fig. 5 is the example of original frequency setting module in the clock ce circuit provided by the invention based on embedded clock position
Circuit diagram.
Fig. 6 is the circuit of original frequency setting module in the clock ce circuit provided by the invention based on embedded clock position
Simulation waveform.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
The above-mentioned clock ce circuit and control device based on embedded clock position, by increasing clock in data link
Position, and realized under conditions of no reference clock by specific CDR structures, carry out data clock recovery.It is thus achieved that
Reducing needs additional increased clock line to improve functional reliability to reduce system cost in traditional structure.It uses spy
Different circuit structure and system structure solves currently used phase-interpolation structure C DR and has to additional clock line with true
The problem of guarantor will not be locked in harmonic frequency has at low cost, high reliability, is highly suitable for the data of long range
Transmission, such as automobile display system, the application scenarios such as Central Information Display.
Fig. 2 shows the modular structures of the clock ce circuit provided by the invention based on embedded clock position, for the ease of saying
Bright, only the parts related to this embodiment are shown, and details are as follows：
The above-mentioned clock ce circuit based on embedded clock position, including frequency and phase discrimination module 201, the first charge pump 202,
Two charge pumps 203, original frequency setting module 204, voltage controlled oscillator array (Fig. 2 use VCO indicate) 205, frequency divider 207 with
And mostly along sampling module 206.
The receiving terminal of frequency and phase discrimination module 201 accesses embedded clock serial data, the first input of frequency and phase discrimination module 201
The output end of frequency divider 207 is terminated, the first of the second input termination voltage controlled oscillator array 205 of frequency and phase discrimination module 201 is defeated
Outlet, the first output end and second output terminal of frequency and phase discrimination module 201 connect the first charge pump 202 and the second charge pump simultaneously
203, the input terminal of the output termination original frequency setting module 204 of the first charge pump 202, the output end of the second charge pump 203
The output end of original frequency setting module 204 is connect, the second output terminal of voltage controlled oscillator array 205 connects the input of frequency divider 207
End, the third output termination of voltage controlled oscillator array 205 is mostly along sampling module 206.
In the case of 207 output frequency division signal of frequency divider, frequency and phase discrimination module 201 is to embedded clock string row data and pressure
It controls the feedback signal that oscillator array 205 exports and carries out frequency and phase discrimination, and detect the frequency/phase of embedded clock serial data
When being more than predetermined threshold value with the difference of the frequency/phase of feedback signal, output control signal is to drive the first charge pump 202 and the
Two charge pumps 203 start so that original frequency setting module 204 to voltage controlled oscillator array 205 provide initial voltage and into
Line frequency is converted, and then by mostly exporting parallel data along sampling module 206.
As an embodiment of the present invention, above-mentioned clock ce circuit further includes the first NOT gate NOT1 and the second NOT gate NOT2；Mirror
The input terminal of first the first NOT gate NOT1 of output termination of frequency phase demodulation module 201, the first electricity of output termination of the first NOT gate NOT1
The first input end of lotus pump 202, the second output terminal of frequency and phase discrimination module 201 connect the input terminal of the second NOT gate NOT2, and second is non-
Second input terminal of output the first charge pump 202 of termination of door NOT2.
As an embodiment of the present invention, above-mentioned clock ce circuit further includes the first capacitance C1, the second capacitance C2 and first
Switching tube Q1；The first termination reference voltage source of first capacitance C1, the second termination original frequency setting module of the first capacitance C1
204 input terminal, the first end of the second capacitance C2 and the controlled end of first switch pipe Q1 and original frequency setting module 204
Output end connects altogether, and the input termination voltage controlled oscillator array 205 of first switch pipe Q1, the second end of the second capacitance C2 is opened with first
Close the output end ground connection of pipe Q1.
Specifically, above-mentioned first switch pipe Q1 can be field-effect tube or triode.The grid of field-effect tube, drain electrode with
And source electrode corresponds to the controlled end, input terminal and output end of first switch pipe Q1 respectively；Base stage, collector and the hair of triode
Emitter-base bandgap grading corresponds to the controlled end, input terminal and output end of first switch pipe Q1 respectively.
As an embodiment of the present invention, above-mentioned frequency and phase discrimination module 201 is only carried out in the frequency dividing action of corresponding clock bit
Frequency and phase discrimination, and the frequency/phase difference for being detected frequency and phase discrimination module 201 by the second charge pump 203, are converted into electric current
Difference, and control voltage is formed on the second capacitance C2, to control the electric current of first switch pipe Q1.Meanwhile first charge pump 202 with
Second charge pump 203 works together, but reverse phase, the output current of the first charge pump 202 are directly injected into pressure to input signal each other
It controls in oscillator array 205, since voltage controlled oscillator array 205 is made of several ring oscillators, realizes broadband
Range exports.Wherein, frequency divider 207 is that the signal exported to voltage controlled oscillator array 205 divides, and frequency dividing ratio corresponds to clock
The data volume ratio of position and data-link carries out frequency and phase discrimination, when ensureing that voltage controlled oscillator array 205 is exported to realize in clock bit
Clock and alignment of data.In addition, original frequency setting module 204 is the attached initial voltages of Vtune so that voltage controlled oscillator array 205
Frequency from high frequency to low frequency move, it is ensured that will not be locked at harmonic wave.
Specifically, above-mentioned clock ce circuit is based on automatic biasing structure, and (Process is balanced by adjusting process stream
Flow Diagram, PFD) structure, so that system is only carried out frequency and phase discrimination operation at the clock bit of serial data.Therefore, it only needs
The proportionate relationship that control frequency divider frequency dividing ratio is accounted for clock bit in data link, you can realize the alignment of data and clock, it is real
Recovery now without reference clock data clock.
Fig. 3 shows the example of frequency and phase discrimination module in the clock ce circuit provided by the invention based on embedded clock position
Circuit, for convenience of description, only the parts related to this embodiment are shown, and details are as follows：
As an embodiment of the present invention, above-mentioned frequency and phase discrimination module 201 include the first trigger D1, the second trigger D2,
Third trigger D3, first and door AND1 and delay setting unit 301；
The input of first trigger D1 terminates reference voltage, and the clock end of the first trigger D1 accesses embedded clock serial number
According to, the reset terminal of the first trigger D1 connects altogether with the reset terminal of the second trigger D2 and the first end of delay setting unit 301,
The first input end of the output termination first and door AND1 of first trigger D1, the clock end of the second trigger D2 access feedback letter
Number, the second input terminal of the output termination first and door AND1 of the second trigger D2, the output of first and door AND1 terminates third
The clock end of the reset terminal of trigger D3, third trigger D3 accesses fractional frequency signal, the output termination delay of third trigger D3
The second end of setting unit 301.
Compared with traditional frequency and phase discrimination circuit, a delay setting unit 301 is increased in above-mentioned frequency and phase discrimination module 201
And third trigger D3, fractional frequency signal are the clock signal after frequency dividing.Fig. 4 is shown in frequency and phase discrimination module 201 everywhere
Signal waveforms (when leading time T1 is more than delay T0), job order is as follows：
1, RESET signal is 0 at the beginning, and the first trigger D1 and the second trigger D2 form most basic PFD, to embedded
Clock serial data carries out frequency and phase discrimination with feedback signal.
2, after completing a frequency and phase discrimination operation, the output Q combinations of the first trigger D1 and the second trigger D2 generate
RESET signal.First trigger D1 and the second trigger D2 are resetted.Since the CLK of third trigger D3 is after dividing
Clock signal, before fractional frequency signal does not occur, the first trigger D1 and the second trigger D2 will maintain RESET state.
3, the CLK signal input of third trigger D3 is that divided signal rising edge, the D3 outputs of third trigger occurs
It is low, the RESET of the first trigger D1 and the second trigger D2 are decontroled, is made of the first trigger D1 and the second trigger D2
PFD tasks again.Delay setting unit 301 can control the RESET times.
4, the operation of step 2 is repeated.
By above-mentioned flow, realizes and only the function that rising edge carries out frequency and phase discrimination occur in divided signal.
Fig. 5 and Fig. 6 respectively illustrates original frequency in the clock ce circuit provided by the invention based on embedded clock position and sets
The exemplary circuit and circuit simulation waveform of cover half block, for convenience of description, only the parts related to this embodiment are shown, is described in detail
It is as follows：
As an embodiment of the present invention, above-mentioned original frequency setting module 204 include first resistor R1, second resistance R2,
First transmission gate TG1, the second transmission gate TG2, second switch pipe Q2, third switching tube Q3 and the 4th switching tube Q4；
Input terminal of the input terminal of first transmission gate TG1 as original frequency setting module 204, the first transmission gate TG1's
The controlled end of output termination second switch pipe Q2, the input terminal of second switch pipe Q2 are referred to the input termination of third switching tube Q3
Voltage, the input terminal of the 4th switching tube Q4 of output termination of second switch pipe Q2, the first electricity of output termination of third switching tube Q3
Hinder the first end of R1, the first end of the second termination second resistance R2 of first resistor R1, the output end of the 4th switching tube Q4 and the
The second end of two resistance R2 is grounded, the input terminal of the second transmission gate of controlled termination TG2 of the 4th switching tube Q4, the second transmission gate
Output end of the output end of TG2 as original frequency setting module 204.
Specifically, above-mentioned second switch pipe Q2 can be field-effect tube or triode.The grid of field-effect tube, drain electrode with
And source electrode corresponds to the controlled end, input terminal and output end of second switch pipe Q2 respectively；Base stage, collector and the hair of triode
Emitter-base bandgap grading corresponds to the controlled end, input terminal and output end of second switch pipe Q2 respectively.Third switching tube Q3 and the 4th switching tube Q4
All similarly with second switch pipe Q2.
The operation principle of above-mentioned original frequency setting module 204 is：When EN is height, and ENB is low, third switching tube Q3 is led
Logical, first resistor R1 and second resistance R2 divide VDD, and Vtune voltages are pulled to first by the second transmission gate TG2 conductings
In the partial pressure value of resistance R1 and second resistance R2.The NMOS adjustment pipes of 4th switching tube Q4 mirror image voltage controlled oscillators array 205, the
Two switching tube Q2 mirror images PMOS adjustment pipes, make the voltage of second switch pipe Q2 work frequency corresponding with voltage controlled oscillator array 205
Rate VBP voltages are equal, and the first transmission gate TG1 is opened, and voltage is passed to VBP.
Partial pressure value size is set, ensures that Vtune point corresponding voltages can make the working frequency of voltage controlled oscillator array 205 high
Frequency is needed in locking.
When EN is low, when ENB is high, the Q3 shutdowns of third switching tube, the first transmission gate TG1 and the second transmission gate TG2 are turned off,
Original frequency setting module 204 decontrols Vtune and VBP, and Vtune voltages are controlled by loop.Since the initial value of setting is higher than lock
Fixed needs frequency, therefore loop will control CDR and be moved from high frequency to low frequency, prevent the case where being locked at harmonic wave.
The present invention also provides control devices, including embedded clock position and clock ce circuit as described above.
Below in conjunction with Fig. 1-Fig. 6 to above-mentioned based on the clock ce circuit of embedded clock position and the operation principle of control device
It is described：
First, data are restored based on embedded clock position, position when needing embedded in data-link a, it is assumed that number
According to packet 28, then the first and end is clock bit, permanent first place is 1, and end perseverance is 0, then valid data are 26.
It is 14 frequency dividings by the ratio setting of frequency divider according to the ratio of data bit and clock bit.Frequency and phase discrimination module in this way
201 will carry out frequency and phase discrimination at 14 frequency dividings of input clock frequency.(it is assumed to be lower edge while samples, the sampling frequency needed
Rate is the half of data transfer rate.Different according to sampling section structure, frequency divider frequency dividing ratio is as follows：)
One different data digit of table corresponds to frequency divider frequency dividing ratio
Then, design original frequency setting module 204 makes the original frequency of voltage controlled oscillator array 205 be needed higher than locking
The highest frequency wanted.
Then, frequency and phase discrimination module 201 work, since the frequency of voltage controlled oscillator array 205 is higher, control Vtune to
Stability at lower frequencies moves.
Finally, the frequency of voltage controlled oscillator array 205 continuously decreases, since frequency and phase discrimination module 201 is only in voltage controlled oscillation
Clock bit carries out frequency and phase discrimination, the final frequency for controlling CDR and being locked in voltage controlled oscillator array 205 at 14 frequency dividings of device array 205
Rate 14 divides the position overlapped with clock bit, and the frequency of voltage controlled oscillator array 205 is 14 times of clock bit frequency at this time.On if
Lower edge is sampled, and just each clock exports the phase needed along to homogeneous number evidence to voltage controlled oscillator array 205
It moves, mostly data is being sampled along sampling module 206, realize that data are restored.
To sum up, clock ce circuit and control device provided in an embodiment of the present invention based on embedded clock position, by dividing
In the case of frequency device carries out frequency dividing action, carried out to embedding clock string row data and the feedback signal of voltage controlled oscillator array output
Frequency and phase discrimination, and detect that the difference of the frequency/phase of embedded clock serial data and the frequency/phase of feedback signal is more than pre-
If when threshold value, output control signal is to drive the first charge pump and the second charge pump startup so that is carried to voltage controlled oscillator array
For initial voltage and frequency conversion is carried out, and then by mostly exporting parallel data along sampling module, increased therefore without additional
Add reference frequency signal line that data clock recovery can be realized, reduces system cost, while it is humorous to ensure that CDR will not be locked in
At wave, solves existing clock CDR Line technologies there is additional increase reference frequency signal line is needed, cause circuit mixed and disorderly
And the problem of increasing system cost.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (10)
1. a kind of clock ce circuit based on embedded clock position, which is characterized in that the clock ce circuit includes：
Frequency and phase discrimination module, the first charge pump, the second charge pump, original frequency setting module, voltage controlled oscillator array, frequency divider
And mostly along sampling module；
The receiving terminal of the frequency and phase discrimination module accesses embedded clock serial data, the first input end of the frequency and phase discrimination module
The output end of the frequency divider is connect, the first of the second input termination voltage controlled oscillator array of the frequency and phase discrimination module is defeated
Outlet, the first output end and second output terminal of the frequency and phase discrimination module connect first charge pump and second electricity simultaneously
Lotus pumps, and the output of first charge pump terminates the input terminal of the original frequency setting module, second charge pump it is defeated
Go out the output end for terminating the original frequency setting module, the second output terminal of the voltage controlled oscillator array connects the frequency divider
Input terminal, the voltage controlled oscillator array third output termination it is described mostly along sampling module；
In the case of the frequency divider output frequency division signal, the frequency and phase discrimination module to the embedded clock serial data with
The feedback signal of the voltage controlled oscillator array output carries out frequency and phase discrimination, and detects the frequency of the embedded clock serial data
When the difference of the frequency/phase of rate/phase and the feedback signal is more than predetermined threshold value, output control signal is to drive described the
One charge pump and the second charge pump startup so that the original frequency setting module provides the voltage controlled oscillator array
Initial voltage and frequency conversion is carried out, and then is mostly exported parallel data along sampling module by described.
2. clock ce circuit as described in claim 1, which is characterized in that the clock ce circuit further includes：
First NOT gate and the second NOT gate；
First output of the frequency and phase discrimination module terminates the input terminal of first NOT gate, the output termination of first NOT gate
The first input end of first charge pump, the second output terminal of the frequency and phase discrimination module connect the input of second NOT gate
End, the output of second NOT gate terminate the second input terminal of first charge pump.
3. clock ce circuit as described in claim 1, which is characterized in that the clock ce circuit further includes：
First capacitance, the second capacitance and first switch pipe；
The second termination original frequency of the first termination reference voltage source of first capacitance, first capacitance sets mould
The input terminal of block, the first end of second capacitance set mould with the controlled end of the first switch pipe and the original frequency
The output end of block connects altogether, the input termination voltage controlled oscillator array of the first switch pipe, and the second of second capacitance
End and the output end of the first switch pipe are grounded.
4. clock ce circuit as described in claim 1, which is characterized in that the frequency and phase discrimination module includes：
First trigger, the second trigger, third trigger, first and door and delay setting unit；
The input of first trigger terminates reference voltage, and the clock end of first trigger accesses the embedded clock string
The of row data, the reset terminal of the reset terminal of first trigger and second trigger and the delay setting unit
One end connects altogether, output termination described first and the first input end of door of first trigger, second trigger when
Clock is terminated into the feedback signal, the second input terminal of the output termination described first and door of second trigger, and described the
One terminates the reset terminal of the third trigger with the output of door, and the clock end of the third trigger accesses the frequency dividing letter
Number, the second end of the output termination delay setting unit of the third trigger.
5. clock ce circuit as described in claim 1, which is characterized in that the original frequency setting module includes：
First resistor, second resistance, the first transmission gate, the second transmission gate, second switch pipe, third switching tube and the 4th switch
Pipe；
Input terminal of the input terminal of first transmission gate as the original frequency setting module, first transmission gate it is defeated
Go out the controlled end for terminating the second switch pipe, the input terminal of the second switch pipe and the input of the third switching tube terminate
Reference voltage, the output of the second switch pipe terminate the input terminal of the 4th switching tube, the output of the third switching tube
Terminate the first end of the first resistor, the first end of the second termination second resistance of the first resistor, the described 4th
The output end of switching tube and the second end of the second resistance are grounded, controlled termination second transmission of the 4th switching tube
The input terminal of door, the output end of the output end of second transmission gate as the original frequency setting module.
6. a kind of control device, including embedded clock position and clock ce circuit, which is characterized in that the clock ce circuit packet
It includes：
Frequency and phase discrimination module, the first charge pump, the second charge pump, original frequency setting module, voltage controlled oscillator array, frequency divider
And mostly along sampling module；
The receiving terminal of the frequency and phase discrimination module accesses embedded clock serial data, the first input end of the frequency and phase discrimination module
The output end of the frequency divider is connect, the first of the second input termination voltage controlled oscillator array of the frequency and phase discrimination module is defeated
Outlet, the first output end and second output terminal of the frequency and phase discrimination module connect first charge pump and second electricity simultaneously
Lotus pumps, and the output of first charge pump terminates the input terminal of the original frequency setting module, second charge pump it is defeated
Go out the output end for terminating the original frequency setting module, the second output terminal of the voltage controlled oscillator array connects the frequency divider
Input terminal, the voltage controlled oscillator array third output termination it is described mostly along sampling module；
In the case of the frequency divider output frequency division signal, the frequency and phase discrimination module to the embedded clock serial data with
The feedback signal of the voltage controlled oscillator array output carries out frequency and phase discrimination, and detects the frequency of the embedded clock serial data
When the difference of the frequency/phase of rate/phase and the feedback signal is more than predetermined threshold value, output control signal is to drive described the
One charge pump and the second charge pump startup so that the original frequency setting module provides the voltage controlled oscillator array
Initial voltage and frequency conversion is carried out, and then is mostly exported parallel data along sampling module by described.
7. control device as claimed in claim 6, which is characterized in that the clock ce circuit further includes：
First NOT gate and the second NOT gate；
First output of the frequency and phase discrimination module terminates the input terminal of first NOT gate, the output termination of first NOT gate
The first input end of first charge pump, the second output terminal of the frequency and phase discrimination module connect the input of second NOT gate
End, the output of second NOT gate terminate the second input terminal of first charge pump.
8. control device as claimed in claim 6, which is characterized in that the clock ce circuit further includes：
First capacitance, the second capacitance and first switch pipe；
The second termination original frequency of the first termination reference voltage source of first capacitance, first capacitance sets mould
The input terminal of block, the first end of second capacitance set mould with the controlled end of the first switch pipe and the original frequency
The output end of block connects altogether, the input termination voltage controlled oscillator array of the first switch pipe, and the second of second capacitance
End and the output end of the first switch pipe are grounded.
9. control device as claimed in claim 6, which is characterized in that the frequency and phase discrimination module includes：
First trigger, the second trigger, third trigger, first and door and delay setting unit；
The input of first trigger terminates reference voltage, and the clock end of first trigger accesses the embedded clock string
The of row data, the reset terminal of the reset terminal of first trigger and second trigger and the delay setting unit
One end connects altogether, output termination described first and the first input end of door of first trigger, second trigger when
Clock is terminated into the feedback signal, the second input terminal of the output termination described first and door of second trigger, and described the
One terminates the reset terminal of the third trigger with the output of door, and the clock end of the third trigger accesses the frequency dividing letter
Number, the second end of the output termination delay setting unit of the third trigger.
10. control device as claimed in claim 6, which is characterized in that the original frequency setting module includes：
First resistor, second resistance, the first transmission gate, the second transmission gate, second switch pipe, third switching tube and the 4th switch
Pipe；
Input terminal of the input terminal of first transmission gate as the original frequency setting module, first transmission gate it is defeated
Go out the controlled end for terminating the second switch pipe, the input terminal of the second switch pipe and the input of the third switching tube terminate
Reference voltage, the output of the second switch pipe terminate the input terminal of the 4th switching tube, the output of the third switching tube
Terminate the first end of the first resistor, the first end of the second termination second resistance of the first resistor, the described 4th
The output end of switching tube and the second end of the second resistance are grounded, controlled termination second transmission of the 4th switching tube
The input terminal of door, the output end of the output end of second transmission gate as the original frequency setting module.
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| CN201810441738.XA CN108599759B (en) | 2018-05-10 | 2018-05-10 | Clock CDR circuit based on embedded clock bit and control device |
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| CN201810441738.XA CN108599759B (en) | 2018-05-10 | 2018-05-10 | Clock CDR circuit based on embedded clock bit and control device |
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| CN108599759B CN108599759B (en) | 2022-09-30 |
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| CN115714596A (en) * | 2022-10-25 | 2023-02-24 | 北京显芯科技有限公司 | Clock data recovery circuit, display chip and display device |
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| CN108599759B (en) | 2022-09-30 |
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