CN112052043B - Method, device, equipment and storage medium for adapting memory bank parameters of embedded system - Google Patents
Method, device, equipment and storage medium for adapting memory bank parameters of embedded system Download PDFInfo
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- CN112052043B CN112052043B CN202010796412.6A CN202010796412A CN112052043B CN 112052043 B CN112052043 B CN 112052043B CN 202010796412 A CN202010796412 A CN 202010796412A CN 112052043 B CN112052043 B CN 112052043B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
Abstract
The invention discloses a method, a device, equipment and a storage medium for adapting parameters of a memory bank of an embedded system, wherein the method comprises the steps of acquiring memory bank information of target memory banks of different types, and acquiring the routing length of a clock and data on the memory bank from a DIMM (double-address-memory) to the memory bank of each memory particle according to the memory bank information; acquiring the routing length of the clock and the data on the PCB from the CPU to the PCB of the DIMM according to the PCB information, wherein the sum of the routing length on the memory bank and the routing length on the PCB is the total routing length between the clock and the data from the CPU to each memory particle; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and enabling the embedded system to automatically adapt to the target memory bank according to the time sequence parameter; the embedded system can be automatically adapted to different types of memory banks, the stability of the system is improved, the range of the memory banks adapted to the system is enlarged, the flexibility of the memory adaptation of the system is improved, and the work production efficiency is improved.
Description
Technical Field
The present invention relates to the field of embedded hardware, and in particular, to a method, an apparatus, a device, and a storage medium for adapting memory bank parameters of an embedded system.
Background
With the increasing performance requirements of embedded systems, the requirements for the size and speed of the system memory are also increasing, which requires that a larger number of memory particles are used, and the area of a Printed Circuit Board (PCB) of a motherboard is not increased with the increasing number of memory particles, so that the memory bank can be used as a storage medium of the dynamic memory of the system under the condition that the area of the PCB of the motherboard is limited.
From the design experience of attaching memory granules in an embedded Reduced Instruction Set Computer (RISC) RISC microprocessor (ARM) system, even if the schematic design is the same, if any one of the layout and routing of the memory granules is changed, the phase relationship between the memory clock and the data needs to be adjusted.
However, even if the information of the memory banks is the same, the memory banks have different designs, that is, the daisy chain topology fly-by of the memory banks is different, and the layout and routing of the memory particles are different, so that the timing sequence parameters between the clock and the data need to be adjusted, and thus different memory banks can cause the problem that the memory banks cannot be normally adapted in the embedded system.
Disclosure of Invention
The invention mainly aims to provide a method, a device, equipment and a storage medium for adapting memory bank parameters of an embedded system, and aims to solve the technical problem that different memory banks cannot be normally adapted in the embedded system in the prior art.
In a first aspect, the present invention provides a method for adapting parameters of a memory bank of an embedded system, where the method for adapting parameters of a memory bank of an embedded system includes the following steps:
acquiring memory bar information of different types of target memory bars, and acquiring the routing length of a clock and data on the memory bar from a dual in-line memory module (DIMM) to the memory bar of each memory particle according to the memory bar information;
acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB;
and calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Optionally, the obtaining memory chip information of different types of target memory chips, and obtaining the routing length of the clock and data on the memory chip from the dual inline memory module DIMM to the memory chip of each memory granule according to the memory chip information, includes:
obtaining memory bank information of different types of target memory banks;
acquiring reference design original card information from the memory bank information;
screening information in the reference design original card information to obtain a daisy chain topology fly-by topological structure;
and acquiring the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by topological structure.
Optionally, the obtaining of the routing length of the clock and the data from the dual inline memory module DIMM to the memory stripe of each memory granule according to the fly-by topology includes:
acquiring a fly-by wiring sequence of the clock according to the fly-by topological structure;
and determining the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by routing sequence.
Optionally, the determining, according to the fly-by routing sequence, a routing length of a clock and data from the dual inline memory module DIMM to a memory stripe of each memory granule includes:
determining the phase relation between the signal flow direction of the clock and the data according to the fly-by routing sequence;
determining the clock routing length of a clock from the dual in-line memory module (DIMM) to each memory grain according to the phase relation;
determining the data routing length of data from the DIMM to each memory grain according to the phase relation;
and taking the clock routing length and the data routing length as the routing length on the memory bank.
Optionally, the screening the information in the reference design original card information to obtain a daisy chain topology fly-by topology structure includes:
obtaining the model and the version of the reference original card from the reference design original card information;
acquiring JEDEC specifications corresponding to the model and version of the reference original card;
and determining a corresponding daisy chain topology fly-by topology structure according to the JEDEC specification.
Optionally, the calculating, according to a preset configuration algorithm, a timing parameter corresponding to the total track length, and writing the timing parameter into a memory parameter configuration program of an embedded system, so that the embedded system automatically adapts to the target memory bank includes:
obtaining the total length of clock routing and the total length of data routing from the total length of routing, and calculating to obtain the difference of the total length of the clock routing and the total length of the data routing;
acquiring time delay corresponding to the routing length difference, and acquiring DDR working speed from CPU configuration parameters of the embedded system;
determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat;
compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length;
and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Optionally, writing the timing parameter into a memory parameter configuration program of an embedded system, so that the embedded system automatically adapts to the target memory bank, including:
and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system reads a target model and a target version of memory bank information of the target memory bank, searching for a corresponding target time sequence parameter according to the target model and the target version, and initializing the target memory bank according to the target time sequence parameter to complete adaptation of the target memory bank.
In a second aspect, the present invention further provides an embedded system memory parameter adapting device, where the embedded system memory parameter adapting device includes:
the data acquisition module is used for acquiring memory chip information of different types of target memory chips and acquiring the routing length of a clock and data on the memory chip from a dual in-line memory module (DIMM) to the memory chip of each memory particle according to the memory chip information;
the length determining module is used for acquiring the routing length of the clock and the data on the PCB from the CPU to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB;
and the adaptation module is used for calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system automatically adapts to the target memory bank.
In a third aspect, the present invention further provides an embedded system memory parameter adapting device, where the embedded system memory parameter adapting device includes: the memory comprises a memory, a processor and an embedded system memory bank parameter adaptation program which is stored on the memory and can run on the processor, wherein the embedded system memory bank parameter adaptation program is configured to realize the steps of the embedded system memory bank parameter adaptation method.
In a fourth aspect, the present invention further provides a storage medium, where an embedded system memory bank parameter adaptation program is stored on the storage medium, and when executed by a processor, the embedded system memory bank parameter adaptation program implements the steps of the embedded system memory bank parameter adaptation method described above.
The method for adapting the parameters of the memory bank of the embedded system comprises the steps of acquiring the memory bank information of target memory banks of different types, and acquiring the routing length of a clock and data on the memory bank from a dual in-line memory module (DIMM) to the memory bank of each memory particle according to the memory bank information; acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank; by calculating the time sequence parameters of different types of memory banks in advance, the embedded system can be automatically adapted to the different types of memory banks, the target memory can be quickly and accurately adapted efficiently, the system stability is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of an apparatus architecture of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a first embodiment of a method for adapting memory bank parameters of an embedded system according to the present invention;
FIG. 3 is a flowchart illustrating a second embodiment of a method for adapting memory bank parameters of an embedded system according to the present invention;
FIG. 4 is a flowchart illustrating a method for adapting memory bank parameters of an embedded system according to a third embodiment of the present invention;
FIG. 5 is a flowchart illustrating a fourth embodiment of a method for adapting memory bank parameters of an embedded system according to the present invention;
FIG. 6 is a flowchart illustrating a fifth embodiment of a method for adapting memory bank parameters of an embedded system according to the present invention;
FIG. 7 is a flowchart illustrating a sixth embodiment of a method for adapting memory bank parameters of an embedded system according to the present invention;
FIG. 8 is a functional block diagram of a memory parameter adapting device of an embedded system according to a first embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The solution of the embodiment of the invention is mainly as follows: acquiring the routing length of a clock and data on a memory bank from a dual in-line memory module (DIMM) to the memory bank of each memory particle according to the memory bank information by acquiring the memory bank information of different types of target memory banks; acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank; by calculating the time sequence parameters of different types of memory banks in advance, the embedded system can be automatically adapted to the different types of memory banks, the target memory can be efficiently and accurately quickly adapted, the system stability is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, the work production efficiency is improved, and the technical problem that different memory banks cannot be normally adapted in the embedded system in the prior art is solved.
Referring to fig. 1, fig. 1 is a schematic device structure diagram of a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the apparatus may include: a processor 1001, such as a CPU, a communication bus 1002, a user side interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., a Wi-Fi interface). The Memory 1005 may be a high-speed RAM Memory or a Non-Volatile Memory (Non-Volatile Memory), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration of the apparatus shown in fig. 1 is not intended to be limiting of the apparatus and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, the storage 1005 as a storage medium may include an operating device, a network communication module, a client interface module, and an embedded system memory parameter adapting program.
The device calls an embedded system memory parameter adaptation program stored in a storage 1005 through a processor 1001, and executes the following operations:
acquiring memory bar information of different types of target memory bars, and acquiring the routing length of a clock and data on the memory bar from a dual in-line memory module (DIMM) to the memory bar of each memory particle according to the memory bar information;
acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB;
and calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Further, the processor 1001 may call the embedded system memory bank parameter adaptation program stored in the storage 1005, and further perform the following operations:
obtaining memory bank information of different types of target memory banks;
acquiring reference design original card information from the memory bank information;
screening information in the reference design original card information to obtain a daisy chain topology fly-by topological structure;
and acquiring the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by topological structure.
Further, the processor 1001 may call the embedded system memory parameter adaptation program stored in the storage 1005, and further perform the following operations:
acquiring a fly-by wiring sequence of the clock according to the fly-by topological structure;
and determining the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by routing sequence.
Further, the processor 1001 may call the embedded system memory parameter adaptation program stored in the storage 1005, and further perform the following operations:
determining the phase relation between the signal flow direction of the clock and the data according to the fly-by routing sequence;
determining the clock routing length of a clock from the dual in-line memory module (DIMM) to each memory grain according to the phase relation;
determining the data routing length of data from the DIMM to each memory grain according to the phase relation;
and taking the clock routing length and the data routing length as the routing length on the memory bank.
Further, the processor 1001 may call the embedded system memory parameter adaptation program stored in the storage 1005, and further perform the following operations:
obtaining the model and the version of the reference original card from the reference design original card information;
acquiring JEDEC specifications corresponding to the model and version of the reference original card;
and determining a corresponding daisy chain topology fly-by topology structure according to the JEDEC specification.
Further, the processor 1001 may call the embedded system memory parameter adaptation program stored in the storage 1005, and further perform the following operations:
obtaining the total length of clock routing and the total length of data routing from the total length of routing, and calculating to obtain the difference of the total length of the clock routing and the total length of the data routing;
acquiring time delay corresponding to the routing length difference value, and acquiring DDR working speed from CPU configuration parameters of the embedded system;
determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat;
compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length;
and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Further, the processor 1001 may call the embedded system memory parameter adaptation program stored in the storage 1005, and further perform the following operations:
and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system reads a target model and a target version of memory bank information of the target memory bank, searching for a corresponding target time sequence parameter according to the target model and the target version, and initializing the target memory bank according to the target time sequence parameter to complete adaptation of the target memory bank.
According to the scheme, the method comprises the steps that the line length from a dual in-line memory module (DIMM) to the memory bank of each memory particle of the memory bank is obtained according to the memory bank information by obtaining the memory bank information of different types of target memory banks; acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank; by calculating the time sequence parameters of different types of memory banks in advance, the embedded system can be automatically adapted to the different types of memory banks, the target memory can be quickly and accurately adapted efficiently, the system stability is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
Based on the hardware structure, the embodiment of the memory bank parameter adaptation method of the embedded system is provided.
Referring to fig. 2, fig. 2 is a flowchart illustrating a first embodiment of a memory stripe parameter adaptation method of an embedded system according to the present invention.
In a first embodiment, the method for adapting memory parameter of an embedded system includes the following steps:
step S10, obtaining the memory bar information of different types of target memory bars, and obtaining the wiring length of the clock and data on the memory bar from the dual in-line memory module DIMM to the memory bar of each memory grain according to the memory bar information.
It should be noted that different memory banks may have different memory bank information, and the memory bank information has many kinds, including but not limited to: the memory type, the number of memory chip sets rank, whether there is Error Correcting Code (ECC), data input and output pin Mapping DQ Mapping settings, whether there is mirror image, the memory grain size, bit width, row address number, column address number, and timing parameters between the memory clock and data, and other information.
It can be understood that the Memory bank information is recorded in the module configuration information (SPD) of the Memory bank, the CPU reads all information of the SPD through a low speed interface, usually an Integrated Circuit bus (IIC) interface, and after obtaining the Memory bank information of the Memory banks of different types, the CPU can obtain the trace length of the clock and data from the Dual-Inline Memory module (DIMM) to the Memory bank of each Memory granule from the Memory bank information.
In a specific implementation, the layout and routing of memory granules are different due to different daisy chain topology fly-by structures of the memory strips, and the routing length of a Clock (Clock, CLK)/Command (Command, CMD)/Address (Address, ADDR) signal from a connector of the DIMM to each granule on the DIMM is different, generally, the routing length of the CLK/CMD/ADDR signal from the first granule to each granule is gradually increased, but the routing length of a Data input pin, a Data output pin DQ, a bidirectional Data control pin (B i-bidirectional Data Strobe, DQs) from the connector of the DIMM to each granule on the DIMM is basically the same, or the difference of the routing length of DQ (DQs) is not as large as that of the CLK/CMD/ADDR, so that on the fly-by granules, the Clock (CLK) and the Data (DQ, CMD/by granules, DQS) are increasingly more and more dissimilar; that is, the time to the memory data of each grain is approximately the same, but the time to the memory clock of each grain is separated by a certain time, the data sampling of each grain is again based on the clock, because the time of the clock reaching each grain is different, the sampling time point of each group of data is also different, which is to sample 32bit or 64bit data at the same time, but because the time of the clock reaching each grain is different, the error sampling data appears at different times of data sampling.
Step S20, obtaining the length of the clock and data on the PCB from the CPU to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total length of the trace between the CPU and the clock and data of each memory particle according to the sum of the length of the trace on the memory strip and the length of the trace on the PCB.
It should be understood that the length of the traces on the PCB from the CPU to the DIMM on the PCB is the length of the traces from the CPU to the DIMM connector on the PCB, and the total length of the traces from the CPU to each memory particle can be calculated according to the length of the traces on the memory stripe and the length of the traces on the PCB.
Step S30, calculating a timing parameter corresponding to the total track length according to a preset configuration algorithm, and writing the timing parameter into a memory parameter configuration program of an embedded system, so that the embedded system automatically adapts to the target memory bank.
It can be understood that the preset configuration algorithm is a preset algorithm corresponding to mapping relationships between different trace lengths and different timing parameters, and generally, the preset configuration algorithm may be recorded in software or a calculation module for memory parameter configuration, and a timing parameter corresponding to the total trace length is calculated.
According to the scheme, the method comprises the steps that the line length from a dual in-line memory module (DIMM) to the memory bank of each memory particle of the memory bank is obtained according to the memory bank information by obtaining the memory bank information of different types of target memory banks; acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank; by calculating the time sequence parameters of different types of memory banks in advance, the embedded system can be automatically adapted to the different types of memory banks, the target memory can be quickly and accurately adapted efficiently, the system stability is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
Further, fig. 3 is a schematic flowchart of a second embodiment of the method for adapting memory bank parameters of an embedded system according to the present invention, and as shown in fig. 3, the second embodiment of the method for adapting memory bank parameters of an embedded system according to the present invention is proposed based on the first embodiment, in this embodiment, the step S10 specifically includes the following steps:
and step S11, acquiring the memory bank information of the target memory banks of different types.
It should be noted that, generally, the memory bank information included in the memory banks of different types, for example, different main frequencies and capacities, different memory bank design structures, and the like; the preparation for the subsequent embedded system to automatically adapt to the different types of memory banks can be made by acquiring the information of the different memory banks, the information of the memory banks can be read out through a low-speed interface of the CPU, and certainly, the information of the memory banks can be acquired through an interface or other manners, which is not limited in this embodiment.
And step S12, obtaining the reference design original card information from the memory bank information.
It can be understood that the reference design source card information is reference design source card information in a memory bank specified in Joint Electronic Device Engineering Council (JEDEC) standard, and in this embodiment, the reference design source card information may be JEDEC specifications corresponding to types and versions of reference design source cards corresponding to the memory bank.
In the specific implementation, taking a DDR4 type Small Outline Dual In-line Memory Module (SODIMM) as an example, a JEDEC standard (JEDEC 21-C) of a DDR4 SPD specifies that Byte128 and Byte130 represent reference raw card information of a Memory bank, namely reference design original card information, bits 4-0 of the Byte130 represent the model of the reference raw card, differences of A-AL and AM-CB exist, bits 6-5 represent versions 0-3 of the reference raw card, if the difference exceeds 0-3, bits 6-5 are also set to 11, then the definition of the Byte128 needs to be seen, and bits 7-5 In the Byte128 represent extended versions 4-10 of the reference raw card; the combination of Byte128 and Byte130 indicates the model number and version of the reference raw card; for example, type A and version 0 of reference raw card constitute reference raw card A0, R/C A0; the type D and version 1 of the reference raw card constitute reference raw card D1, R/C D1 for short.
For Memory banks of the types such as the SODIMM, a Dual-Line Memory module with a Register (RDIMM), an Unbuffered Dual In-Line Memory module or an Unbuffered Dual In-Line Memory module (UDIMM), a Load Dual-Line Memory module (Load-Reduced DIMM, LRDIMM) and the like, the Memory banks have respective types such as R/C A1 or R/C D1; taking reference raw card D1 of DDR4 SDOIMM as an example, there is also a specific JEDEC specification (4_20_25_ AnnexDR28), which specifies that a memory bank of reference raw card D1 type has 1 rank, and includes 9 memory banks, each memory bank being data bit wide of x8, and so on, as main configuration information of basic modules.
And step S13, screening the information in the reference design original card information to obtain a daisy chain topology fly-by topology structure.
It should be understood that through in-depth analysis of the reference design raw card information, a daisy chain topology fly-by topology can be obtained.
It should be noted that, a plurality of high-speed storage devices are often involved in a high-speed circuit, so a reasonable topology structure is very important for layout and routing, and the mainstream topology modes include daisy chain, fly-by and T-type; daisy chaining is a relatively common topology, and the principle of daisy chain topology can be explained as follows: all buses are taken as topological trunk lines, after the buses are led out from a processor, buses required by each storage device are taken as branch lines, from the viewpoint of microcomputer principle, all buses are taken as a 'big bus', and when each memory device needs a bus, a data bus, an address bus and a control bus required by the memory device are directly led in from the 'big bus'; the fly-by topology is a special case in daisy chain topologies; when a branch in a daisy chain topology is rather short, it may be referred to as "fly-by".
Further, the step S13 specifically includes the following steps:
obtaining the model and the version of the reference original card from the reference design original card information;
acquiring JEDEC specifications corresponding to the model and version of the reference original card;
and determining a corresponding daisy chain topology fly-by topology structure according to the JEDEC specification.
It should be understood that different reference design raw card information will record the model and version of the reference raw card, different models and versions will correspond to different JEDEC specifications, and each JEDEC specification will have a corresponding daisy-chain topology fly-by topology.
And step S14, acquiring the routing length of the clock and the data from the Dual Inline Memory Module (DIMM) to the memory strip of each memory grain according to the fly-by topological structure.
It should be understood that the relationship between the clock flow and the data can be made explicit by the fly-by topology, so as to calculate the trace length of the clock and the data from the dual inline memory module DIMM to the memory stripe of each memory granule.
According to the scheme, the memory bank information of different types of target memory banks is acquired; acquiring reference design original card information from the memory bank information; screening information in the reference design original card information to obtain a daisy chain topology fly-by topological structure; the method has the advantages that the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle is obtained according to the fly-by topological structure, the routing length of the clock and the data from the DIMM to each particle can be accurately obtained, the speed of calculating the routing length is improved by obtaining the information of the reference design original card meeting the JEDEC standard regulation, the condition that the sampling data of the routing length has larger errors due to errors in the data sampling process is avoided, and the stability of an embedded system is indirectly improved.
Further, fig. 4 is a schematic flowchart of a third embodiment of the method for adapting memory parameters of an embedded system according to the present invention, and as shown in fig. 4, the third embodiment of the method for adapting memory parameters of an embedded system according to the present invention is proposed based on the second embodiment, in this embodiment, the step S14 specifically includes the following steps:
and S141, acquiring a fly-by wiring sequence of the clock according to the fly-by topological structure.
It should be noted that different fly-by topologies have different routing sequences, that is, a routing sequence corresponding to a flow direction from a clock to each memory particle and a flow direction from data to each memory particle can be obtained by the fly-by topologies.
And S142, determining the wiring length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory grain according to the fly-by wiring sequence.
It can be understood that after the fly-by trace sequence is determined, the trace length from the DIMM to the memory stripe of each memory granule can be determined by sequentially calculating the trace length through the trace sequence.
According to the scheme, the fly-by wiring sequence of the clock is obtained according to the fly-by topological structure; the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle is determined according to the fly-by routing sequence, the routing length of the clock and the data from the DIMM to each particle can be obtained, the speed of routing length calculation is improved, the condition that errors in the data sampling process cause large errors in the routing length sampling data is avoided, and the stability of the embedded system is indirectly improved.
Further, fig. 5 is a schematic flowchart of a fourth embodiment of the method for adapting memory bank parameters of an embedded system according to the present invention, and as shown in fig. 5, the fourth embodiment of the method for adapting memory bank parameters of an embedded system according to the present invention is proposed based on the third embodiment, in this embodiment, the step S142 specifically includes the following steps:
step S1421, determining a phase relationship between the signal flow direction of the clock and the data according to the fly-by routing sequence.
It should be noted that when the routing of the memory grain changes, the phase relationship between the memory clock and the data also changes correspondingly, and the phase relationship between the signal flow direction of the clock and the data can be determined through the fly-by routing sequence.
Step S1422, determining the clock routing length of the clock from the Dual Inline Memory Module (DIMM) to each memory granule according to the phase relation.
It will be appreciated that the individual stubs of the clock from the DIMM to each memory die can be determined by the phase relationship, and the clock trace length of the clock from the DIMM to each memory die can be determined by calculating the sum of the individual stubs.
Step S1423, determining the data routing length from the DIMM to each memory granule according to the phase relationship.
It should be understood that the individual stubs of data from the DIMM to each memory die can be determined by the phase relationship, and the data trace length of data from the DIMM to each memory die can be determined by calculating the sum of the individual stubs.
Step S1424, the clock trace length and the data trace length are used as the trace length on the memory chip.
It can be understood that when the routing of the memory particles changes, the phase relationship between the memory clock and the data also changes correspondingly, and the phase relationship between the signal flow direction of the clock and the data can be determined through the fly-by routing sequence; the routing length from the DIMM to each memory grain of the clock and the routing length from the data to each memory grain can be obtained through the phase relation, and then the set of the clock routing length and the data routing length can be used as the routing length on the memory bank.
In specific implementation, a common clock is used for each memory particle, and the routing length from data to each memory particle is also specified in the JEDEC specification, that is, the routing length can be obtained by searching for relevant specifications, and the routing data of the clock and the data can be obtained from a main board PCB file, so as to obtain the routing length.
According to the scheme, the phase relation between the signal flow direction of the clock and the data is determined according to the fly-by routing sequence; determining the clock routing length of a clock from the dual in-line memory module (DIMM) to each memory grain according to the phase relation; determining the data routing length of data from the DIMM to each memory grain according to the phase relation; taking the clock routing length and the data routing length as the routing length on the memory bank; the method can obtain the routing length of the clock and the data from the DIMM to each particle, improves the speed of routing length calculation, avoids the condition that errors in the data sampling process cause large errors in the routing length sampling data, and indirectly improves the stability of the embedded system.
Further, fig. 6 is a schematic flowchart of a fifth embodiment of the method for adapting memory parameters of an embedded system according to the present invention, and as shown in fig. 6, the fifth embodiment of the method for adapting memory parameters of an embedded system according to the present invention is proposed based on the first embodiment, and in this embodiment, the step S30 specifically includes the following steps:
step S31, obtaining a total clock trace length and a total data trace length from the total trace length, and calculating a trace length difference between the total clock trace length and the total data trace length.
It is understood that the trace length difference is the total clock trace length minus the total data trace length, and generally, the unit of the trace length difference is mil.
And step S32, acquiring the time delay corresponding to the routing length difference, and acquiring the DDR working speed from the CPU configuration parameters of the embedded system.
It should be noted that, the advantage of using the fly-by topology is that the trace via and the length can be reduced, but signal delay between the clock and the data can be caused, that is, signal delay caused by trace difference caused by the topology, so that corresponding time delay can be determined by calculating the trace length difference between the total length of the clock trace and the total length of the data trace, and generally can be determined by conversion between the length and the delay time, or can be determined by other manners, which is not limited in this embodiment.
It should be understood that the CPU configuration parameters of the embedded system store a DDR operating rate, which is generally in units of MT/s.
And step S33, determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat.
It is understood that the minimum beat is the minimum beat of the timing parameter, the minimum beat can be determined by the DDR operating rate, generally, the frequency of the clock CLK is half of the DDR operating rate, the minimum beat is generally CLK/8, the minimum beat is related to the DDR operating rate, and the number of beats between time and data can be determined by the ratio of the time delay to the minimum beat, that is, the ratio of the time delay divided by the minimum beat is the number of beats between time and data.
And step S34, compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length.
It should be noted that, according to the experience of the CPU of the embedded system, the data signal of each memory particle arrives in advance of the clock signal by half a cycle, where the half cycle is 4 beats, and the 4 beats are the preset beat compensation value, the beat number can be compensated by the preset beat compensation value, that is, the beat number to be adjusted is increased by 4, and the compensated beat is subjected to hexadecimal conversion, so as to obtain the timing parameter corresponding to the total length of the trace.
In the specific implementation, because the read-write data values of the CPU register are hexadecimal, the calculated adjustment cycle number is generally rounded up in a rounding manner, and the hexadecimal value obtained by conversion is filled in the DDR register of the CPU.
Step S35, writing the timing parameter into a memory parameter configuration program of the embedded system, so that the embedded system automatically adapts to the target memory bank.
It should be understood that, by writing the timing parameter into the memory parameter configuration program of the embedded system, fast adaptation can be realized during subsequent memory bank embedding, and the embedded system can automatically adapt to different types of memory banks due to the fact that parameter configurations of different types of memory banks are recorded.
In this embodiment, by using the above scheme, the total length of the clock traces and the total length of the data traces are obtained from the total lengths of the traces, and a trace length difference between the total length of the clock traces and the total length of the data traces is obtained through calculation; acquiring time delay corresponding to the routing length difference, and acquiring DDR working speed from CPU configuration parameters of the embedded system; determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat; compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length; the time sequence parameters are written into a memory parameter configuration program of the embedded system, so that the embedded system is automatically adapted to the target memory bank, the embedded system can be automatically adapted to different types of memory banks, the rapid adaptation of the target memory is efficiently and accurately realized, the stability of the system is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
Further, fig. 7 is a flowchart illustrating a sixth embodiment of a memory parameter adaptation method for an embedded system according to the present invention, and as shown in fig. 7, the sixth embodiment of the memory parameter adaptation method for an embedded system according to the present invention is proposed based on the fifth embodiment, in this embodiment, the step S35 specifically includes the following steps:
step S351, writing the timing parameter into a memory parameter configuration program of an embedded system, so that the embedded system reads a target model and a target version of memory bank information of the target memory bank, searches for a corresponding target timing parameter according to the target model and the target version, and initializes the target memory bank according to the target timing parameter, thereby completing adaptation of the target memory bank.
It should be noted that, after the memory parameter configuration program in the embedded system stores the timing parameters of different memory banks, and after the memory bank information of a target memory bank is obtained, a target timing parameter corresponding to a target model and a target version may be determined, and then the target memory bank may be initialized according to the target timing parameter to complete the adaptation of the target memory bank.
According to the scheme, the time sequence parameters are written into the memory parameter configuration program of the embedded system, so that the embedded system reads the target model and the target version of the memory bank information of the target memory bank, searches for the corresponding target time sequence parameters according to the target model and the target version, and initializes the target memory bank according to the target time sequence parameters, so that the target memory bank is adapted, the embedded system can be automatically adapted to different types of memory banks, the fast adaptation of the target memory is efficiently and accurately realized, the stability of the system is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
Correspondingly, the invention further provides a device for adapting the memory bank parameters of the embedded system.
Referring to fig. 8, fig. 8 is a functional block diagram of a memory parameter adapting device of an embedded system according to a first embodiment of the present invention.
In a first embodiment of the present invention, the device for adapting parameters of a memory bank of an embedded system comprises:
the data acquisition module 10 acquires memory chip information of different types of target memory chips, and acquires the routing length of the clock and data on the memory chip from the dual inline memory module DIMM to the memory chip of each memory granule according to the memory chip information.
The length determining module 20 is configured to obtain the length of the traces on the PCB from the CPU to the DIMM of the CPU according to the PCB information of the printed circuit board, and determine the total length of the traces between the CPU and each memory particle according to the sum of the length of the traces on the memory bank and the length of the traces on the PCB.
The adapting module 30 is configured to calculate a timing parameter corresponding to the total track length according to a preset configuration algorithm, and write the timing parameter into a memory parameter configuration program of the embedded system, so that the embedded system automatically adapts to the target memory bank.
The steps implemented by each functional module of the embedded system memory bank parameter adaptation device may refer to each embodiment of the embedded system memory bank parameter adaptation method of the present invention, and are not described herein again.
In addition, an embodiment of the present invention further provides a storage medium, where the storage medium may be a computer-readable nonvolatile storage medium, and certainly may also be other types of storage media, which is not limited in this embodiment; the storage medium stores an embedded system memory bank parameter adaptation program, and when the embedded system memory bank parameter adaptation program is executed by a processor, the following operations are realized:
acquiring memory bar information of different types of target memory bars, and acquiring the routing length of a clock and data on the memory bar from a dual in-line memory module (DIMM) to the memory bar of each memory particle according to the memory bar information;
acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB;
and calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Further, when executed by the processor, the embedded system memory bank parameter adaptation program further implements the following operations:
obtaining memory bank information of different types of target memory banks;
acquiring reference design original card information from the memory bank information;
screening information in the reference design original card information to obtain a daisy chain topology fly-by topological structure;
and acquiring the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by topological structure.
Further, when executed by the processor, the embedded system memory parameter adaptation program further implements the following operations:
acquiring a fly-by wiring sequence of a clock according to the fly-by topological structure;
and determining the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by routing sequence.
Further, when executed by the processor, the embedded system memory parameter adaptation program further implements the following operations:
determining the phase relation between the signal flow direction of the clock and the data according to the fly-by routing sequence;
determining the clock routing length of a clock from the dual in-line memory module (DIMM) to each memory grain according to the phase relation;
determining the data routing length of data from the DIMM to each memory grain according to the phase relation;
and taking the clock routing length and the data routing length as the routing length on the memory bank.
Further, when executed by the processor, the embedded system memory parameter adaptation program further implements the following operations:
obtaining the model and the version of the reference original card from the reference design original card information;
acquiring JEDEC specifications corresponding to the model and version of the reference original card;
and determining a corresponding daisy chain topology fly-by topology structure according to the JEDEC specification.
Further, when executed by the processor, the embedded system memory parameter adaptation program further implements the following operations:
obtaining the total length of clock routing and the total length of data routing from the total length of routing, and calculating to obtain the difference of the total length of the clock routing and the total length of the data routing;
acquiring time delay corresponding to the routing length difference, and acquiring DDR working speed from CPU configuration parameters of the embedded system;
determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat;
compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length;
and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
Further, when executed by the processor, the embedded system memory bank parameter adaptation program further implements the following operations:
and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system reads a target model and a target version of memory bank information of the target memory bank, searching for a corresponding target time sequence parameter according to the target model and the target version, and initializing the target memory bank according to the target time sequence parameter to complete adaptation of the target memory bank.
According to the scheme, the method comprises the steps that the line length from a dual in-line memory module (DIMM) to the memory bank of each memory particle of the memory bank is obtained according to the memory bank information by obtaining the memory bank information of different types of target memory banks; acquiring the routing length of the clock and the data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB; calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank; by calculating the time sequence parameters of different types of memory banks in advance, the embedded system can be automatically adapted to the different types of memory banks, the target memory can be quickly and accurately adapted efficiently, the system stability is improved, the memory bank range of the system adaptation is enlarged, the flexibility of the system memory adaptation is improved, and the work production efficiency is improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method for adapting parameters of a memory bank of an embedded system is characterized by comprising the following steps:
acquiring memory bar information of different types of target memory bars, and acquiring the routing length of a clock and data on the memory bar from a dual in-line memory module (DIMM) to the memory bar of each memory particle according to the memory bar information;
acquiring the length of a clock and data on the PCB from a Central Processing Unit (CPU) to the PCB of the DIMM according to the PCB information of the Printed Circuit Board (PCB), and determining the total length of the wire between the clock and the data from the CPU to each memory particle according to the sum of the length of the wire on the memory strip and the length of the wire on the PCB;
calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm, and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system is automatically adapted to the target memory bank;
wherein, the calculating the timing parameter corresponding to the total track length according to a preset configuration algorithm, and writing the timing parameter into a memory parameter configuration program of an embedded system, so that the embedded system automatically adapts to the target memory bank, includes:
obtaining the total length of clock routing and the total length of data routing from the total length of routing, and calculating to obtain the difference of the total length of the clock routing and the total length of the data routing;
acquiring time delay corresponding to the routing length difference, and acquiring DDR working speed from CPU configuration parameters of the embedded system;
determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat;
compensating the beat number according to a preset beat compensation value, and performing hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total length of the wiring;
and writing the time sequence parameter into a memory parameter configuration program of the embedded system so that the embedded system is automatically adapted to the target memory bank.
2. The method for adapting memory bank parameters of an embedded system according to claim 1, wherein the obtaining of memory bank information of different types of target memory banks and the obtaining of the trace length of the clock and data on the memory bank from the Dual Inline Memory Module (DIMM) to the memory bank of each memory granule according to the memory bank information comprises:
obtaining memory bank information of different types of target memory banks;
acquiring reference design original card information from the memory bank information;
screening information in the reference design original card information to obtain a daisy chain topology fly-by topological structure;
and acquiring the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by topological structure.
3. The method for adapting memory bank parameters of an embedded system according to claim 2, wherein said obtaining clock and data trace lengths from Dual Inline Memory Modules (DIMMs) to the memory bank of each memory granule according to a fly-by topology comprises:
acquiring a fly-by wiring sequence of a clock according to the fly-by topological structure;
and determining the routing length of the clock and the data from the dual in-line memory module (DIMM) to the memory strip of each memory particle according to the fly-by routing sequence.
4. The method for adapting memory bank parameters of an embedded system according to claim 3, wherein said determining a length of traces for a clock and data from a Dual Inline Memory Module (DIMM) to a memory bank of each memory die according to the fly-by trace order comprises:
determining the phase relation between the signal flow direction of the clock and the data according to the fly-by routing sequence;
determining the clock routing length of a clock from the dual in-line memory module (DIMM) to each memory grain according to the phase relation;
determining the data routing length of data from the DIMM to each memory grain according to the phase relation;
and taking the clock routing length and the data routing length as the routing length on the memory bank.
5. The method for adapting memory bank parameters of an embedded system according to claim 2, wherein the step of screening the information in the reference design original card information to obtain a daisy chain topology fly-by topology comprises:
obtaining the model and the version of the reference original card from the reference design original card information;
acquiring JEDEC specifications corresponding to the model and the version of the reference original card;
and determining a corresponding daisy chain topology fly-by topology structure according to the JEDEC specification.
6. The method for adapting memory bank parameters of an embedded system according to claim 1, wherein writing the timing parameters into a memory parameter configuration program of the embedded system to automatically adapt the embedded system to the target memory bank comprises:
and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system reads a target model and a target version of memory bank information of the target memory bank, searching for a corresponding target time sequence parameter according to the target model and the target version, and initializing the target memory bank according to the target time sequence parameter to complete adaptation of the target memory bank.
7. An embedded system memory bank parameter adapting device, comprising:
the data acquisition module is used for acquiring memory chip information of different types of target memory chips and acquiring the routing length of a clock and data on the memory chip from a dual in-line memory module (DIMM) to the memory chip of each memory particle according to the memory chip information;
the length determining module is used for acquiring the routing length of the clock and the data on the PCB from the CPU to the PCB of the DIMM according to the PCB information of the printed circuit board, and determining the total routing length between the clock and the data from the CPU to each memory particle according to the sum of the routing length on the memory strip and the routing length on the PCB;
the adaptive module is used for calculating a time sequence parameter corresponding to the total track length according to a preset configuration algorithm and writing the time sequence parameter into a memory parameter configuration program of an embedded system so that the embedded system automatically adapts to the target memory bank;
the adapter module is further configured to obtain a total clock trace length and a total data trace length from the total trace length, and calculate a trace length difference between the total clock trace length and the total data trace length; acquiring time delay corresponding to the routing length difference, and acquiring DDR working speed from CPU configuration parameters of the embedded system; determining a minimum beat according to the DDR working rate, and determining the number of beats between time and data according to the ratio of the time delay to the minimum beat; compensating the beat number according to a preset beat compensation value, and carrying out hexadecimal conversion on the compensated beat number to obtain a time sequence parameter corresponding to the total track length; and writing the time sequence parameters into a memory parameter configuration program of the embedded system so that the embedded system automatically adapts to the target memory bank.
8. An embedded system memory bank parameter adapting device, comprising: a memory, a processor and an embedded system memory bank parameter adaptation program stored on the memory and executable on the processor, the embedded system memory bank parameter adaptation program being configured to implement the steps of the embedded system memory bank parameter adaptation method according to any of claims 1 to 6.
9. A storage medium, wherein an embedded system memory bank parameter adaptation program is stored on the storage medium, and when executed by a processor, the embedded system memory bank parameter adaptation program implements the steps of the embedded system memory bank parameter adaptation method according to any one of claims 1 to 6.
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