CN116318075A - Single pulse signal clock domain crossing circuit and method - Google Patents

Single pulse signal clock domain crossing circuit and method Download PDF

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Publication number
CN116318075A
CN116318075A CN202310244997.4A CN202310244997A CN116318075A CN 116318075 A CN116318075 A CN 116318075A CN 202310244997 A CN202310244997 A CN 202310244997A CN 116318075 A CN116318075 A CN 116318075A
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signal
stage
circuit
clock domain
flip
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Inventor
王波
高礼
周宏然
陈名
秦健
盛俊毅
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Tbea Xi'an Flexible Power T&d Co ltd
TBEA Xinjiang Sunoasis Co Ltd
Super High Transmission Co of China South Electric Net Co Ltd
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Tbea Xi'an Flexible Power T&d Co ltd
TBEA Xinjiang Sunoasis Co Ltd
Super High Transmission Co of China South Electric Net Co Ltd
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Priority to CN202310244997.4A priority Critical patent/CN116318075A/en
Publication of CN116318075A publication Critical patent/CN116318075A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of clock domain signal time sequence processing, and particularly discloses a single pulse signal clock domain crossing circuit and a method, wherein an A clock domain logic circuit comprises a first-stage register circuit and a flip level circuit, the first-stage register circuit registers an input level for one beat and then outputs the input level, and the flip level circuit reversely and then re-inputs an output signal to the first-stage register circuit; the B clock domain logic circuit comprises a three-stage register circuit and a non-equal combination logic judging circuit, wherein the three-stage register circuit registers output signals for three beats and outputs the output signals, and when two input signals of the non-equal combination logic judging circuit are different, a single pulse signal crossing the clock domain is output. The invention can not only span the monopulse signal from the slow clock domain to the fast clock domain, but also span the monopulse signal from the fast clock domain to the slow clock domain, deduce the level conversion of the monopulse signal in different clock domains, judge the path crossing the clock domains, and has simple processing process and no waste of logic resources on the FPGA logic.

Description

Single pulse signal clock domain crossing circuit and method
Technical Field
The invention belongs to the technical field of clock domain crossing signal timing sequence processing, and particularly relates to a single pulse signal clock domain crossing circuit and a method.
Background
In flexible direct current valve control systems, FPGA chips are often required to handle high-speed communications, signal processing, and algorithm fusion functions. Processing signals across clock domains is also a very common problem in FPGA logic design. In some simpler digital circuits, there is only one clock, i.e. all flip-flops use the same clock, i.e. there is only one clock domain in the circuit. For chips with more complex functions, there are often multiple clocks in the circuit, and different modules use different clocks, i.e., multiple clock domains in this design. When signals are transmitted between different clock domains, they are referred to as cross-clock domain signals. As shown in fig. 2, two clock domains are shown, the block 1 clock is aclk and the block 2 clock is bclk. There is a cross-clock domain processing of a signal as it is transmitted in both modules.
For a single pulse data/control signal, it may jump during a setup time or hold time window when transferred from one clock domain to another, and metastability may occur. As shown in fig. 3 and 4, two D flip-flops (DFFs) are divided into two different clock domains a and b, and data adat of the clock domain a (whose active level lasts for one clock cycle) needs to be transferred to the clock domain b, and since adat is asynchronous to bclk, adata may jump during a window period of the setup time of the D flip-flop (DFF), resulting in bdat1 being an indeterminate state, and DFF1 has a metastable state. There are many ways to resolve the metastable state of a single pulse signal across the clock domain, mainly two-stage D flip-flop synchronous and asynchronous FIFOs.
This cross-clock domain approach to synchronizing two-stage D flip-flops falls into two cases: when the single pulse signal is transmitted from the slow clock domain to the fast clock domain, the single pulse signal is registered by two stages of registers under the fast clock domain; when the single pulse signal is transmitted from the fast clock domain to the slow clock domain, the single pulse signal is subjected to level broadening under the fast clock domain, and then the stretched signal is subjected to two-stage register registration under the slow clock domain, so that the two-stage D trigger synchronization method is too complex. Asynchronous FIFOs are typically used as clock-crossing domains for multi-bit data, while using asynchronous FIFOs for single-pulse signals would be a significant waste of FPGA logic resources.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a circuit and a method for crossing clock domains by a single pulse signal, so as to solve the problems of excessively complex method for generating metastable state by crossing clock domains by the single pulse signal or waste of logic resources.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
in a first aspect, the present invention provides a single pulse signal clock domain crossing circuit comprising:
a clock domain logic circuit A and a clock domain logic circuit B; the A clock domain logic circuit comprises a first-stage register circuit and a flip-level circuit INV; the input end of the primary register circuit is connected with the output end of the single pulse signal dat_pulse_i, the output end of the primary register circuit is connected with the input end of the flip level circuit INV, and the output end of the flip level circuit INV is connected with the input end of the primary register circuit;
the B clock domain logic circuit comprises a three-stage register circuit and a non-equal combination logic judging circuit NET; the output end of the first-level register circuit is connected with the input end of the third-level register circuit, the first-level register circuit outputs a signal dat1 to the third-level register circuit, the output end of the third-level register circuit is connected with the input end of the unequal combination logic judging circuit NET, and the output end of the unequal combination logic judging circuit NET outputs a single pulse signal dat_pulse_o.
Further, the device also comprises an asynchronous reset signal generator, wherein the output end of the asynchronous reset signal generator is respectively connected with the asynchronous reset signal to the A clock domain logic circuit and the B clock domain logic circuit; the asynchronous reset signal generator can issue an asynchronous reset signal rst_n.
Further, the first-stage register circuit comprises a first-stage D trigger DFF1; the Q output end of the first-stage D flip-flop DFF1 is connected with the input end of the flip-level circuit INV, and the first-stage D flip-flop DFF1 can send out a signal dat1; the output end of the flip-flop level circuit INV is connected to the D input end of the primary D flip-flop DFF1, and the flip-flop level circuit INV can send out a signal dat1_inv.
Further, the output end of the asynchronous reset signal generator is connected with the CLR asynchronous reset end of the one-stage D flip-flop DFF1, the CLK clock input end of the one-stage D flip-flop DFF1 is connected with the output end of the aclk clock, and the single pulse signal dat_pulse_i output end is connected with the CE enable end of the one-stage D flip-flop DFF 1.
Further, the three-stage register circuit comprises a two-stage D trigger DFF2, a three-stage D trigger DFF3 and a four-stage D trigger DFF4; the Q output end of the first-stage D trigger DFF1 is connected with the D data input end of the second-stage D trigger DFF2, the Q output end of the second-stage D trigger DFF2 is connected with the D data input end of the third-stage D trigger DFF3, the Q output end of the third-stage D trigger DFF3 is connected with the D data input end of the fourth-stage D trigger DFF4, the Q output end of the fourth-stage D trigger DFF4 is connected with the first input end which is not equal to the combinational logic judgment circuit NET, and the second input end which is not equal to the combinational logic judgment circuit NET is connected with the Q output end of the third-stage D trigger DFF 3.
Furthermore, the CLK clock input ends of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF4 are connected with the output end of the bclk clock; the output end of the asynchronous reset signal is respectively connected with the CLR asynchronous reset ends of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF 4.
Further, the input data of the second-stage D flip-flop DFF2 is a signal dat1, and the output signal of the second-stage D flip-flop DFF2 is a signal dat2; the input data of the three-stage D trigger DFF3 is a signal dat2, and the output signal of the three-stage D trigger DFF3 is a signal dat3; the input data of the four-stage D flip-flop DFF4 is a signal dat3, and the output signal of the four-stage D flip-flop DFF4 is a signal dat4; the two input signals which are not equal to the combinational logic determination circuit NET are the signal dat3 and the signal dat4 respectively, and the output signal which is not equal to the combinational logic determination circuit NET is the single pulse signal dat_pulse_o.
Further, the primary register circuit is configured to perform primary register on the signal dat1_inv when the single pulse signal dat_pulse_i is at a high level; the inversion level circuit INV is used for inverting the level of the input data.
In a second aspect, the present invention provides a method for crossing clock domains by using a single pulse signal, which is based on any one of the above single pulse signal crossing clock domains, and includes:
a single pulse signal spans from the slow clock domain to the fast clock domain and a single pulse signal spans from the fast clock domain to the slow clock domain;
the single pulse signal spans from the slow clock domain to the fast clock domain as follows: inputting a single pulse signal dat_pulse_i to a slow clock domain, outputting a signal dat1 after passing through a first-stage register circuit and a flip-level circuit INV in an A clock domain logic circuit, and outputting the single pulse signal dat_pulse_o after the signal dat1 enters a B clock domain logic circuit and passes through a third-stage D trigger and a non-equal combination logic judgment circuit NET;
the single pulse signal spans from the fast clock domain to the slow clock domain as follows: the single pulse signal dat_pulse_i is input to a fast clock domain, the signal dat1 is output after passing through a first-stage register circuit and a flip-level circuit INV in the logic circuit of the A clock domain, and the signal dat1 is output after entering into the logic circuit of the B clock domain and passing through a third-stage D trigger and a non-equal combination logic judging circuit NET.
Further, the crossing of the monopulse signal from the slow clock domain to the fast clock domain is specifically: inputting a single pulse signal dat_pulse_i to a slow clock domain, and outputting a signal dat1 jumping from low level to high level after passing through a one-level D trigger DFF1 and an inversion level circuit INV in an A clock domain logic circuit; the signal dat1 enters a B clock domain logic circuit and then passes through a three-stage D trigger and a non-equal combination logic judging circuit NET, specifically, the signal dat1 enters a two-stage D trigger DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters a three-stage D trigger DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters a four-stage D trigger DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judgment clock period passes through the non-equal combination logic judging circuit NET;
the crossing of the monopulse signal from the fast clock domain to the slow clock domain is specifically as follows: inputting a single pulse signal dat_pulse_i to a fast clock domain, and outputting a signal dat1 jumping from low level to high level after passing through a one-level D trigger DFF1 and an inversion level circuit INV in an A clock domain logic circuit; the signal dat1 enters the B clock domain logic circuit and then passes through the three-stage D flip-flop and the unequal combination logic judging circuit NET, specifically, the signal dat1 enters the two-stage D flip-flop DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters the three-stage D flip-flop DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters the four-stage D flip-flop DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judging clock period passes through the unequal combination logic judging circuit NET.
The invention has at least the following beneficial effects:
the circuit comprises an A clock domain logic circuit and a B clock domain logic circuit, wherein the A clock domain logic circuit comprises a first-stage register circuit and a turnover level circuit, the first-stage register circuit registers an input level for one time and outputs the input level when a single pulse signal is at a high level, and the turnover level circuit inverts an output signal of the first-stage register circuit and inputs the output signal to the first-stage register circuit again; the B clock domain logic circuit comprises a three-stage register circuit and a non-equal combination logic judging circuit, wherein the three-stage register circuit registers output signals of the B clock domain logic circuit and outputs the output signals, the input signals of the non-equal combination logic judging circuit are three-stage trigger output signals and four-stage trigger output signals of the three-stage register circuit, and when the two input signals of the non-equal combination logic judging circuit are different, a single pulse signal crossing a clock domain is output. The invention can not only span the single pulse signal from the slow clock domain to the fast clock domain, but also span the single pulse signal from the fast clock domain to the slow clock domain, deduce the level conversion of the single pulse signal in different clock domains, judge the path crossing the clock domain, and has simple processing process on the FPGA logic without wasting logic resources, and the signal crossing the clock domain is correct, stable and reliable.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a circuit diagram of a single pulse signal cross clock domain synthesized by programmable logic;
FIG. 2 is an asynchronous clock domain diagram;
FIG. 3 is a cross-clock domain diagram;
FIG. 4 is an asynchronous clock domain timing diagram;
FIG. 5 is a timing waveform diagram of a single pulse signal crossing from a slow clock domain to a fast clock domain;
FIG. 6 is a timing waveform diagram of a single pulse signal crossing from a fast clock domain to a slow clock domain.
Detailed Description
The invention will be described in detail below with reference to the drawings in connection with embodiments. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The following detailed description is exemplary and is intended to provide further details of the invention. Unless defined otherwise, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the invention.
Example 1
As shown in fig. 1, a single pulse signal cross-clock domain circuit includes:
the clock domain logic circuit A and the clock domain logic circuit B are respectively a left broken line frame circuit of the figure 1, and the clock domain logic circuit B is a right broken line frame circuit of the figure 1; the output end of the asynchronous reset signal generator is respectively connected with the asynchronous reset signal to the A clock domain logic circuit and the B clock domain logic circuit; the asynchronous reset signal generator can send out an asynchronous reset signal rst_n; the asynchronous reset signal is valid at a low level, the initial state is at a low level, and the signal is kept at a high level after the reset is completed;
the A clock domain logic circuit comprises a first-stage register circuit and a flip-level circuit INV; the first-stage register circuit comprises a first-stage D trigger DFF1; the Q output end of the first-stage D flip-flop DFF1 is connected with the input end of the flip-level circuit INV, and the first-stage D flip-flop DFF1 can send out a signal dat1; the output end of the inversion level circuit INV is connected with the D input end of the one-stage D trigger DFF1, and the inversion level circuit INV can send out a signal dat1_inv which is input into the one-stage D trigger DFF1;
the output end of the asynchronous reset signal generator is connected with the CLR asynchronous reset end of the first-stage D trigger DFF1, and the asynchronous reset signal rst_n inputs a reset signal into the first-stage D trigger DFF1; the CLK clock input end of the first-stage D trigger DFF1 is connected with the output end of the aclk clock, and the input clock of the first-stage D trigger DFF1 is aclk; the output end of the single pulse signal dat_pulse_i is connected with the CE enabling end of the one-stage D trigger DFF1, and the enabling signal input to the one-stage D trigger DFF1 is the single pulse signal dat_pulse_i; the output data of the first-stage D flip-flop DFF1 is a signal dat1, and the signal dat1 is input into the flip-level circuit INV; the primary register circuit has the function of carrying out primary register on the signal dat1_inv when the single pulse signal dat_pulse_i is at a high level; the flip level circuit INV functions to flip the level of input data.
The B clock domain logic circuit comprises a three-stage register circuit and a non-equal combination logic judging circuit NET; the three-level register circuit comprises a two-level D trigger DFF2, a three-level D trigger DFF3 and a four-level D trigger DFF4; the Q output end of the D trigger DFF1 is connected with the D data input end of the second-stage D trigger DFF2, the Q output end of the second-stage D trigger DFF2 is connected with the D data input end of the third-stage D trigger DFF3, the Q output end of the third-stage D trigger DFF3 is connected with the D data input end of the fourth-stage D trigger DFF4, the Q output end of the fourth-stage D trigger DFF4 is connected with the first input end of the unequal combination logic judging circuit NET, and the second input end of the unequal combination logic judging circuit NET is connected with the Q output end of the third-stage D trigger DFF 3;
CLK clock input ends of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF4 are connected with output ends of bclk clocks, and input clocks of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF4 are bclk; the output end of the asynchronous reset signal is respectively connected with the CLR asynchronous reset ends of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF4, and the asynchronous reset signal rst_n is respectively used for inputting reset signals to the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF4; the input data of the two-stage D flip-flop DFF2 is a signal dat1, and the output signal of the two-stage D flip-flop DFF2 is a signal dat2; the input data of the three-stage D trigger DFF3 is a signal dat2, and the output signal of the three-stage D trigger DFF3 is a signal dat3; the input data of the four-stage D flip-flop DFF4 is a signal dat3, and the output signal of the four-stage D flip-flop DFF4 is a signal dat4; the two input signals which are not equal to the combinational logic judgment circuit NET are the signal dat3 and the signal dat4 respectively, and the output signal which is not equal to the combinational logic judgment circuit NET is the finally output cross-clock domain single pulse signal dat_pulse_o.
Example 2
A single pulse signal cross clock domain method comprising: a single pulse signal spans from the slow clock domain to the fast clock domain and a single pulse signal spans from the fast clock domain to the slow clock domain;
the timing waveforms of the single pulse signal crossing from the slow clock domain to the fast clock domain are shown in fig. 5, specifically: the single pulse signal dat_pulse_i is input to the slow clock domain, and the signal dat1 which jumps from low level to high level is output after passing through the D flip-flop DFF1 and the flip-flop level circuit INV in the logic circuit of the A clock domain. The signal dat1 enters the B clock domain logic circuit and then passes through the three-stage D flip-flop and the unequal combination logic judging circuit NET, specifically, the signal dat1 enters the two-stage D flip-flop DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters the three-stage D flip-flop DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters the four-stage D flip-flop DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judging clock period passes through the unequal combination logic judging circuit NET. Thus, the single pulse signal is dat_pulse_i, and the single pulse signal dat_pulse_o is generated after the slow clock domain crosses to the fast clock domain.
The timing waveforms of the single pulse signal crossing from the fast clock domain to the slow clock domain are shown in fig. 6, specifically: the single pulse signal dat_pulse_i is input to the fast clock domain, and the signal dat1 which jumps from low level to high level is output after passing through the D flip-flop DFF1 and the flip-flop level circuit INV in the logic circuit of the A clock domain. The signal dat1 enters the B clock domain logic circuit and then passes through the three-stage D flip-flop and the unequal combination logic judging circuit NET, specifically, the signal dat1 enters the two-stage D flip-flop DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters the three-stage D flip-flop DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters the four-stage D flip-flop DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judging clock period passes through the unequal combination logic judging circuit NET. Thus, the single pulse signal is dat_pulse_i, and the single pulse signal dat_pulse_o is generated after the fast clock domain crosses to the slow clock domain.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.

Claims (10)

1. A single pulse signal cross clock domain circuit, comprising:
a clock domain logic circuit A and a clock domain logic circuit B; the A clock domain logic circuit comprises a first-stage register circuit and a flip-level circuit INV; the input end of the primary register circuit is connected with the output end of the single pulse signal dat_pulse_i, the output end of the primary register circuit is connected with the input end of the flip level circuit INV, and the output end of the flip level circuit INV is connected with the input end of the primary register circuit;
the B clock domain logic circuit comprises a three-stage register circuit and a non-equal combination logic judging circuit NET; the output end of the first-level register circuit is connected with the input end of the third-level register circuit, the first-level register circuit outputs a signal dat1 to the third-level register circuit, the output end of the third-level register circuit is connected with the input end of the unequal combination logic judging circuit NET, and the output end of the unequal combination logic judging circuit NET outputs a single pulse signal dat_pulse_o.
2. The single pulse signal cross clock domain circuit according to claim 1, further comprising an asynchronous reset signal generator, wherein an output terminal of the asynchronous reset signal generator is connected to the asynchronous reset signal to the a clock domain logic circuit and the B clock domain logic circuit, respectively; the asynchronous reset signal generator can issue an asynchronous reset signal rst_n.
3. A single pulse signal cross clock domain circuit according to claim 2, wherein said primary register circuit comprises a primary D flip-flop DFF1; the Q output end of the first-stage D flip-flop DFF1 is connected with the input end of the flip-level circuit INV, and the first-stage D flip-flop DFF1 can send out a signal dat1; the output end of the flip-flop level circuit INV is connected to the D input end of the primary D flip-flop DFF1, and the flip-flop level circuit INV can send out a signal dat1_inv.
4. A single pulse signal cross clock domain circuit according to claim 3, wherein the output of the asynchronous reset signal generator is connected to the CLR asynchronous reset of the stage D flip-flop DFF1, the CLK clock input of the stage D flip-flop DFF1 is connected to the output of the aclk clock, and the single pulse signal dat_pulse_i output is connected to the CE enable of the stage D flip-flop DFF 1.
5. A single pulse signal cross clock domain circuit according to claim 3, wherein said three stage register circuit comprises a two stage D flip-flop DFF2, a three stage D flip-flop DFF3 and a four stage D flip-flop DFF4; the Q output end of the first-stage D trigger DFF1 is connected with the D data input end of the second-stage D trigger DFF2, the Q output end of the second-stage D trigger DFF2 is connected with the D data input end of the third-stage D trigger DFF3, the Q output end of the third-stage D trigger DFF3 is connected with the D data input end of the fourth-stage D trigger DFF4, the Q output end of the fourth-stage D trigger DFF4 is connected with the first input end which is not equal to the combinational logic judgment circuit NET, and the second input end which is not equal to the combinational logic judgment circuit NET is connected with the Q output end of the third-stage D trigger DFF 3.
6. The single pulse signal cross clock domain circuit according to claim 5, wherein CLK clock inputs of the two-stage D flip-flop DFF2, the three-stage D flip-flop DFF3, and the four-stage D flip-flop DFF4 are all connected to an output of a bclk clock; the output end of the asynchronous reset signal is respectively connected with the CLR asynchronous reset ends of the second-stage D trigger DFF2, the third-stage D trigger DFF3 and the fourth-stage D trigger DFF 4.
7. The single pulse signal clock domain crossing circuit according to claim 5, wherein the input data of the two-stage D flip-flop DFF2 is a signal dat1, and the output signal of the two-stage D flip-flop DFF2 is a signal dat2; the input data of the three-stage D trigger DFF3 is a signal dat2, and the output signal of the three-stage D trigger DFF3 is a signal dat3; the input data of the four-stage D flip-flop DFF4 is a signal dat3, and the output signal of the four-stage D flip-flop DFF4 is a signal dat4; the two input signals which are not equal to the combinational logic determination circuit NET are the signal dat3 and the signal dat4 respectively, and the output signal which is not equal to the combinational logic determination circuit NET is the single pulse signal dat_pulse_o.
8. A single pulse signal clock domain crossing method according to claim 3, wherein said one stage register circuit is adapted to perform one stage register of the signal dat1_inv when the single pulse signal dat_pulse_i is at a high level; the inversion level circuit INV is used for inverting the level of the input data.
9. A single pulse signal clock domain crossing method, characterized in that it is based on a single pulse signal clock domain crossing circuit according to any of claims 1-8, comprising:
a single pulse signal spans from the slow clock domain to the fast clock domain and a single pulse signal spans from the fast clock domain to the slow clock domain;
the single pulse signal spans from the slow clock domain to the fast clock domain as follows: inputting a single pulse signal dat_pulse_i to a slow clock domain, outputting a signal dat1 after passing through a first-stage register circuit and a flip-level circuit INV in an A clock domain logic circuit, and outputting the single pulse signal dat_pulse_o after the signal dat1 enters a B clock domain logic circuit and passes through a third-stage D trigger and a non-equal combination logic judgment circuit NET;
the single pulse signal spans from the fast clock domain to the slow clock domain as follows: the single pulse signal dat_pulse_i is input to a fast clock domain, the signal dat1 is output after passing through a first-stage register circuit and a flip-level circuit INV in the logic circuit of the A clock domain, and the signal dat1 is output after entering into the logic circuit of the B clock domain and passing through a third-stage D trigger and a non-equal combination logic judging circuit NET.
10. The method for crossing clock domains by single pulse signals according to claim 9, wherein the single pulse signals are crossed from slow clock domains to fast clock domains specifically comprises the following steps: inputting a single pulse signal dat_pulse_i to a slow clock domain, and outputting a signal dat1 jumping from low level to high level after passing through a one-level D trigger DFF1 and an inversion level circuit INV in an A clock domain logic circuit; the signal dat1 enters a B clock domain logic circuit and then passes through a three-stage D trigger and a non-equal combination logic judging circuit NET, specifically, the signal dat1 enters a two-stage D trigger DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters a three-stage D trigger DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters a four-stage D trigger DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judgment clock period passes through the non-equal combination logic judging circuit NET;
the crossing of the monopulse signal from the fast clock domain to the slow clock domain is specifically as follows: inputting a single pulse signal dat_pulse_i to a fast clock domain, and outputting a signal dat1 jumping from low level to high level after passing through a one-level D trigger DFF1 and an inversion level circuit INV in an A clock domain logic circuit; the signal dat1 enters the B clock domain logic circuit and then passes through the three-stage D flip-flop and the unequal combination logic judging circuit NET, specifically, the signal dat1 enters the two-stage D flip-flop DFF2 and then outputs a signal dat2 which jumps from low level to high level, the signal dat2 enters the three-stage D flip-flop DFF3 and then outputs a signal dat3 which jumps from low level to high level, the signal dat3 enters the four-stage D flip-flop DFF4 and then outputs a signal dat4 which jumps from low level to high level, and finally, the signal dat_pulse_o is output after the judging clock period passes through the unequal combination logic judging circuit NET.
CN202310244997.4A 2023-03-14 2023-03-14 Single pulse signal clock domain crossing circuit and method Pending CN116318075A (en)

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CN117538622A (en) * 2024-01-08 2024-02-09 湖南进芯电子科技有限公司 Pulse width measuring circuit and pulse width measuring method
CN117595841A (en) * 2024-01-18 2024-02-23 苏州萨沙迈半导体有限公司 Cross-clock domain pulse synchronization circuit, chip and computer equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117538622A (en) * 2024-01-08 2024-02-09 湖南进芯电子科技有限公司 Pulse width measuring circuit and pulse width measuring method
CN117538622B (en) * 2024-01-08 2024-03-26 湖南进芯电子科技有限公司 Pulse width measuring circuit and pulse width measuring method
CN117595841A (en) * 2024-01-18 2024-02-23 苏州萨沙迈半导体有限公司 Cross-clock domain pulse synchronization circuit, chip and computer equipment
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