CN207301963U - A kind of reset detection circuit - Google Patents
A kind of reset detection circuit Download PDFInfo
- Publication number
- CN207301963U CN207301963U CN201721088693.XU CN201721088693U CN207301963U CN 207301963 U CN207301963 U CN 207301963U CN 201721088693 U CN201721088693 U CN 201721088693U CN 207301963 U CN207301963 U CN 207301963U
- Authority
- CN
- China
- Prior art keywords
- circuit
- reset
- clock
- input
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model discloses a kind of reset detection circuit, reset request input circuit receives the effective reset request of low level of reset pin input and exports the reset request；Latch circuit generates the connection control signal or shut-off control signal of clock circuit according to the reset request that the reset request input circuit exports by the second phase inverter；The clock circuit closes clock signal according to the connection control signal generation clock signal or according to the shut-off control signal；Synchronously withdraw circuit controls M digit counters to start to work according to the reset request that the reset request input circuit is exported by the first phase inverter；The M digit counters run duration is at least through 2MAfter a clock cycle, output resets useful signal.By using the technical solution, the stability of reset detection is improved.
Description
Technical field
It the utility model is related to electronic technology field, more particularly to a kind of reset detection circuit.
Background technology
Electronic product based on IC (Integrated Circuit, integrated circuit) during powering on or reset rank
Section, in order to preferably control the state of IC, prevent CPU (Central Processing Unit, central processing unit) or other
IP (Intellectual Property, kernel) module false triggering or maloperation occurs, it is necessary to design one it is accurate and reliable
Reset detection circuit.Reset pin is needed on usual IC, the effect of reset pin is when IC hangs dead, is not being powered off
In the case of active homing can occur, restart IC.Existing reset detection circuit is being subject to external electromagnetic to do sometimes
When disturbing, false triggering is easily produced, so as to cause IC operation irregularities.
As it can be seen that existing reset detection circuit at least has the following technical problems：Easily produced when detecting reset signal
False triggering so that the technical problem that IC is reduced due to extraneous electromagnetic interference job stability.
Utility model content
The utility model embodiment is by providing a kind of reset detection circuit, for solving to reset in detection in the prior art
False triggering is easily produced during signal so that the technical problem that IC is reduced due to extraneous electromagnetic interference job stability.
One embodiment of the utility model provides a kind of reset detection circuit, including：
Reset request input circuit, latch circuit, clock circuit, synchronously withdraw circuit, be M digit counters, first anti-phase
Device and the second phase inverter；
The input terminal of the reset request input circuit is connected with reset pin, the reset request input circuit it is defeated
Outlet is connected with the first input end of the latch circuit, and the output terminal of the reset request input circuit is anti-by first
Phase device is connected with the reset terminal for synchronously withdrawing circuit, and the output terminal of the latch circuit passes through the second phase inverter and institute
The first control terminal for stating clock circuit is connected, the output terminal of the clock circuit respectively with the clock for synchronously withdrawing circuit
Signal input part is connected with the clock signal input terminal of the M digit counters, described synchronously to withdraw circuit and described M counting
The reset terminal of device is connected；
Wherein, the reset request input circuit please for receiving effective reset of low level of the reset pin input
Ask and export the reset request, the latch circuit is used for the reset request exported according to the reset request input circuit
The connection control signal or shut-off control signal of clock circuit are generated, the clock circuit is used to connect control letter according to described
Number generation clock signal or according to it is described shut-off control signal close clock signal, it is described synchronously withdraw circuit be used for according to institute
The reset request control M digit counters for stating the output of reset request input circuit are started to work, the operation duration of the M digit counters
Time is at least through 2MAfter a clock cycle, output resets useful signal.
Optionally, the output terminal of the M digit counters is connected with the second control terminal of the clock circuit, in the M
When digit counter output resets useful signal, the clock circuit is based on the reset useful signal and closes clock signal.
Optionally, the output terminal of the M digit counters is connected with the second input terminal of the latch circuit, when described
The reset request of reset request input circuit output is withdrawn before the non-set of output terminal of the M digit counters, the latch
Circuit output high level signal, so as to control the clock circuit to close clock signal.
Optionally, the reset request input circuit includes Enable Pin, input, output end, the first NOT gate and OR gate, institute
The input terminal for stating reset request input circuit is connected with the first input end of the OR gate, and the reset request input circuit makes
Energy end is connected by the first NOT gate with the second input terminal of the OR gate, and the output terminal of the OR gate is the reset request circuit
Output terminal；
When the Enable Pin is high level, what is be connected with the input terminal of the reset request input circuit is used for institute
The reset function for stating the reset pin of reset request input circuit input reset signal is effective.
Optionally, when the Enable Pin is low level, the reset function of the reset pin is invalid, the reset pin
Used as GPIO (General Purpose Input Output, universal input/output) pin.
Optionally, the latch circuit is specially that the SR being made of the second NOT gate, the 3rd NOT gate and two NAND gates locks
Storage；
The first input end of the latch circuit is the R ends of the S/R latch；
Second input terminal of the latch circuit is the S ends of the S/R latch；
The output terminal of the latch circuit is the Q ends of the S/R latch.
Optionally, the clock circuit includes the first clock module and second clock module, first clock module
Output terminal is connected with the input terminal of the second clock module；
First control terminal of the clock circuit be first clock module Enable Pin, the second of the clock circuit
Control terminal is the Enable Pin of the second clock module, and the output terminal of the clock circuit is the output of the second clock module
End.
Optionally, the circuit of synchronously withdrawing includes two sequentially connected first d type flip flops and the second d type flip flop；
The output terminal of the clock circuit is triggered with the clock signal input terminal of first d type flip flop and the 2nd D respectively
The clock signal input terminal of device is connected；
The Q ends of first d type flip flop are connected with the D ends of second d type flip flop, described synchronously to withdraw the defeated of circuit
Outlet is the output terminal of second d type flip flop.
Optionally, the M digit counters are M ripple counters, and the M ripple counter is made of d type flip flop
Asynchronous M binary addition counters.
The one or more technical solutions provided in the utility model embodiment, at least have the following technical effect that or excellent
Point：
By using the technical scheme in the embodiment of the utility model, the electromagnetic interference in the external world can be effectively filtered, is carried
The high reliability of reset detection circuit, reduces the energy consumption of reset detection circuit, and reset pin is multiplexed, i.e., multiple
Position pin can be used as GPIO.
Brief description of the drawings
Figure 1A is the first schematic diagram of the reset detection circuit that the utility model embodiment provides；
Figure 1B is the second schematic diagram of the reset detection circuit that the utility model embodiment provides；
Fig. 2A is the schematic diagram for the reset request input circuit that the utility model embodiment provides；
Fig. 2 B are the schematic diagram for the latch circuit that the utility model embodiment provides；
Fig. 2 C are the schematic diagram for the clock circuit that the utility model embodiment provides；
Fig. 2 D are the schematic diagram for synchronously withdrawing circuit that the utility model embodiment provides；
Fig. 2 E are the schematic diagram for the M digit counters that the utility model embodiment provides；
Fig. 2 F are the schematic diagram for the specific logic circuit of reset detection circuit that the utility model embodiment provides；
Embodiment
In order to solve the above-mentioned technical problem, the general thought of the technical scheme in the embodiment of the utility model is as follows：
A kind of reset detection circuit, reset detection circuit include reset request input circuit, latch circuit, clock electricity
Road, synchronously withdraw circuit, M digit counters, the first phase inverter and the second phase inverter；
The input terminal of the reset request input circuit is connected with reset pin, the reset request input circuit it is defeated
Outlet is connected with the first input end of the latch circuit, and the output terminal of the reset request input circuit is anti-by first
Phase device is connected with the reset terminal for synchronously withdrawing circuit, and the output terminal of the latch circuit passes through the second phase inverter and institute
The first control terminal for stating clock circuit is connected, the output terminal of the clock circuit respectively with the clock for synchronously withdrawing circuit
Signal input part is connected with the clock signal input terminal of the M digit counters, described synchronously to withdraw circuit and described M counting
The reset terminal of device is connected；
Wherein, the reset request input circuit please for receiving effective reset of low level of the reset pin input
Ask and export the reset request, the latch circuit is used for the reset request exported according to the reset request input circuit
The connection control signal or shut-off control signal of clock circuit are generated, the clock circuit is used to connect control letter according to described
Number generation clock signal or according to it is described shut-off control signal close clock signal, it is described synchronously withdraw circuit be used for according to institute
The reset request control M digit counters for stating the output of reset request input circuit are started to work, the operation duration of the M digit counters
Time is at least through 2MAfter a clock cycle, output resets useful signal.
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
Technical solution is stated to be described in detail.
Referring to Figure 1A, the utility model embodiment one provides a kind of reset detection circuit, including：
Reset request input circuit 10, latch circuit 20, clock circuit 30, synchronously withdraw circuit 40, M digit counters
50th, the first phase inverter 60 and the second phase inverter 70；
The input terminal of the reset request input circuit 10 is connected with reset pin (not shown in figure 1), the reset
The output terminal of request input circuit 10 is connected with the first input end of the latch circuit 20, the reset request input electricity
The output terminal on road 10 is connected by first phase inverter 60 with the reset terminal for synchronously withdrawing circuit 40, the latch
The output terminal of circuit 20 is connected by second phase inverter 70 with the first control terminal of the clock circuit 30, the clock
The output terminal of circuit 30 respectively with the clock signal input terminal for synchronously withdrawing circuit 40 and the clock of the M digit counters 50
Signal input part is connected, and the circuit 40 of synchronously withdrawing is connected with the reset terminal of the M digit counters 50；
Wherein, the reset request input circuit 10 is effectively resetted for receiving the low level of the reset pin input
Ask and export the reset request, the latch circuit 20 is used to be answered according to what the reset request input circuit 10 exported
Position requests to generate the connection control signal of clock circuit 30 or shut-off control signal, the clock circuit 30 are used for according to
Connect control signal generation clock signal or clock signal is closed according to the shut-off control signal, it is described synchronously to withdraw circuit
The 40 reset request control M digit counters for being used to be exported according to the reset request input circuit are started to work, the M counting
The run duration of device 50 is at least through 2MAfter a clock cycle, output resets useful signal.
Wherein, reset pin can be the reset pin in IC chip, and reset detection circuit can be applied to IC chip
The internal detection circuit being connected with the reset pin.
Referring to Figure 1B, in order to further reduce the power consumption of clock, clock circuit 30 can also have the second control terminal, M
The output terminal of digit counter 50 is connected with the second control terminal of clock circuit 30, has in the M digit counters 50 output reset
When imitating signal, the clock circuit 30 closes clock signal according to the reset useful signal；
The output terminal of M digit counters 50 is connected with the second input terminal of the latch circuit 20, when the reset please
The reset request that input circuit exports is asked to be withdrawn before the non-set of output terminal of the M digit counters, the latch circuit 20
High level signal is exported, so as to control the clock circuit to close clock signal.Specifically, if the duration of reset request
It is shorter, such as less than 2MA clock cycle, i.e. reset request withdraw before the non-set of output terminal of M digit counters 50, then latch
Two input terminals of device circuit 20 are high level, and latch circuit 20 exports high level signal, so as to control clock circuit 30
Close clock signal.
In order to enable reset pin has the function of multiplexing, such as reset pin can be used as multiplexing GPIO to use, and resetting please
The structure for asking input circuit 10 that Fig. 2A can be used to use；Certainly, if being not required reset pin that there is multiplexing, reset
Request input circuit both may be used only with the existing circuit that can transmit reset signal.
Referring to Fig. 2A, reset request input circuit 10 can include Enable Pin PAD_EN, input terminal PAD_IN, NOT gate 101
With OR gate 102, the input terminal PAD_IN of reset request input circuit is connected with the first input end of OR gate 102, and reset request is defeated
The Enable Pin PAD_EN for entering circuit is connected by the first NOT gate 101 with the second input terminal of OR gate 102, the output terminal of OR gate 102
For the output terminal VLD_IN of the reset request circuit；
When Enable Pin PAD_EN is high level, it is used for what the input terminal PAD_IN of reset request input circuit was connected
It is effective to the reset function of the reset pin of reset request input circuit input reset signal；
When Enable Pin PAD_EN is low level, the reset function of the reset pin is invalid, the reset pin conduct
GPIO pin uses.
Referring to Fig. 2 B, for latch circuit 20, S/R latch can be specifically used, specifically, latch circuit 20 wraps
Include the S/R latch that the second NOT gate 201, the 3rd NOT gate 202 and two NAND gates 203 and 204 are formed；
The first input end of latch circuit 20 is connected by the second NOT gate 201 with the R ends of the S/R latch；Latch
Second input terminal of device circuit 20 is connected by the 3rd NOT gate 202 with the S ends of the S/R latch；Latch circuit 20 it is defeated
Outlet is the Q ends of the S/R latch.
Referring to Fig. 2 C, for clock circuit 30, the clock circuit can be specifically Clock Managing Unit CMU,
The clock circuit 30 includes the first clock module G0 and second clock module G1, the first clock module G0's
Output terminal GCK is connected with the input terminal GCK of the second clock module G1；
First control terminal of the clock circuit 30 be the first clock module G0 Enable Pin E, the clock circuit
30 the second control terminal is the Enable Pin E of the second clock module G1, and the output terminal GCK of the clock circuit 30 is described the
The output terminal SM_CLK of two clock module G1.
Referring to Fig. 2 D, synchronously withdrawing circuit 40 includes two sequentially connected first d type flip flop, 401 and second d type flip flops
402；
The output terminal of the clock circuit respectively with the clock signal input terminal of the first d type flip flop SYNC0_REG and
The clock signal input terminal of second d type flip flop SYNC1_REG is connected；
The Q ends of the first d type flip flop SYNC0_REG are connected with the D ends of the second d type flip flop SYNC1_REG, institute
State the output terminal for synchronously withdrawing the output terminal PAD_SYNG of circuit as the second d type flip flop SYNC1_REG.
For M digit counters 50, it can be specifically for M ripple counters, and the M ripple counter is touched by D
Send out the asynchronous M binary addition counters that device is formed.Wherein, the digit of ripple counter can be made by specific IC demands
It is fixed, the length of reset detection circuit filtering is determined with this.
Referring to Fig. 2 E, for the concrete structure of the M ripple counter, including M d type flip flop, wherein M=n.Specifically,
The input terminal D of each d type flip flop is connected with its output terminal Q, the input terminal of first order d type flip flop and the output terminal of clock circuit
SM_CLK is connected, and the output terminal Q of first order d type flip flop is connected with the input terminal of its rear stage d type flip flop, according to this class leg,
The output terminal Q of afterbody d type flip flop is the output terminal PAD_RSTG of whole ripple counter.
Referring to Fig. 2 F, the overall logic circuit diagram of the reset detection circuit provided for the utility model embodiment.With reference to this
Circuit diagram, is further described the operation principle of reset detection circuit.
If it is 0 to set PAD_EN, reset pin can be used as GPIO pin, and any saltus step of PAD_IN cannot make
VLD_IN produces the saltus step from 1 to 0.
If it is 1 to set PAD_EN, GPIO pin is changed into reset pin, and when not producing reset request, which should
In pull-up state, VLD_IN is high level at this time；It synchronously to withdraw two triggers in circuit 40 by phase inverter
In reset state, therefore it is 0 that it, which exports PAD_SYNJ,；PAD_SYNJ can make M digit counters 50 be in reset state, therefore its
OutputFor high level, G1 is held in clock circuit, has no reset；Latch circuit 20 is seen again, itself S and R end is equal
Input high level, SJ and RJ is low level after phase inverter, therefore the output Q and QN of two NAND gates are high electricity
Flat, reverser is passed through in wherein Q outputs, and the clock of whole circuit is have turned off by the G0 in clock circuit 30, although G1 is turned on
Without SM_CLK.
If it is 1 to set PAD_EN, and when reset pin has low level input, reset detection circuit is opened in the following way
Beginning work：
The meeting saltus steps of VLD_IN first are low level；
At the same time, the R ends meeting saltus step of latch circuit 20 is low level, and therefore saltus step is high level to RJ, and QN is still
High level is kept, therefore Q meeting saltus steps are low level output, so as to open the G0 of clock circuit 30 by phase inverter, release SM_
CLK；See again and synchronously withdraw circuit 40, because the saltus steps of VLD_IN from high to low are synchronously withdrawn from reset state, two SIM_CLK
Afterwards, PAD_SYNJ makes M digit counters 50 be withdrawn from reset state；
The clock of M digit counters 50 is effectively at this time and reset is invalid, starts counting up；
If the low level input of reset pin is long enough so that the highest order RPL_BIT of M digit counters 50
The Q ends of [n-1] are counted as height, thenFor low level, an effective PAD_RSTJ (low level is effective), while clock electricity are sent
The G1 on road 30 is turned off, and SIM_CLK is turned off, and M digit counters 50 stop counting,Remain low level.If by taking n=5 as an example,
Then the low level input of reset pin needs at least to continue 32 SIM_CLK cycles, could produce PAD_RSTJ from high to low
Saltus step；
If the low level input of reset pin is no long enough, VLD_IN is at the Q ends of RPL_BIT [n-1]
Withdrawn before non-set, then the R and S of latch circuit 20 at the same time for height, its Q output can also become higher, in clock circuit 30 G0 also by
Shut-off, SIM_CLK disappear, at the same synchronously withdraw circuit 40 and M digit counters 50 also can asynchronous reset, whole reset detection electricity
Road returns to its original state, and the saltus steps of PAD_RSTJ from high to low will not occur in whole process；
Situation is withdrawn after the saltus step of PAD_RSTJ generations from high to low, the G1 of clock circuit 30 is turned off, SIM_CLK
Be turned off, with the low level of foregoing reset pin do not have it is long enough compare, be a difference in that VLD_IN is being withdrawn
When (by 0 to 1 saltus step), the Q ends set of RPL_BIT [n-1], PAD_RSTJ is in low level and resets effective status, herein
Repeat no more.
It was found from above-described embodiment, increase clock synchronously withdraws circuit 40 for system clock on PAD_RSTJ, with
Ensure when effective asynchronous reset occurs for reset pin, whole system, which can ensure to reset, synchronously withdraws.
Above-mentioned the technical scheme in the embodiment of the utility model, at least has the following technical effect that or advantage：
By using the technical scheme in the embodiment of the utility model, the reliability of reset detection circuit is improved, is reduced
The energy consumption of reset detection circuit, and reset pin is multiplexed, i.e., reset pin can be used as GPIO.
Although having been described for the preferred embodiment of the utility model, those skilled in the art once know substantially
Creative concept, then can make these embodiments other change and modification.So appended claims are intended to be construed to wrap
Include preferred embodiment and fall into all change and modification of the scope of the utility model.
Claims (9)
- A kind of 1. reset detection circuit, it is characterised in that including：Reset request input circuit, latch circuit, clock circuit, synchronously withdraw circuit, M digit counters, the first phase inverter and Second phase inverter；The input terminal of the reset request input circuit is connected with reset pin, the output terminal of the reset request input circuit It is connected with the first input end of the latch circuit, the output terminal of the reset request input circuit passes through the first phase inverter Be connected with the reset terminal for synchronously withdrawing circuit, the output terminal of the latch circuit by the second phase inverter with it is described when First control terminal of clock circuit is connected, the output terminal of the clock circuit respectively with the clock signal for synchronously withdrawing circuit Input terminal is connected with the clock signal input terminal of the M digit counters, described synchronously to withdraw circuit and the M digit counters Reset terminal is connected；Wherein, the reset request input circuit is for receiving the effective reset request of low level of the reset pin input simultaneously The reset request is exported, the reset request that the latch circuit is used to export according to the reset request input circuit generates The connection control signal or shut-off control signal of clock circuit, the clock circuit are used for according to the connection control signal life Clock signal is closed into clock signal or according to the shut-off control signal, the circuit of synchronously withdrawing is used for according to described multiple The reset request control M digit counters of position request input circuit output are started to work, the run duration of the M digit counters At least through 2MAfter a clock cycle, output resets useful signal.
- 2. circuit as claimed in claim 1, it is characterised in that：The output terminal of the M digit counters is connected with the second control terminal of the clock circuit, is exported in the M digit counters When resetting useful signal, the clock circuit is based on the reset useful signal and closes clock signal.
- 3. circuit as claimed in claim 2, it is characterised in that：The output terminal of the M digit counters is connected with the second input terminal of the latch circuit, when the reset request is defeated The reset request for entering circuit output is withdrawn before the non-set of output terminal of the M digit counters, and the latch circuit output is high Level signal, so as to control the clock circuit to close clock signal.
- 4. circuit as claimed in claim 1, it is characterised in that：The reset request input circuit includes Enable Pin, input, output end, the first NOT gate and OR gate, the reset request The input terminal of input circuit is connected with the first input end of the OR gate, and the Enable Pin of the reset request input circuit passes through One NOT gate is connected with the second input terminal of the OR gate, and the output terminal of the OR gate is the output terminal of the reset request circuit；When the Enable Pin is high level, what is be connected with the input terminal of the reset request input circuit is used for described multiple The reset function of the reset pin of position request input circuit input reset signal is effective.
- 5. circuit as claimed in claim 4, it is characterised in that：When the Enable Pin is low level, the reset function of the reset pin is invalid, and the reset pin draws as GPIO Foot uses.
- 6. circuit as claimed in claim 3, it is characterised in that：The latch circuit is specially the S/R latch being made of the second NOT gate, the 3rd NOT gate and two NAND gates；The first input end of the latch circuit is the R ends of the S/R latch；Second input terminal of the latch circuit is the S ends of the S/R latch；The output terminal of the latch circuit is the Q ends of the S/R latch.
- 7. circuit as claimed in claim 6, it is characterised in that：The clock circuit includes the first clock module and second clock module, the output terminal of first clock module with it is described The input terminal of second clock module is connected；First control terminal of the clock circuit is the Enable Pin of first clock module, and the second of the clock circuit controls It is the output terminal of the second clock module to hold as the Enable Pin of the second clock module, the output terminal of the clock circuit.
- 8. circuit as claimed in claim 1, it is characterised in that：The circuit of synchronously withdrawing includes two sequentially connected first d type flip flops and the second d type flip flop；The output terminal of the clock circuit respectively with the clock signal input terminal of first d type flip flop and the second d type flip flop Clock signal input terminal is connected；The Q ends of first d type flip flop are connected with the D ends of second d type flip flop, the output terminal for synchronously withdrawing circuit For the output terminal of second d type flip flop.
- 9. circuit as claimed in claim 1, it is characterised in that：The M digit counters are M ripple counters, and the M ripple counter is the asynchronous M positions two being made of d type flip flop System up counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721088693.XU CN207301963U (en) | 2017-08-28 | 2017-08-28 | A kind of reset detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721088693.XU CN207301963U (en) | 2017-08-28 | 2017-08-28 | A kind of reset detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207301963U true CN207301963U (en) | 2018-05-01 |
Family
ID=62438914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721088693.XU Active CN207301963U (en) | 2017-08-28 | 2017-08-28 | A kind of reset detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207301963U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | A kind of reset detection circuit and reset detection method |
| CN112639954A (en) * | 2018-10-10 | 2021-04-09 | 深圳市柔宇科技股份有限公司 | GOA circuit, display device and display control method |
-
2017
- 2017-08-28 CN CN201721088693.XU patent/CN207301963U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | A kind of reset detection circuit and reset detection method |
| CN107463236B (en) * | 2017-08-28 | 2023-05-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
| CN112639954A (en) * | 2018-10-10 | 2021-04-09 | 深圳市柔宇科技股份有限公司 | GOA circuit, display device and display control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107463236A (en) | A kind of reset detection circuit and reset detection method | |
| CN103645794B (en) | Chip and method for achieving sleep mode wake-up through edge detection circuit | |
| CN207301963U (en) | A kind of reset detection circuit | |
| US9685953B1 (en) | Low latency asynchronous interface circuits | |
| CN107678532A (en) | A kind of low-power dissipation SOC wake module and low-power dissipation SOC | |
| CN104205755A (en) | Method, device, and system for delaying packets during a network-triggered wake of a computing device | |
| CN106100621A (en) | A kind of automatic reset structure for clock handoff procedure | |
| CN109032987A (en) | A kind of computer system and method accelerating domestic processor based on FPGA | |
| CN106502357A (en) | A kind of reset circuit and electronic equipment | |
| CN102111147B (en) | Asynchronous counter circuit and realizing method thereof | |
| CN207115391U (en) | A kind of automatic reset circuit | |
| CN107368255A (en) | Unlocking method, mobile terminal and computer-readable recording medium | |
| CN112733478B (en) | Apparatus for formal verification of a design | |
| GB2273834A (en) | Clock signal conditioning circuit | |
| CN107436856B (en) | Communication device with direct control and related method | |
| EP3428804A1 (en) | Biometric sensing system | |
| CN106096457B (en) | A kind of defence circuit of the anti-clock frequency error injection attacks of safety chip | |
| CN106066684B (en) | Master-slave mode SOC chip low power consumpting controling circuit | |
| CN205647472U (en) | Reset circuit and electronic equipment | |
| CN208092728U (en) | Device and electronic chip for detecting failure | |
| JP3018404B2 (en) | Microprocessor | |
| CN106557138B (en) | Servo-system and random start device | |
| CN105656472B (en) | A kind of priority decision circuitry | |
| CN102955545A (en) | Computer | |
| CN105718402B (en) | Programmable timing generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |