CN108337097B - Remote hardware reset system of optical communication equipment - Google Patents
Remote hardware reset system of optical communication equipment Download PDFInfo
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- CN108337097B CN108337097B CN201710486946.7A CN201710486946A CN108337097B CN 108337097 B CN108337097 B CN 108337097B CN 201710486946 A CN201710486946 A CN 201710486946A CN 108337097 B CN108337097 B CN 108337097B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
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- Optical Communication System (AREA)
Abstract
The invention discloses a remote hardware reset system of optical communication equipment, the equipment is connected with the optical communication equipment at the far end through optical fibers, the optical communication equipment at the local end and the optical communication equipment at the far end both comprise an optical module, a CPLD/FPGA chip, a series resistor and a power-on reset circuit, the optical module transmits a no-light alarm signal to the CPLD/FPGA chip, the CPLD/FPGA chip generates a reset signal after processing the no-light alarm signal and transmits the reset signal to the power-on reset circuit through the series resistor, and the power-on reset circuit performs hardware reset on the optical communication equipment at the local end and the optical communication equipment at the far end after receiving the reset signal. The invention can realize the remote fault elimination of the optical communication equipment, and has short fault elimination time and low fault elimination cost.
Description
Technical Field
The invention relates to the field of optical communication, in particular to a remote hardware resetting system of optical communication equipment.
Background
In order to eliminate such a fault, hardware reset needs to be performed on the optical communication device to enable the optical communication device to be in an initial state and to restart operation.
The hardware reset scheme adopted by the existing optical communication equipment is mainly a mode of power-on single reset or a mode of power-on single reset plus an external reset key, and if the hardware reset is required, manual field operation is required. However, optical communication equipment is often installed in an unattended machine room or a remote suburb or rural area, manual troubleshooting consumes time and labor, is not beneficial to timely troubleshooting, and is high in cost.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a remote hardware reset system for optical communication devices, which can remotely eliminate faults of the optical communication devices, has a short fault elimination time and a low fault elimination cost, and aims to overcome the defects of the prior art that the remote hardware reset cannot be performed, the fault elimination time is long, and the cost is high.
The technical scheme adopted by the invention for solving the technical problems is as follows: the optical communication equipment at the local end and the optical communication equipment at the far end are connected through optical fibers, the optical communication equipment at the local end and the optical communication equipment at the far end respectively comprise an optical module, a CPLD/FPGA chip, a serial resistor and a power-on reset circuit, the optical module transmits a non-optical alarm signal to the CPLD/FPGA chip, the CPLD/FPGA chip processes the non-optical alarm signal to generate a reset signal and transmits the reset signal to the power-on reset circuit through the serial resistor, the power-on reset circuit receives the reset signal and then performs hardware reset on the optical communication equipment at the local end and the optical communication equipment at the far end, and the CPLD/FPGA chip comprises 1 frequency divider and two frequency dividers, The system clock signal generation device comprises a plurality of sixteen frequency dividers, a plurality of reset signal generators and a plurality of phase inverters, wherein the sixteen frequency dividers are sequentially connected in series, one end of the series connection is connected with a clock signal output end of the two frequency dividers, the other end of the series connection is connected with a clock signal input end of the reset signal generator, a system clock signal is input to the clock signal input end of the two frequency dividers, the non-light alarm signal is input to the other input end of the reset signal generator, an output end of the reset signal generator is connected with an input end of the phase inverter, an output end of the phase inverter outputs the reset signal, the system clock signal generates a 10Hz clock after one-time two-time frequency division and 5-time sixteen-frequency division to trigger the reset signal generators, the reset signal generators define 1D trigger, when the rising edge of the input clock signal comes, and inputting the value of the non-optical alarm signal to the D trigger, and simultaneously inverting the non-optical alarm signal, then performing phase comparison with the D trigger, inverting the value after the phase comparison, and outputting a reset signal.
In the remote hardware resetting system of the optical communication device, the optical communication device at the office end and the optical communication device at the far end are subjected to hardware resetting by plugging and unplugging optical fibers on the optical communication device at the office end or the optical communication device at the far end.
In the remote hardware reset system of the optical communication equipment, the number of the sixteen frequency dividers is 5.
In the remote hardware reset system of the optical communication equipment, the clock signal input end of the sixteen frequency divider positioned at the beginning end is connected with the clock signal output end of the two frequency dividers, the clock signal output end of the sixteen frequency divider positioned at the beginning end is connected with the clock signal input end of the adjacent sixteen frequency divider, the clock signal input end of the sixteen frequency divider positioned at the tail end is connected with the clock signal output end of the adjacent sixteen frequency divider, and the clock signal output end of the sixteen frequency divider positioned at the tail end is connected with the clock signal input end of the reset signal generator.
In the remote hardware reset system of the optical communication equipment, when the rising edge of the no light alarm signal arrives, the reset signal outputs low level.
The remote hardware resetting system of the optical communication equipment has the following beneficial effects: because the optical communication equipment at the local end and the optical communication equipment at the far end both comprise the optical module, the CPLD/FPGA chip, the series resistor and the power-on reset circuit, the optical module transmits the lightless alarm signal to the CPLD/FPGA chip, the CPLD/FPGA chip generates a reset signal after processing the lightless alarm signal, and transmits the reset signal to the power-on reset circuit through the series resistor, the power-on reset circuit performs hardware reset on the optical communication device at the local end and the optical communication device at the far end after receiving the reset signal, it does not need to be reset manually, in addition, because the optical communication equipment generally has a CPLD/FPGA chip, therefore, the cost is not increased, only two I/O ports and a small amount of internal resources of the CPLD/FPGA are occupied, therefore, the optical communication equipment can remotely eliminate faults, and has short fault removal time and low fault removal cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of a remote hardware reset system of an optical communication device according to the present invention;
fig. 2 is a schematic circuit structure diagram of the CPLD/FPGA chip in the embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment of the remote hardware resetting system of an optical communication device according to the present invention, a schematic structural diagram of the remote hardware resetting system of an optical communication device is shown in fig. 1. In fig. 1, the remote hardware reset system of the optical communication device includes an optical communication device located at the office end and an optical communication device located at the far end, where the optical communication device located at the office end and the optical communication device located at the far end are connected by an optical fiber, and both the optical communication device located at the office end and the optical communication device located at the far end include an optical module, a CPLD/FPGA chip, a series resistor, and a power-on reset circuit, where the optical module transmits an alarm signal without light to the CPLD/FPGA chip for processing, the CPLD/FPGA chip generates a reset signal after processing the alarm signal without light, and transmits the reset signal to the power-on reset circuit through the series resistor, and the power-on reset circuit performs hardware reset on the optical communication device located at the office end and the optical communication device located at the far end after receiving the reset signal, so that manual reset is not required.
It is worth mentioning that the series resistor can separate the CPLD/FPGA chip from the power-on reset circuit, so as to ensure that the initial state of the I/O port of the CPLD/FPGA chip does not affect the reset of the optical communication device when the power is turned on. Because the optical communication equipment generally has a CPLD/FPGA chip, the cost is not increased additionally, and only two I/O ports and a small amount of internal resources of the CPLD/FPGA are occupied, so that the optical communication equipment can remotely eliminate faults, has short fault removing time and low fault removing cost.
In this embodiment, the optical fiber is plugged in or unplugged from the optical communication device located at the office end or the optical communication device located at the far end, so that hardware reset can be performed on the optical communication device located at the office end and the optical communication device located at the far end. That is to say, plugging and unplugging the optical fiber on the optical communication device located at the office end can implement hardware reset on the optical communication device located at the office end and the optical communication device located at the far end, and similarly plugging and unplugging the optical fiber on the optical communication device located at the far end can also implement hardware reset on the optical communication device located at the office end and the optical communication device located at the far end.
Fig. 2 is a schematic circuit structure diagram of the CPLD/FPGA chip in this embodiment. In fig. 2, the CPLD/FPGA chip includes 1 frequency divider DIV2, a plurality of sixteen frequency dividers DIV16, 1 reset signal generator PULSE and 1 inverter INV, the sixteen frequency dividers DIV16 are sequentially connected in series, one end of the series is connected to the clock signal output end of the frequency divider DIV2, the other end of the series is connected to the clock signal input end of the reset signal generator PULSE, a system clock signal clk25m is input to the clock signal input end of the frequency divider DIV2, a non-light alarm signal nop is input to the other input end of the reset signal generator PULSE, the output end of the reset signal generator PULSE is connected to the input end of the inverter INV, and the output end of the inverter INV outputs a reset signal reset. In this embodiment, the number of the sixteen frequency dividers DIV16 is 5, and of course, in other cases of this embodiment, the number of the sixteen frequency dividers DIV16 may be adjusted accordingly according to specific situations.
For several sixteen frequency dividers DIV16 connected in series, the clock signal input of the beginning sixteen frequency divider DIV16 is connected to the clock signal output of the two frequency dividers DIV2, the clock signal output of the beginning sixteen frequency divider DIV16 is connected to the clock signal input of its adjacent sixteen frequency divider DIV16, the clock signal input of the end sixteen frequency divider DIV16 is connected to the clock signal output of its adjacent sixteen frequency divider DIV16, and the clock signal output of the end sixteen frequency divider DIV16 is connected to the clock signal input of the reset signal generator PULSE.
In this embodiment, the system clock signal clk25m generates a clock of about 10Hz after being divided by two and 5 sixteen times to trigger the reset signal generator PULSE, which defines 1D flip-flops, and when the rising edge of the input clock signal inclk comes, the value of the input no-light alarm signal nop is given to the D flip-flop, and the inverted value of the no-light alarm signal nop is inverted and then anded with the D flip-flop, and the inverted value is given to the output reset signal reset. After the rising edge of the non-light alarm signal nop is realized, the reset signal reset outputs a low pulse with the period equal to that of the clock signal inclk. That is, when a rising edge of the no light alarm signal nop comes, the reset signal res outputs a low level.
It should be noted that, in this embodiment, the non-light alarm signal nop is at a high level when light is present and at a low level when light is absent, that is, a falling edge is generated when the optical fiber is pulled out, and a rising edge is generated when the optical fiber is inserted. The reset signal reset of the optical communication device is active low. Specifically, the system clock signal clk25m is first divided into a clock of about 10Hz to trigger the reset signal generator PULSE, capture the rising edge of the non-optical alarm signal nop, and when the rising edge of the non-optical alarm signal nop arrives, the reset signal generator PULSE starts outputting low level for a clock cycle and then outputs high level, so that a low PULSE of about 100ms is generated to reset the system hardware. The invention generates a low-pulse reset signal reset system by capturing the rising edge of the non-optical alarm signal nop, thereby realizing the remote hardware reset of the optical communication equipment.
In short, in this embodiment, the optical fiber is plugged to generate a rising edge of a non-optical alarm signal of the optical module, and then the rising edge is processed by the CPLD/FPGA chip to generate a reset signal, so that the optical communication device can remotely eliminate the fault, thereby shortening the fault elimination time and reducing the fault elimination cost.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A remote hardware reset system of optical communication equipment is characterized by comprising optical communication equipment positioned at a local end and optical communication equipment positioned at a far end, wherein the optical communication equipment positioned at the local end and the optical communication equipment positioned at the far end are connected through optical fibers, the optical communication equipment positioned at the local end and the optical communication equipment positioned at the far end respectively comprise an optical module, a CPLD/FPGA chip, a series resistor and a power-on reset circuit, the optical module transmits a lightless alarm signal to the CPLD/FPGA chip, the CPLD/FPGA chip generates a reset signal after processing the lightless alarm signal and transmits the reset signal to the power-on reset circuit through the series resistor, and the power-on reset circuit performs hardware reset on the optical communication equipment positioned at the local end and the optical communication equipment positioned at the far end after receiving the reset signal, the CPLD/FPGA chip comprises 1 frequency divider, a plurality of sixteen frequency dividers, 1 reset signal generator and 1 inverter, wherein the sixteen frequency dividers are sequentially connected in series, one end of the series connection is connected with a clock signal output end of the frequency divider, the other end of the series connection is connected with a clock signal input end of the reset signal generator, a system clock signal is input to the clock signal input end of the frequency divider, the non-light alarm signal is input to the other input end of the reset signal generator, the output end of the reset signal generator is connected with the input end of the inverter, the output end of the inverter outputs the reset signal, the system clock signal generates a 10Hz clock after one-time frequency division and 5-time sixteen-frequency division to trigger the reset signal generator, and the reset signal generator defines 1D trigger, when the rising edge of the input clock signal comes, the value of the input lightless alarm signal is sent to the D trigger, the lightless alarm signal is inverted and then is in AND-phase with the D trigger, and the inverted value is sent to the output reset signal; and plugging optical fibers on the optical communication equipment at the local side or the optical communication equipment at the far end to realize hardware reset of the optical communication equipment at the local side and the optical communication equipment at the far end.
2. The optical communication device remote hardware reset system of claim 1, wherein the number of the sixteen frequency dividers is 5.
3. The optical communication device remote hardware reset system of claim 2, wherein the clock signal input terminal of the sixteen-frequency divider at the beginning is connected to the clock signal output terminal of the two-frequency divider, the clock signal output terminal of the sixteen-frequency divider at the beginning is connected to the clock signal input terminal of the sixteen-frequency divider adjacent thereto, the clock signal input terminal of the sixteen-frequency divider at the end is connected to the clock signal output terminal of the sixteen-frequency divider adjacent thereto, and the clock signal output terminal of the sixteen-frequency divider at the end is connected to the clock signal input terminal of the reset signal generator.
4. The optical communication device remote hardware reset system of any of claims 1 to 2, wherein the reset signal outputs a low level when a rising edge of the no light alarm signal arrives.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710039109 | 2017-01-19 | ||
| CN201710039109X | 2017-01-19 |
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| CN108337097A CN108337097A (en) | 2018-07-27 |
| CN108337097B true CN108337097B (en) | 2020-11-03 |
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| CN201710486946.7A Active CN108337097B (en) | 2017-01-19 | 2017-06-23 | Remote hardware reset system of optical communication equipment |
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| CN111200425A (en) * | 2020-01-23 | 2020-05-26 | 华为技术有限公司 | Reset circuit and related electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100646473B1 (en) * | 2004-05-24 | 2006-11-15 | 에스케이 텔레콤주식회사 | Remote release device of base transceiver station using optical network unit |
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