CN101515796B - Digital signal noise filtering device - Google Patents
Digital signal noise filtering device Download PDFInfo
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- CN101515796B CN101515796B CN2009100570216A CN200910057021A CN101515796B CN 101515796 B CN101515796 B CN 101515796B CN 2009100570216 A CN2009100570216 A CN 2009100570216A CN 200910057021 A CN200910057021 A CN 200910057021A CN 101515796 B CN101515796 B CN 101515796B
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Abstract
The invention provides a digital signal noise filtering device comprising a first counting circuit for counting high-level input signals, a second counting circuit for counting low-level input signals and a RS trigger with an S end which is connected with the output of the first counting circuit and a R end which is connected with the output of the second counting circuit. As the first counting circuit and the second counting circuit do not respond to continuous false positive pulses and false negative pulses respectively, the RS trigger still outputs low level in spite of the emergence of the false positive pulses and still outputs high level in spite of the emergence of the false negative pulses after the outputs of the two counters are treated by the SR trigger; in such a way, when the digital signal noise filtering device is used for blanking and filtering output signals of a power supply detection circuit, the digital signal noise filtering device can effectively filter the continuous false positive pulses and the false negative pulses, and the misoperation during the false power up or the false power off of a power supply can be avoided at the same time.
Description
Technical field
The present invention relates to noise filtering and limiting technology, particularly a kind of noise filtering device of digital signal.
Background technology
Along with development of integrated circuits, increasing signal generating circuit, testing circuit and terminal receiving circuit all are integrated into chip internal, to reduce cost.Since between the element in the raising of integrated level, chip and the distance between the line more and more littler, make that the coupling between signal and signal, signal and the power supply ground becomes very important; In addition, some is used to detect or judge the on-chip circuit of sheet external signal, can't provide correct signal owing to be subjected to the influence of sheet external noise.Just because of the existence of aforementioned coupling and sheet external noise, cause to introduce noise contribution unavoidably in the input signal of terminal receiving circuit, and then can cause misoperation.So, be necessary the input signal of terminal receiving circuit is carried out filtering.
Input signal for the terminal receiving circuit, it is the digital signal through transforming normally, thereby have a variety of to its mode of carrying out filtering: a kind of mode is to adopt Schmidt trigger, it can suppress the less noise signal of amplitude, but the but effectively filtering of noise of and certain time big for amplitude; What another kind was comparatively commonly used is the filtering mode that the RC filter circuit adds Schmidt trigger, it not only can carry out filtering on the amplitude to noise, can also carry out temporal filtering, lengthening along with the noise duration, corresponding R, the C value also increases thereupon, this realizes than being easier on pcb board, yet, along with chip integration is more and more higher, require in sheet, to realize filtering in the same way, will cause conflicting between quiescent dissipation and the area, and the method that solves this contradiction is to adopt digital filter to replace traditional analog filter to carry out filtering, so can effectively reduce power consumption and area.
But Design of Digital Filter need possess the background knowledge of Digital Signal Processing, also relates to complicated modeling of Z territory and derivation simultaneously, therefore also has certain limitation in actual applications.More convenient reliable method is to adopt so-called blanking filter circuit (blanking circuits) to carry out filtering at present, it also is to adopt digital mode to carry out noise filtering, but do not relate to derivation complicated in the digital filter, but by the optimal design on the sequential, the noise of finishing certain time carries out filtering.It is very little that this filter circuit not only takies area of chip, and do not consume quiescent dissipation.Even so, but a lot of blanking filter circuits commonly used all have drawback separately: perhaps can only carry out filtering or can only carry out filtering to the false negative pulse of input signal the false positive pulse of input signal, and those circuit that can be simultaneously false positive pulse and false negative pulse be carried out filtering, but there are problems such as filtering is not clean.
For example, please refer to U.S. Pat No. 5418486, as shown in Figure 1, it provides a kind of device that input signal is carried out the eliminated noise filtering, this device is a blanking filter circuit, comprises 204, one of delay circuits by 250 and 252 set-reset flip-floops of forming and part combinational logic.The physical circuit figure of contrast among Fig. 1, delay circuit 204 is used to set a fixing time-delay, and its structure can be the delay unit of Current Control or based on the delay unit of counter.Delay time greater than this when input signal 202 pulse durations, then be considered to actual signal, otherwise be the ghost pulse signal; AND door 220 with input signal 202 and by the input signal 208 of being delayed time with after, deliver to the SET input 222 of set-reset flip-floop; NOR door 210 is with input signal 202 with by the input signal 208 of being delayed time mutually or after non-, deliver to AND door 230,230 with the inverted signal 236 of this signal and input signal 202 with after, deliver to the RESET input 232 of set-reset flip-floop.Can see that from Fig. 2 and 3 216 waveform is identical with 232 waveform, obviously, the effect that adds INV door 238 and AND door 230 herein just makes treated input signal be transferred to the time-delay approximately equal of the SET end 222 and the RESET end 232 of set-reset flip-floop.Please refer to Fig. 2 and Fig. 3, wherein, what indicate S is the actual signal pulse, indicates the noise pulse that is of N, as seen from Figure 2, if a noise pulse within filtering delay-time, only occurs, then can be clean by filtering; As seen from Figure 3, if occur a plurality of noise pulses continuously within filtering delay-time, the sordid situation of filtering can appear then.
For another example, please refer to U.S. Patent application US 2002/0101945 A1 number, as shown in Figure 4, it provides a kind of device that input signal is carried out the blanking Filtering Processing.Described digital blanking circuit comprises that two latchs 50 and 54, one blanking time-delays of 52, one MUX circuit produce circuit 22.For latch 50, when LATCH=" 1 ", when running into the trailing edge of input signal, its can with after " 0 " signal latch, and when LATCH=" 0 ", its output is transparent to importing; For latch 52, when LATCH=" 0 ", when running into the rising edge of input signal, its can with after " 1 " signal latch, when LATCH=" 1 ", its output is transparent to importing; Produce circuit 22 for the blanking time-delay, it is subjected to the control of the output 26 of MUX circuit 54, produces to select signal SELECT, be used for control lock storage 50 and 52, and as the selection signal of MUX circuit 54, when SELECT=" 1 ", the OUT=A of MUX, when SELECT=" 0 ", the OUT=B of MUX.
As can be seen from Figure 5, behind the trailing edge of input signal 10, there is noise 12, suppose that the SELECT signal begins to be " 1 ", then latch 50 latchs " 0 " behind the trailing edge of input signal, and its output A is transferred to the output 26 of MUX circuit 54, make output 26 by " 1 " changes " 0 " and trigger blanking time-delay generation circuit 22, make its output SELECT after the time-delay of setting by " 1 " change " 0 ", before this, latch 52 transparent (being B=input), but because SELECT=" 1 ", 52 output B can't be transferred to the output 26 of MUX circuit 54; Behind the rising edge of input signal 10, there is noise 12, at this moment, SELECT is " 0 ", latch 52 latchs " 1 " behind the rising edge of input signal, and its output B is transferred to the output 26 of MUX circuit 54, make output 26 also trigger the blanking time-delay once more and produce circuit 22 by " 0 " change " 1 ", make its output SELECT after the time-delay of setting by " 0 " change " 1 ", to wait for the arrival of input signal 10 next trailing edges, before this, latch 50 transparent (being A=input), but because SELECT=" 0 ", 50 output A can't be transferred to the output 26 of MUX circuit 54.Through after the above-mentioned blanking Filtering Processing, output signal 26 is exactly to the filtered output signal of input signal 10 blankings.Although described blanking circuit can carry out filtering to the false positive pulse and the false negative pulse of input signal 10, and output is to almost not time-delay of input, but whether its rising edge or trailing edge itself to input signal 10 is that real saltus step can't be judged, for example, when input signal 10 is " 0 ", but make input signal 10 that a series of " 0 " and " 1 " upset takes place sometime owing to noise after, return to " 0 " again, if the width of these upsets is all less than the filtering delay-time of setting, exporting 26 so answers described maintenance " 0 " constant, but the output of this circuit will inevitably be overturn, thereby produces misoperation.
Given this, be necessary to design and a kind ofly new input signal carried out the method for blanking Filtering Processing to address the above problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of described digital signal noise filtering device, so that continuous false positive pulse and false negative pulse to input signal all can be carried out effective filtering, also can avoid because of judging the problem of the misoperation whether the input signal edge truly brings simultaneously.
In order to solve the problems of the technologies described above, the solution that the present invention proposes is: a kind of digital signal noise filtering device, it comprises: signal input interface, first counting circuit that is connected and has reset function with described signal input interface, be used for beginning counting during for high level when input signal, and its output is second state by first state transition just when counting reaches 6.5 input clock cycles, and its output returns back to first state at once when input signal is low level, described first counting circuit comprises the input clock signal end, first reset terminal and the first asynchronous clock counter that forms by 3 d type flip flops, described input clock signal end is used for the receive clock signal, described first reset terminal is used to insert external reset signal to reset, and the described first asynchronous clock counter is used for beginning counting according to the clock signal of input; Second counting circuit that is connected and has reset function with described signal input interface, be used for beginning counting during for low level when input signal, and its output is second state by first state transition just when counting reaches 6.5 input clock cycles, and its output returns back to first state at once when input signal is high level, described second counting circuit comprises the input clock signal end, second reset terminal and the second asynchronous clock counter that forms by 3 d type flip flops, described input clock signal end is used for the receive clock signal, described second reset terminal is used to insert external reset signal to reset, and the described second asynchronous clock counter is used for beginning counting according to the clock signal of input; And rest-set flip-flop, its S end is connected with the output of described first counting circuit, and its R end is connected with the output of described second counting circuit.
In addition, described digital signal noise filtering device also comprises the Schmidt circuit that is connected with described signal input interface and is used for sending into behind the noise of earlier preliminary filtering input signal described first counting circuit and second counting circuit, and described Schmidt circuit can comprise the schmitt inverter that is connected with input signal, and the inverter that is connected with described schmitt inverter output.
Have, when described first state is a low level, when described second state was high level, described rest-set flip-flop adopted two NOR gate cross-couplings to form again; When described first state is a high level, when described second state was low level, described rest-set flip-flop circuit adopted two NAND gate cross-couplings to form.
In sum, first counting circuit of digital signal noise filtering device of the present invention and second counting circuit are not made a response to continuous false positive pulse and false negative pulse respectively, therefore, when false positive pulse occurring, the rest-set flip-flop circuit is output low level still, when false negative pulse occurring, the rest-set flip-flop circuit is still exported high level, so can carry out effective filtering, also can avoid because of judging the problem of the misoperation whether the input signal edge truly brings simultaneously continuous false positive pulse and false negative pulse.
Description of drawings
Fig. 1 is a kind of existing digital noise filtering circuit schematic diagram;
Fig. 2 is the existing digital noise filtering circuit of a Fig. 1 working waveform figure;
Fig. 3 is existing another working waveform figure of digital noise filtering circuit of Fig. 1;
Fig. 4 is another existing digital noise filtering circuit schematic diagram;
Fig. 5 is the working waveform figure of Fig. 4 digital noise filtering circuit;
Fig. 6 is the structured flowchart of digital signal noise filtering device of the present invention
Fig. 7 is the schematic diagram of digital signal noise filtering device one embodiment of the present invention;
Fig. 8 is the working waveform figure of Fig. 7 digital signal noise filtering device;
Fig. 9 is the schematic diagram of another embodiment of digital signal noise filtering device of the present invention.
The main element symbol description
The first asynchronous clock timing, 61,91 second asynchronous clock timing 62,92
The device device
Rest-set flip-flop 63,93 inverters 64,68,97
Schmitt inverter 65,94 inputs and door 79,80
Not gate 110,111 NAND gate 108,109
With door 69,70,71, d type flip flop 73,74,75,
72，95，96， 76，77，78，
98，99， 102，103，
100，101 104，105，
106，107
NOR gate 66,67,81,
82
Embodiment
Content of the present invention, advantage and purpose will be set forth in the following description of the embodiments.
The present invention is directed to the shortcoming of above-mentioned digital blanking filtering method, improved, a kind of more reliable digital blanking filtering implementation method is provided.
See also Fig. 6 and Fig. 7, digital signal noise filtering device of the present invention comprises: signal input part, Schmidt circuit, first counting circuit, second counting circuit, rest-set flip-flop, and signal output part.
Described Schmidt circuit is connected with signal input part, be used for and send into described first counting circuit and second counting circuit after the medium and small amplitude noise filtering of input signal INPUT, it comprises the schmitt inverter 65 that is connected with input signal INPUT, and the inverter 68 that is connected with described schmitt inverter 65 outputs, and described inverter 68 is used for anti-phase once more by the anti-phase input signal of described schmitt inverter 65.
Described first counting circuit has the input clock signal end and first reset terminal, be used for when input signal INPUT is high level, beginning counting according to the clock signal of being imported, and its output is second state (high level) by first state (low level) saltus step just when counting reaches preset number (for example 6.5 input clock cycles), and its output returns back to low level at once when input signal is low level, and described first reset terminal is used to insert external reset signal so that described first counting circuit resets.Described first counting circuit comprises one first asynchronous clock counter 61, it comprises 3 d type flip flops 73 that have reset terminal R, 75 and 77, three's reset signal rst by the signal of inverter 68 output and external reset signal RSTN through with door 71 with after obtain, the clock CK of d type flip flop 73 is from controlled clock signal ck1, the clock CK of d type flip flop 75 is the Q output of d type flip flop 73, the clock CK of d type flip flop 77 is the Q output of d type flip flop 75, d type flip flop 73,75 and 77 D input is all exported from the Q of self, d type flip flop 73,75 and 77 output Q11, Q12 and Q13 are sent to wherein three inputs of one four input and door 79, four inputs directly link to each other with external reset signal RSTN with the 4th input of door 79, the output vf1 of four inputs and door 79 is sent to an input of NOR gate 67, another input of NOR gate 67 inserts through the anti-phase RSTN signal of inverter 64, its output signal is input to and door 69, insert external timing signal CLK_IN with another input of door 69, its output signal is access in the clock end of d type flip flop 73 as controlled clock signal ck1.
Described second counting circuit has the input clock signal end and second reset terminal, be used for when input signal is low level, beginning counting according to the clock signal of being imported, and when counting when reaching preset number (for example 6.5 input clock cycles) its to export first state (low level) saltus step be second state (high level), and its output answer at once is low level when input signal is high level, and described second reset terminal is used to insert external reset signal so that described second counting circuit resets.Described second counting circuit comprises the second asynchronous clock counter 62, it comprises 3 d type flip flops 74 that have reset terminal R, 76 and 778, three's reset signal rst by the signal of schmitt inverter 65 output and external reset signal RSTN through with door 72 with after obtain, the clock CK of d type flip flop 74 is from controlled clock signal ck2, the clock CK of d type flip flop 76 is the Q output of d type flip flop 74, the clock CK of d type flip flop 78 is the Q output of d type flip flop 76, d type flip flop 74,76 and 78 D input is all exported from the Q of self, d type flip flop 74,76 and 78 output Q21, Q22 and Q23 are sent to wherein three inputs of four inputs and door 80, four inputs directly link to each other with external reset signal RSTN with the 4th input of door 80, the output vf2 of four inputs and door 80 is sent to an input of NOR gate 66, another input of NOR gate 66 inserts through the anti-phase RSTN signal of inverter 64, its output signal is input to and door 70, insert external timing signal CLK_IN with another input of door 70, its output signal is access in the clock end of d type flip flop 74 as controlled clock signal ck2.
The output of the S of described rest-set flip-flop 63 end and described first counting circuit (promptly four importing and 79 output vf1) is connected, the output of its R end and described second counting circuit (promptly four importing and 80 output vf2) is connected, it adopts two NOR gate 81 and 82 cross-couplings to form, the output (being the Q end) that is correspondingly provided with the NOR gate 82 of R end is the output OUTPUT of described rest-set flip-flop, it is signal output part, the signal of its output is compared to input signal, be delayed a preset number time of day, promptly time of delay Tdelay=6.5 input clock cycle.The truth table of rest-set flip-flop 63 is as follows:
| S(SET)? | R(RESET)? | Q(OUTPUT)? | Q |
| First state: 0 | First state: 0 | Keep | Keep |
| First state: 0 | Second state: 1 | 0? | 1? |
| Second state: 1 | First state: 0 | 1? | 0? |
| Second state: 1 | Second state: 1 | Forbid | Forbid |
See also Fig. 8, it is the working waveform figure of described digital signal noise filtering device, wherein, INPUT is the digital input signals that has noise, 12 and 15 rising edge and trailing edges that are respectively actual signal wherein, 13,14,16,17 are respectively false trailing edge and rising edge, and S1 and S2 are the actual signal pulse, N1, N2 are false noise negative pulse, and N3, N4 are false noise positive pulse; CLK_IN is an external timing signal, and it can be from the frequency division or the frequency multiplication of system clock, system clock, and the setting of clock cycle is relevant with filtering delay-time; RSTN is an external reset signal, and it can be the power or power-down reset signal of chip; Ck1 is the controlled clock input signal of the first asynchronous clock counter 61; Rst is the reset signal of the first asynchronous clock counter 61; Vf1 is the output signal of four inputs and door 79; Ck2 is the controlled clock input signal of the second asynchronous clock counter 62; Rsti is the reset signal of the second asynchronous clock counter 62; Vf2 is the output signal of four inputs and door 80; OUTPUT is the output signal of described digital signal noise filtering device.The concrete operation principle of described digital signal noise filtering device is as follows:
One, when outside RSTN is " 0 ", no matter why input signal INPUT is worth, the first asynchronous clock counter 61 and the second asynchronous clock counter 62 all are in reset mode (rst=" 0 " and rsti=" 0 "), the output Q11 of the first asynchronous clock counter 61, Q12 and Q13 are " 0 ", make vf1 keep " 0 ", the output Q21 of the second asynchronous clock counter 62, Q22 and Q13 also are " 0 ", make vf2 also remain " 0 ", the S of rest-set flip-flop 63 and R end is " 0 " like this, make the output Q of rest-set flip-flop 63 keep original value constant, promptly the output OUTPUT of described digital signal noise filtering device keeps original value.In addition, when RSTN is " 0 ", can shield external timing signal, make internal clock signal ck1 and ck2 keep " 0 " by NOR gate 67 and 66.
Two, when outside RSTN is " 1 ", described digital signal noise filtering device just can carry out following filtering operation:
1, as shown in Figure 8, suppose when input signal INPUT begins to low level, can make the first asynchronous clock counter 61 be in reset mode (rst=" 0 "), the second asynchronous clock counter 62 is counted (rsti=" 1 "), when the second asynchronous clock counter 62 after preset number (i.e. 6.5 clock cycle), the output vf2 of four inputs and door 80 is by " 0 " change " 1 ", and remain " 1 ", at this moment, the S end of rest-set flip-flop 63 is input as " 0 ", and the R end is input as " 1 ", if before the output Q of rest-set flip-flop 63 is " 0 ", then keep " 0 " constant, if before the Q is " 1 ", then be changed to " 0 ", make that output OUTPUT is " 0 ", simultaneously, the output vf2 of four inputs and door 80 is sent to the input of NOR gate 66, the output of NOR gate 66 is become " 0 ", and by shielding external timing signal CLK_IN with door 70, " 1 " of four inputs and the output vf2 of door 80 makes the input clock signal ck2=" 0 " of the second asynchronous clock counter 62, till will be held input signal INPUT and uprise.
2, when input signal INPUT at 12 places during by low uprising (S1), can make the second asynchronous clock counter 62 be in reset mode (rsti=" 0 "), the first asynchronous clock counter 61 is counted (rst=" 1 "), when the first asynchronous clock counter 61 after preset number (i.e. 6.5 clock cycle), the output vf1 of four inputs and door 79 is by " 0 " change " 1 ", and remain " 1 ", four inputs and door 80 output vf2 when input signal INPUT uprises by reset, at this moment, the S end of rest-set flip-flop 63 is input as " 1 ", and the R end is input as " 0 ", so, the output Q of rest-set flip-flop 63 after the filtering delay-time Tdelay that sets by " 0 " change " 1 ", make output OUTPUT by " 0 " change " 1 ", simultaneously, the output vf1 of four inputs and door 79 is sent to the input of NOR gate 67, the output of NOR gate 67 is become " 0 ", and by shielding external timing signal CLK_IN with door 69, make the input clock signal ck1=" 0 " of the asynchronous clock counter 61 of winning, four inputs will be held till the input signal INPUT step-down with the output vf1 of door 79 " 1 ".
3, when input signal INPUT at 13 and 14 places (N1 during by high step-down, N2), the first asynchronous clock counter 61 is in reset mode (rst=" 0 "), the second asynchronous clock counter 62 is counted (rsti=" 1 "), because the low level width of N1 and N2 is less than filtering delay-time Tdelay, so the second asynchronous clock counter 62 fails to count down to preset number, and input signal INPUT saltus step be high level, so four inputs can be by " 0 " change " 1 " with the output vf2 of door 80, it is any variation that the low level pulse at N1 or N2 place can not cause four inputs and the output vf2 of door 80, four inputs will remain " 0 " with the output vf2 of door 80, four inputs and door 79 output vf1 when input signal INPUT step-down by reset, at this moment, the S end input of rest-set flip-flop 63 and the input of R end are " 0 ", the output Q of rest-set flip-flop 63 keeps original high level constant, though, after input signal INPUT rising edge 18, four inputs can become " 1 " by " 0 " with the output vf1 of door 79, make the S end of rest-set flip-flop 63 be input as " 1 ", but because the input of R end still is " 0 ", so the high level of the output Q of rest-set flip-flop 63 can not be changed, promptly output signal OUTPUT can not respond false negative pulse N1 and N2.
4, when input signal INPUT at 15 places during by high step-down (S2), the first asynchronous clock counter 61 is in reset mode (rst=" 0 "), the second asynchronous clock counter 62 is counted (rsti=" 1 "), since input signal INPUT from trailing edge 15 to rising edge duration of 16 greater than 6.5 input clock cycles, so four inputs can be by " 0 " change " 1 " with the output vf2 of door 80, and remain " 1 ", four inputs and door 79 output vf1 when input signal INPUT step-down by reset, at this moment, the S end of rest-set flip-flop 63 is input as " 0 ", and the R end is input as " 1 ", the output Q of rest-set flip-flop 63 after 6.5 input clock cycles by " 1 " change " 0 ", make output OUTPUT by " 1 " change " 0 ", simultaneously, the output vf2 of four inputs and door 80 is sent to the input of NOR gate 66, the output of NOR gate 66 is become " 0 ", and by shielding external timing signal CLK_IN with door 70, " 1 " of four inputs and the output vf2 of door 80 makes the input clock signal ck2=" 0 " of the second asynchronous clock counter 62, till will be held input signal INPUT and uprise.
5, when input signal INPUT at 16 and 17 places (N3 during by low uprising, N4), the second asynchronous clock counter 62 is in reset mode (rsti=" 0 "), the first asynchronous clock counter 61 is counted (rst=" 1 "), because the width of N3 and N4 place high level is less than 6.5 input clock cycles, so four inputs can be by " 0 " change " 1 " with the output vf1 of door 79, it is any variation that the high level pulse at N3 or N4 place can not cause four inputs and the output vf1 of door 79, its output vf1 will remain " 0 ", four inputs and door 80 output vf2 when input signal INPUT uprises by reset, at this moment, the S end input of rest-set flip-flop 63 and the input of R end are " 0 ", the output Q of rest-set flip-flop 63 keeps original low level constant, though, after input signal INPUT trailing edge 19, four inputs can become " 1 " by " 0 " with the output vf2 of door 80, make the R end of rest-set flip-flop 63 be input as " 1 ", but because the input of S end still is " 0 ", so the low level of the output Q of rest-set flip-flop 63 can not be changed, promptly output signal OUTPUT can not respond false positive pulse N3 and N4.
It should be noted that rest-set flip-flop 63 when S holds input and the input of R end to be " 1 ", is to forbid attitude should being in this state by the described rest-set flip-flop 63 of avoiding.From above-mentioned analysis as can be known, when outside RSTN was " 0 ", input of S end and the input of R end were " 0 "; When outside RSTN is " 1 ", the first asynchronous clock counter 61 and the second asynchronous clock counter 62 are different according to input signal INPUT's, always can guarantee at any time, have only one to be in count status among both, and another is in reset mode, makes four inputs and door 79 and 80 must have one to be output as " 0 ", this shows, at any time, rest-set flip-flop 63 can not be " 1 " in input of S end and the input of R end simultaneously, has avoided rest-set flip-flop 63 to be in the possibility of forbidding attitude.
Have, in the present invention, the default count number of each counter is 6.5*T again, and wherein, T is the cycle of outside input clock CLK_IN, because the upset edge of input signal can be just in time and the rising edge of clock signal alignment, so the deviation of filtering delay-time exists
In, the filtering signal of actual like this output, compared to input signal, its delay time Tdelay is in the scope of 6T-7T.
Above-described is a kind of form of the present invention, but the present invention is not limited to described form, physical circuit can change according to application requirements: as the requirement according to filtering delay-time, can regulate the cycle of input clock CLK_IN, also can change the number of d type flip flop in each counter, can also form first counting circuit and second counting circuit etc. with counter with auto-reset function and simple gate.In addition, rest-set flip-flop can adopt two cross-linked modes of NAND gate to replace herein two cross-linked modes of NOR gate and build, and just logic should be done change slightly, specifically can be referring to Fig. 9, as shown in Figure 9, Schmidt circuit comprises schmitt inverter 94 and inverter 97; First counting circuit comprises: the first asynchronous clock counter 91, comprise 3 d type flip flops 102,104 and 106 that have reset terminal R again with door 95,98 and 100, four input nand gates 108, the first asynchronous clock counters 91; Second counting circuit comprises: the second asynchronous clock counter 92, comprise 3 d type flip flops 103,105 and 107 that have reset terminal R again with door 96,99 and 101, four input nand gates 109, the second asynchronous clock counters 92; Rest-set flip-flop 93 adopts two NAND gate 110 and 111 cross-couplings to form, and the truth table of rest-set flip-flop 93 is as follows:
| S(SET)? | R(RESET)? | Q(OUTPUT)? | Q |
| Second state: 0 | Second state: 0 | Forbid | Forbid |
| Second state: 0 | First state: 1 | 1? | 0? |
| First state: 1 | Second state: 0 | 0? | 1? |
| First state: 1 | First state: 1 | Keep | Keep |
Because the connected mode and the operation principle of each element of the connected mode of each element and operation principle and digital signal noise filtering device shown in Figure 7 are similar, so no longer repeat at this.
Aforesaid digital signal noise filtering device in the single-phase electric energy meter chip, is mainly used in the output signal of power sense circuit is carried out blanking filtering, powers on or misoperation during false power down in the power supply falseness avoiding.The filtering application of power supply detection range is one of application of the present invention, application of the present invention is in no way limited to this, at the terminal receiving circuit, the pwm pulse output circuit, pulse-generating circuit in the noise circumstance etc. need carry out the occasion of filtering to supplied with digital signal, can carry out blanking filtering with circuit of the present invention.
In sum, beneficial effect of the present invention is as follows:
1) all can carry out effective filtering to the false positive pulse and the false negative pulse of input signal
2) solved in the existing blanking circuit problem that can't judge the misoperation that the input signal edge is whether true and bring to can't the filtering clean problem of continuous ghost pulse and existing blanking circuit
3) d type flip flop in each counter adopts the asynchronous clock mode, the number of filtering delay-time and d type flip flop is near exponential relationship, when needing the filtering delay-time of long period, under identical input clock cycle T, with some based on d type flip flop and adopt the counter of synchronised clock or the implementation method of shift register to compare, can save a lot of hardware spendings, because adopt the counter of synchronised clock or the mode of shift register, the number of its filtering delay-time and d type flip flop is linear, so under identical time delay condition, it need adopt the more d type flip flop of more number
4) adopt the reset signal of system reset, when having avoided circuit to start working,, and cause that the input of rest-set flip-flop is in the problem of forbidding attitude because counter output may be in nondeterministic statement as blanking circuit
Above-mentioned description to embodiment is can understand and apply the invention for ease of those skilled in the art.The person skilled in the art obviously can easily make various modifications to these embodiment, and needn't pass through performing creative labour being applied in the General Principle of this explanation among other embodiment.Therefore, the invention is not restricted to the embodiment here, those skilled in the art should be within protection scope of the present invention for improvement and modification that the present invention makes according to announcement of the present invention.
Claims (5)
1. digital signal noise filtering device comprises signal input interface, rest-set flip-flop and is connected the signal output interface of described rest-set flip-flop output, it is characterized in that described digital signal noise filtering device further comprises:
First counting circuit with reset function, be connected with described signal input interface, be used for beginning counting during for high level when input signal, and its output is second state by first state transition just when counting reaches 6.5 input clock cycles, and its output returns back to first state at once when input signal is low level; Described first counting circuit comprises input clock signal end, first reset terminal and the first asynchronous clock counter that is formed by 3 d type flip flops, described input clock signal end is used for the receive clock signal, described first reset terminal is used to insert external reset signal to reset, and the described first asynchronous clock counter is used for beginning counting according to the clock signal of input;
Second counting circuit with reset function, be connected with described signal input interface, be used for beginning counting during for low level when input signal, and its output is second state by first state transition just when counting reaches 6.5 input clock cycles, and its output returns back to first state at once when input signal is high level; Described second counting circuit comprises input clock signal end, second reset terminal and the second asynchronous clock counter that is formed by 3 d type flip flops, described input clock signal end is used for the receive clock signal, described second reset terminal is used to insert external reset signal to reset, and the described second asynchronous clock counter is used for beginning counting according to the clock signal of input;
Wherein, the output of described first counting circuit is connected with the S of described rest-set flip-flop end, and the output of described second counting circuit is connected with the R of described rest-set flip-flop end.
2. digital signal noise filtering device as claimed in claim 1, it is characterized in that described digital signal noise filtering device also comprises: be connected with described signal input interface and be used for first preliminary filtering input signal noise after export it Schmidt circuit of described first counting circuit and second counting circuit to.
3. digital signal noise filtering device as claimed in claim 2 is characterized in that: described Schmidt circuit comprises the schmitt inverter that is connected with signal input interface, and the inverter that is connected with described schmitt inverter output.
4. digital signal noise filtering device as claimed in claim 1 is characterized in that: when described first state is a low level, when described second state was high level, described rest-set flip-flop adopted two NOR gate cross-couplings to form.
5. digital signal noise filtering device as claimed in claim 1 is characterized in that: when described first state is a high level, when described second state was low level, described rest-set flip-flop adopted two NAND gate cross-couplings to form.
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| CN2009100570216A CN101515796B (en) | 2009-04-02 | 2009-04-02 | Digital signal noise filtering device |
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| CN101515796B true CN101515796B (en) | 2011-02-09 |
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| WO2015165074A1 (en) * | 2014-04-30 | 2015-11-05 | Abb Technology Ltd | Apparatus and method for filtering noises in signal |
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| CN109039307B (en) * | 2018-08-30 | 2022-07-05 | 华润微集成电路(无锡)有限公司 | Double-edge anti-shake circuit structure |
| CN109286389B (en) * | 2018-11-30 | 2023-10-27 | 成都嘉纳海威科技有限责任公司 | Signal discrimination device and method for burst mode limiting amplifier |
| CN112713895B (en) * | 2019-10-24 | 2024-02-09 | 珠海格力电器股份有限公司 | Clock detection circuit and method |
| CN111092611A (en) * | 2019-11-19 | 2020-05-01 | 优利德科技(中国)股份有限公司 | Signal processing device and method with small edge slope |
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