CN105897220A - Bilateral digital filter circuit for logic port - Google Patents
Bilateral digital filter circuit for logic port Download PDFInfo
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- CN105897220A CN105897220A CN201610195226.0A CN201610195226A CN105897220A CN 105897220 A CN105897220 A CN 105897220A CN 201610195226 A CN201610195226 A CN 201610195226A CN 105897220 A CN105897220 A CN 105897220A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0201—Wave digital filters
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Abstract
The invention discloses a bilateral digital filter circuit for a logic port. The bilateral digital filter circuit comprises a counter circuit connected with an input signal IN. The output end of the counter circuit is connected with an S-R latch circuit. The output end of the S-R latch circuit is used as the output signal OUT of the bilateral digital filter circuit. The control end of the counter circuit is connected with a control circuit. A feedback circuit is connected between the output end of the counter circuit and the input end of the control circuit. The control circuit is connected with a clock signal CLK. The output signal OUT may acquire the input signal IN when the stabilization time of the logic-inverted input signal IN is longer than or equal to the intervals of N CLK falling edges. The output signal OUT is unchanged if the stabilization time cannot satisfy the above condition. Transit time can be controlled by adjusting the clock cycle of the CLK and the counting quantity of the counter circuit. The bilateral digital filter circuit achieves accurately and flexibly adjustable filter time and small physical area of a digital circuit.
Description
Technical field
The present invention relates to digital filtering technique field, particularly relate to a kind of bilateral digital filter circuit.
Background technology
In the chip of band logic control port, particularly have in the chip by key control end, logic input terminal
Usually there will be the burr pulse that various less desirable pulse width is wider at Kou, thus cause chip internal
Logic is judged by accident, is now accomplished by logic input terminal mouth increasing filter structure to eliminate what burr pulse brought
Erroneous judgement risk；And require that the chip area of designer's minimum realizes filtering time under a lot of applied environment
Accurate control, in some applied environments, even require that filtering time reaches tens milliseconds.
Existing disclosed technology implementation scheme is shown in Figure 1, typically can use in input signal IN and output
R, C series connection low-pass filter structure is concatenated real between two-level logic phase inverter INV1, INV2 of signal OUT
Filtering of existing burr pulse；After input logic level IN overturns, by resistance R after the output switching activity of INV1
Electric capacity C is carried out discharge and recharge, if long enough stabilization time of input logic level IN, in input signal IN
Again during upset, electric capacity C reaches the turnover door limit value of INV2 by the voltage after discharge and recharge and allows INV2 overturn,
Then input signal IN can normal delivery to OUT；If the stabilization time of input logic level IN falls short of, defeated
Enter when signal IN overturns again the voltage after electric capacity C discharge and recharge and be not up to the turnover door limit value of INV2, now
INV2 does not overturns, then input signal IN can not normal delivery to OUT, it is achieved that filtering.
But, there is techniques below defect in this technology implementation scheme: the filtering time of this technology implementation scheme is only
One is determined by the size of resistance R and the absolute value of electric capacity C, first at the on-chip capacitance of chip and resistance
It is very big that absolute value does inaccurate, deviation, and extent and direction completely random occur not by designer partially
Control, thus allow and accurately control filtering time and become a difficult problem；If secondly wanting to realize the long period
Filtering is accomplished by the resistance R of very high values and the electric capacity C of very high values, and the value of resistance R, electric capacity C becomes with area
Direct ratio, big area can greatly increase the production finished product of chip.
Summary of the invention
The technical problem to be solved is to provide one can accurately control filtering time and chip area
The little bilateral digital filter circuit for logic port.
For solving above-mentioned technical problem, the technical scheme is that a kind of bilateral number for logic port
Word filter circuit, including the counter circuit being connected with input signal IN, the outfan of described counter circuit
Connect and have S-R latch circuit, defeated as digital filter circuit of the outfan of described S-R latch circuit
Going out signal OUT, the control end of described counter circuit connects control circuit, the output of described counter circuit
Being connected between end and the input of described control circuit and have feedback circuit, described control circuit connects has clock to believe
Number CLK.
As the preferred technical scheme of one, described counter circuit include parallel connection rising edge counter and under
Fall is along enumerator.
As the preferred technical scheme of one, described rising edge counter includes the d type flip flop of N number of series connection,
Described N is the positive integer more than or equal to two, the reverse output of each d type flip flop of N number of described d type flip flop
End is all connected with the signal input part D of this d type flip flop, and the inverse output terminal of previous described d type flip flop
Connecting the CLK input mouth of d type flip flop described in later, the Reset end of N number of described d type flip flop is all and institute
Stating input signal IN to connect, the CLK end of first described d type flip flop connects with the outfan of described control circuit
Connecing, the outfan of d type flip flop described in n-th is connected with the feedback input end of described control circuit.
As the preferred technical scheme of one, described trailing edge enumerator include N number of series connection d type flip flop and
One phase inverter, described N is equal with the N in described rising edge counter, the input of described phase inverter with
Input signal IN connects, the inverse output terminal of each d type flip flop of N number of described d type flip flop and this D
The signal input part D of trigger is connected, and the inverse output terminal of previous d type flip flop connects later D and touches
Sending out the CLK input mouth of device, the outfan of described phase inverter connects with the Reset end of N number of described d type flip flop
Connecing, the CLK end of first described d type flip flop is connected with the outfan of described control circuit, D described in n-th
The outfan of trigger is connected with the feedback input end of described control circuit.
As the preferred technical scheme of one, described control circuit includes NAND gate circuit and lower NAND gate electricity
Road, described upper NAND gate circuit and described lower NAND gate circuit are all connected with described clock signal clk, described
The input of upper NAND gate circuit is connected with the outfan of d type flip flop described in described rising edge counter n-th,
The outfan of described upper NAND gate circuit and the CLK end of described first described d type flip flop of rising edge counter
Connect, the input of described lower NAND gate circuit and d type flip flop described in described trailing edge enumerator n-th
Outfan connects, and the outfan of described lower NAND gate circuit touches with first described D of described trailing edge enumerator
The CLK end sending out device connects.
As the preferred technical scheme of one, described S-R latch circuit includes first that circuit composition is identical
NAND gate circuit and the second NAND gate circuit, an input of described first NAND gate circuit with described on
Rise the outfan along enumerator to connect, an input of described second NAND gate circuit and described trailing edge meter
The outfan of number device connects, and the outfan of described first NAND gate circuit is another with described second NAND gate circuit
One input connects, another of the outfan of described second NAND gate circuit and described first NAND gate circuit
Individual input connects, and the outfan of described second NAND gate circuit connects phase inverter, described phase inverter defeated
Go out end to be connected with described output signal OUT.
Owing to have employed technique scheme, a kind of bilateral digital filter circuit for logic port, including
The counter circuit being connected with input signal IN, the outfan of described counter circuit connects S-R latch
Circuit, the outfan of described S-R latch circuit is as output signal OUT of digital filter circuit, described meter
The control end of number device circuit connects control circuit, the outfan of described counter circuit and described control circuit
Input between connect and have a feedback circuit, described control circuit connects clock signal clk；Control circuit
Major function is that control counter circuit starts counting up and stops counting；The function of counter circuit is input letter
By counter O reset during number IN upset, after upset, wait that clock signal clk is through N (N at steady state
Positive integer for more than or equal to two) transmit the input signal IN S-R latch to rear class after individual trailing edge；
Output is maintained the original state constant for counting waiting time at counter circuit by the function of S-R latch circuit, when
Counter circuit has counted rear real-time Transmission input signal to output signal OUT terminal；If input signal IN is turned over
The time less than N number of trailing edge of the clock signal clk time of steady statue, then output signal is kept after Zhuaning
OUT remains unchanged, i.e. input can not be transferred to output, it is achieved that the function of filtering, filtering time is enumerator
The time of N number of trailing edge detected, and this filtering time can be by adjusting clock cycle sum counter
Number regulates flexibly；Present invention achieves the thing that filtering time is the most adjustable and digital circuit is little
Reason area.
Accompanying drawing explanation
Fig. 1 is existing public technology embodiment；
Fig. 2 is total topological structure of the present invention；
Fig. 3 is the physical circuit embodiment of the present invention；
Fig. 4 is the physical circuit embodiment of the present invention when taking N=3；
Fig. 5 is the physical circuit embodiment of the present invention when taking N=5；
Fig. 6 is the embodiment of the present invention physical circuit work when input signal can pass through wave filter when being to take N=3
Make oscillogram；
Fig. 7 is the embodiment of the present invention concrete electricity when input signal can not pass through wave filter when being to take N=3
Road working waveform figure；
In figure: 301-control circuit；302-counter circuit；303-S-R latch circuit.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the present invention is expanded on further.In the following detailed description, the most logical
The mode crossing explanation describes some one exemplary embodiment of the present invention.Undoubtedly, the common skill of this area
Art personnel will be consequently realised that, in the case of without departing from the spirit and scope of the present invention, can use various difference
Mode described embodiment is modified.Therefore, accompanying drawing and description are the most illustrative,
Rather than be used for limiting scope of the claims.
As in figure 2 it is shown, a kind of bilateral digital filter circuit for logic port, including with input signal IN
The counter circuit 302 connected, the outfan of described counter circuit 302 connects S-R latch circuit
303, the outfan of described S-R latch circuit 303 is as output signal OUT of digital filter circuit, institute
The control end connection stating counter circuit 302 has control circuit 301, the outfan of described counter circuit 302
And being connected between the input of described control circuit 301 and have feedback circuit, described control circuit 301 connects to be had
Clock signal clk.
As it is shown on figure 3, described counter circuit 302 includes rising edge counter and the trailing edge counting of parallel connection
Device.Described rising edge counter includes that the d type flip flop of N number of series connection, described N more than or equal to two are just
Integer, the inverse output terminal of each d type flip flop of N number of described d type flip flop and the signal of this d type flip flop
Input D is connected, and the CLK of the inverse output terminal connection later d type flip flop of previous d type flip flop is defeated
Inbound port, the Reset end of N number of described d type flip flop is all connected with described input signal IN, described in first
The CLK end of d type flip flop is connected with the outfan of described control circuit 301, d type flip flop described in n-th defeated
Go out end to be connected with the feedback input end of described control circuit 301.Described trailing edge enumerator includes N number of series connection
D type flip flop and a phase inverter, described N is equal with the N in rising edge counter, described phase inverter
Input is connected with input signal IN, the inverse output terminal of each d type flip flop of N number of described d type flip flop
All it is connected with the signal input part D of this d type flip flop, and after the inverse output terminal connection of previous d type flip flop
The Reset of the CLK input mouth of one d type flip flop, the outfan of described phase inverter and N number of described d type flip flop
End connects, and the CLK end of first described d type flip flop is connected with the outfan of described control circuit 301, N
The outfan of individual described d type flip flop is connected with the feedback input end of described control circuit 301.Described control electricity
Road 301 includes NAND gate circuit and lower NAND gate circuit, described upper NAND gate circuit and described lower NAND gate
Circuit is all connected with described clock signal clk, the input of described upper NAND gate circuit and described rising edge
The outfan of d type flip flop described in enumerator n-th connects, and the outfan of described upper NAND gate circuit is with described
The CLK end of first described d type flip flop of rising edge counter connects, the input of described lower NAND gate circuit
It is connected with the outfan of d type flip flop described in described trailing edge enumerator n-th, described lower NAND gate circuit
Outfan is connected with the CLK end of described first described d type flip flop of trailing edge enumerator.Described S-R latches
Device circuit 303 includes that circuit forms the first identical NAND gate circuit and the second NAND gate circuit, described first
One input of NAND gate circuit is connected with the outfan of described rising edge counter, described second NAND gate
One input of circuit is connected with the outfan of described trailing edge enumerator, described first NAND gate circuit
Outfan is connected with another input of described second NAND gate circuit, described second NAND gate circuit defeated
Go out end to be connected with another input of described first NAND gate circuit, the output of described second NAND gate circuit
End connection has phase inverter, the outfan of described phase inverter to be connected with described output signal OUT.
When the stabilization time after the logic of input signal IN overturns more than or equal to the interval of N number of CLK trailing edge time,
Output signal OUT can collect input signal IN, if the stabilization time after the logic upset of input signal IN is little
When the interval of N number of CLK trailing edge, the logic state before now output signal OUT maintains is constant, i.e.
Input signal IN can not normal transmission to output signal OUT.Can be by regulating the clock of CLK by the time
Number N of the d type flip flop in cycle sum counter circuit 302 controls.
As it is shown on figure 3, be the physical circuit embodiment of the present invention, in this embodiment, 301 for controlling electricity
The physical circuit embodiment on road, 302 is the physical circuit embodiment of counter circuit, and 303 lock for S-R
The physical circuit embodiment of latch circuit.
As shown in Figure 3, control circuit 301 is by the identical NAND gate circuit group of 301_1,30,1_2 two
Becoming, function is that the output of detection counter allows CLK to enter counter circuit at counting stage, is counting
CLK is stoped to enter counter circuit after one-tenth.Wherein 301_1 is the rising edge working controller of input logic,
Allow CLK to input rising edge counter, when upper when the output H_d of rising edge counter is logic high
Rising stops CLK to input rising edge counter when being logic low along the output H_d of enumerator；301_2 is defeated
Enter the trailing edge working controller of logic, allow when the output L_d of trailing edge enumerator is logic high
CLK inputs trailing edge enumerator, stops CLK defeated when the output L_d of trailing edge enumerator is logic low
Enter trailing edge enumerator.
As it is shown on figure 3, counter circuit 302 by 302_1,302_2 ..., 302_N-1,302_N,
302_N+1,302_N+2 ..., 302_2N-1,302_2N 2N identical Reset altogether is for patrolling
The d type flip flop and the reverser 302_2N+1 that collect the resetting of zero collectively constitute.Wherein 302_1,302_2 ...,
302_N-1,302_N amount to N number of d type flip flop and are combined as the rising edge filtering enumerator of input logic, at meter
The output H_d of number and reseting stage rising edge wave filter is logic high, rising edge filter after counting completes
The output H_d of ripple device is logic low, when input signal IN from logic low become logic high and
Stablize and start counting up when snoop logic high level, when input signal IN is become logic low electricity from logic high
Steadily be scheduled on logic low rising edge counter reset time or counting complete after immediately stop counting；
302_N+1,302_N+2 ..., 302_2N-1,302_2N N number of d type flip flop and reverser 302_2N+1 altogether
It is combined as the trailing edge filtering enumerator of input logic, in counting and the output of reseting stage trailing edge wave filter
L_d is logic high, and after having counted, the output L_d of trailing edge wave filter is logic low, when defeated
Enter signal IN and become from logic high that logic low is stable to be started counting up when logic low, work as input
Signal IN is become logic high from logic low and stable when logic high trailing edge counter resets
Or stop counting when having counted immediately.
As it is shown on figure 3, S-R latch circuit 303 is by two identical NAND gate of 303_1,303_2
Circuit and phase inverter 303_3 collectively constitute.303 are logic high and L_d is logic high at H_d
Time output signal OUT maintained the output in a upper moment constant, be that logic high and L_d are for patrolling at H_d
During volume low level, output signal OUT is logic low, is logic low and L_d is logic high at H_d
During level, output signal OUT is logic high.
As shown in Figure 6, for taking N=3 the embodiment of the present invention tool when input signal can pass through wave filter time
Body circuit working waveform figure.Logic low is become from logic high in t1 moment input signal IN, this
Time input signal IN rising edge counter is resetted and keeps resetting, release trailing edge enumerator simultaneously
Reset terminal makes clock signal clk input normally to count, and this moment H_d and L_d is logic high,
Then the state of output signal OUT maintenance previous moment is constant remains as high level；It it is the t1 moment in the t2 moment
In 3rd the clock falling edge moment of rear clock signal clk, now carve trailing edge rolling counters forward and complete and defeated
Go out L_d and become logic low from logic high, now H_d be logic high, L_d be logic low electricity
Flat, then output signal OUT is just for logic low, and now input signal IN is delivered to output signal OUT.
In like manner become logic high in t3 moment input signal IN from logic low, now input signal IN pair
Trailing edge enumerator carries out resetting and keep to reset, and the reset terminal simultaneously discharging rising edge counter makes clock believe
Number CLK input can normally count, and this moment H_d and L_d is logic high, then output signal OUT
The state of maintenance previous moment is constant remains as low level；Clock signal clk after the t4 moment is the t3 moment
The 3rd clock falling edge moment, now carve rising edge rolling counters forward complete and export H_d from logic high
Level becomes logic low, now H_d be logic low, L_d be logic high, then output signal
OUT is just for logic high, and now input signal IN is delivered to output signal OUT.If input signal IN is again
Secondary variation is then to repeat t1～t2 or one of two processes of t3～t4.Work as input signal as can be seen from Fig.
When being more than the time interval between three trailing edges of CLK the stabilization time of IN, input signal IN can be normal
It is transferred to output signal OUT.
As it is shown in fig. 7, for take embodiment of the present invention during N=3 input signal can not by wave filter time
Physical circuit working waveform figure.Logic low is become from logic high in t1 moment input signal IN,
Now rising edge counter is resetted and keeps resetting by input signal IN, release trailing edge enumerator simultaneously
Reset terminal make clock signal clk input can normally count, this moment H_d and L_d is logic high,
Then the state of output signal OUT maintenance previous moment is constant remains as high level；In t2 moment input signal IN
Being become logic high from logic low, now clock CLK is not the most to three trailing edges, input signal
IN is not transferred to output signal OUT, and now trailing edge enumerator is resetted and keeps by input signal IN
Resetting, the reset terminal simultaneously discharging rising edge counter makes clock signal clk input can normally count, now
Carving H_d and L_d is all logic high, then the state of output signal OUT maintenance previous moment is constant still
For high level；T3 moment duty is identical with the t1 moment；T4 moment duty is identical with the t2 moment；
It is less than between the time between tri-trailing edges of clock CLK when the stabilization time of input signal IN as seen from the figure
Every time, it is constant that output signal OUT is always maintained at former state, it is achieved that the function of filtering.
The ultimate principle of the present invention, principal character and advantages of the present invention have more than been shown and described.The industry
Skilled person will appreciate that, the present invention is not restricted to the described embodiments, in above-described embodiment and description
The principle that the present invention is simply described described, without departing from the spirit and scope of the present invention, the present invention
Also having various changes and modifications, these changes and improvements both fall within scope of the claimed invention.This
The claimed scope of invention is defined by appending claims and equivalent thereof.
Claims (6)
1. the bilateral digital filter circuit for logic port, it is characterised in that: include and input signal
The counter circuit that IN connects, the outfan of described counter circuit connects S-R latch circuit, described
The outfan of S-R latch circuit as output signal OUT of digital filter circuit, described counter circuit
Control end to connect and have a control circuit, the input of the outfan of described counter circuit and described control circuit it
Between connect and have a feedback circuit, described control circuit connects clock signal clk.
2. as claimed in claim 1 for the bilateral digital filter circuit of logic port, it is characterised in that:
Described counter circuit includes rising edge counter and the trailing edge enumerator of parallel connection.
3. as claimed in claim 2 for the bilateral digital filter circuit of logic port, it is characterised in that:
Described rising edge counter includes that the d type flip flop of N number of series connection, described N are the positive integer more than or equal to two, N
The inverse output terminal of each d type flip flop of individual described d type flip flop and the signal input part D of this d type flip flop
It is connected, and described in the inverse output terminal connection later of previous described d type flip flop, the CLK of d type flip flop is defeated
Inbound port, the Reset end of N number of described d type flip flop is all connected with described input signal IN, described in first
The CLK end of d type flip flop is connected with the outfan of described control circuit, the outfan of d type flip flop described in n-th
It is connected with the feedback input end of described control circuit.
4. as claimed in claim 3 for the bilateral digital filter circuit of logic port, it is characterised in that:
Described trailing edge enumerator includes d type flip flop and a phase inverter, described N and the described rising of N number of series connection
N along enumerator is equal, and the input of described phase inverter is connected with input signal IN, and N number of described D touches
The inverse output terminal of each d type flip flop sending out device is connected with the signal input part D of this d type flip flop, and
The inverse output terminal of previous d type flip flop connects the CLK input mouth of later d type flip flop, described anti-phase
The outfan of device is connected with the Reset end of N number of described d type flip flop, the CLK of first described d type flip flop
End is connected with the outfan of described control circuit, and the outfan of d type flip flop described in n-th controls electricity with described
The feedback input end on road connects.
5. as claimed in claim 4 for the bilateral digital filter circuit of logic port, it is characterised in that:
Described control circuit includes NAND gate circuit and lower NAND gate circuit, described upper NAND gate circuit and described under
NAND gate circuit is all connected with described clock signal clk, the input of described upper NAND gate circuit with described on
Rise along d type flip flop described in enumerator n-th outfan connect, the outfan of described upper NAND gate circuit with
The CLK end of described first described d type flip flop of rising edge counter connects, described lower NAND gate circuit defeated
Enter end to be connected with the outfan of d type flip flop described in described trailing edge enumerator n-th, described lower NAND gate electricity
The outfan on road is connected with the CLK end of described first described d type flip flop of trailing edge enumerator.
6. as claimed in claim 1 for the bilateral digital filter circuit of logic port, it is characterised in that:
Described S-R latch circuit includes that circuit forms the first identical NAND gate circuit and the second NAND gate circuit,
One input of described first NAND gate circuit is connected with the outfan of described rising edge counter, and described
One input of two NAND gate circuits is connected with the outfan of described trailing edge enumerator, and described first with non-
The outfan of gate circuit is connected with another input of described second NAND gate circuit, described second NAND gate
The outfan of circuit is connected with another input of described first NAND gate circuit, described second NAND gate electricity
The outfan on road connects has phase inverter, the outfan of described phase inverter to be connected with described output signal OUT.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610195226.0A CN105897220A (en) | 2016-03-31 | 2016-03-31 | Bilateral digital filter circuit for logic port |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610195226.0A CN105897220A (en) | 2016-03-31 | 2016-03-31 | Bilateral digital filter circuit for logic port |
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| CN111404517A (en) * | 2020-04-08 | 2020-07-10 | 北京集创北方科技股份有限公司 | Pulse cancellation circuit, voltage detection circuit, and detection method |
| CN113904655A (en) * | 2021-12-10 | 2022-01-07 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
| CN116827330A (en) * | 2022-12-12 | 2023-09-29 | 南京微盟电子有限公司 | Strong anti-interference communication port circuit |
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| CN111404517A (en) * | 2020-04-08 | 2020-07-10 | 北京集创北方科技股份有限公司 | Pulse cancellation circuit, voltage detection circuit, and detection method |
| CN111404517B (en) * | 2020-04-08 | 2023-11-10 | 北京集创北方科技股份有限公司 | Pulse cancellation circuit, voltage detection circuit, and detection method |
| CN113904655A (en) * | 2021-12-10 | 2022-01-07 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
| CN116827330A (en) * | 2022-12-12 | 2023-09-29 | 南京微盟电子有限公司 | Strong anti-interference communication port circuit |
| CN116827330B (en) * | 2022-12-12 | 2024-03-12 | 南京微盟电子有限公司 | Strong anti-interference communication port circuit |
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Application publication date: 20160824 |