CN108390666A - A kind of delay circuit - Google Patents
A kind of delay circuit Download PDFInfo
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- CN108390666A CN108390666A CN201810385499.0A CN201810385499A CN108390666A CN 108390666 A CN108390666 A CN 108390666A CN 201810385499 A CN201810385499 A CN 201810385499A CN 108390666 A CN108390666 A CN 108390666A
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Abstract
The invention discloses a kind of delay circuits, including：The delay units connected in sequence of N 1, N number of logical AND gate, M-N lines decoder and 1 logic sum gate；Input signal is input to the input terminal of the first delay unit and the first input end of the first logical AND gate in 1 delay unit of N, the output end of the i-th delay unit in 1 delay unit of N is connected to the input terminal of i+1 delay unit and the first input end of i+1 logical AND gate in N number of logical AND gate, and the output end of 1 delay units of N is connect with the first input end of N logical AND gates in N number of logical AND gate in 1 delay unit of N；The second input terminal of L logical AND gates is connect with the L output ends of M-N line decoders in N number of logical AND gate, the output end of N number of logical AND gate and the one-to-one connection successively of N number of input terminal of logic sum gate.Delay circuit using the present invention can be generated with different delayed time time and the high time delayed signal of delay precision.
Description
Technical Field
The invention relates to the technical field of digital circuit signal processing, in particular to a delay circuit.
Background
The delay circuit is used as a key circuit in signal processing and widely applied to occasions such as frequency conversion control, automatic measurement and control, phase control radar, electronic countermeasure and the like. In the process of simulating or testing a measurement and control system, a delay circuit is usually required to generate delay signals with different delay times.
The existing delay circuit is divided into a digital delay circuit and an analog delay circuit, wherein the digital delay circuit generally controls the delay time by controlling the modulus of a counter, and the analog delay circuit allows a signal to propagate along a conductor and controls the delay time by controlling the length of the conductor. However, since the counter in the digital delay circuit is limited by the counting frequency; the analog delay circuit is limited by the volume of the conductor, so that the delay time range and selection of the delay circuit are limited. Therefore, the existing delay circuit can not generate delay signals with different delay times and high delay precision through one delay circuit to meet the requirements of simulation or test in a measurement and control system.
Disclosure of Invention
Aiming at the problems, the delay circuit can generate delay signals with different delay times and high delay precision, and can effectively meet the requirements of simulation or test in a measurement and control system.
To solve the above technical problem, a delay circuit according to the present invention includes:
n-1 delay units connected in sequence, wherein each delay unit is provided with an input end and an output end, and each delay unit is provided with K delay times; n is 2MM is not less than 1 and is an integer; k is an integer;
n logic AND gates, each logic AND gate having a first input terminal, a second input terminal and an output terminal;
an M-N line decoder having M input terminals and N output terminals; the M input ends are used for inputting M-bit binary numbers;
1 logic or gate having N inputs and 1 output; wherein,
an input signal is input to an input end of a first delay unit in N-1 delay units and a first input end of a first logic AND gate, an output end of an ith delay unit in the N-1 delay units is connected to an input end of an i +1 th delay unit and a first input end of an i +1 th logic AND gate in the N logic AND gates, i is greater than or equal to 1 and less than or equal to N-2, i is an integer, and an output end of an N-1 th delay unit in the N-1 delay units is connected with a first input end of an Nth logic AND gate in the N logic AND gates;
the second input end of the L-th logical AND gate in the N logical AND gates is connected with the L-th output end of the M-N line decoder, the output ends of the N logical AND gates are sequentially connected with the N input ends of the logical OR gate in a one-to-one manner, L is larger than or equal to 1 and smaller than or equal to N, and L is an integer; and the output end of the logic OR gate is used for signal output.
Compared with the prior art, the delay circuit adopts N-1 delay units which are sequentially connected to generate delay time, has a large range of delay time, and can enable an input signal to generate N-1 delay signals; the input signal and the N-1 delay signals are sequentially input to the N logic AND gates one by one, the N logic AND gates are controlled by the M-N line decoder, and the input signal or any one of the N-1 delay signals is output through the logic OR gate, so that the delay signals with different delay times can be effectively generated through one delay circuit; moreover, the delay time in the N-1 delay signals is generated by the delay unit, so that the delay circuit has higher delay precision and more selection of the delay time; in addition, because the output of the delay signal can be realized by controlling the M input ends of the M-N line decoder to input different M-bit binary numbers, the flexibility and the convenience of the adjustment of the delay time of the delay signal are improved.
As an improvement of the above scheme, the delay unit includes:
the 1-pair K-path analog switch is provided with 1 input end, K output ends and J gating control ends, wherein the J gating control ends are used for inputting J-bit binary numbers to control gating of the switch in the 1-pair K-path analog switch, and K is 2JJ is not less than 1 and is an integer;
k delay sub-circuits; wherein,
the output end of the s-th delay sub-circuit outputs a delayed signal; s is more than or equal to 1 and less than or equal to K, and s is an integer.
As an improvement of the above, the delay sub-circuit includes:
k resistors and 1 capacitor;
the first end of the s-th resistor in the K resistors is connected with the s-th output end, the second ends of all the K resistors are connected with the first end of the capacitor, the second end of the capacitor is grounded, and the connection point of any resistor in the K resistors and the capacitor is the output end of the delay sub-circuit.
As an improvement of the above scheme, the delay unit further includes:
and the buffer is connected between the input end of the delay unit and the input ends of the 1 pair of K-path analog switches.
As a modification of the above, the K resistors have different resistance values.
As an improvement of the scheme, J strobe control terminals in the N delay units are used for inputting the same J-bit binary number.
Drawings
Fig. 1 is a schematic structural diagram of a delay circuit according to embodiment 1 of the present invention.
Fig. 2 is a schematic structural diagram of a delay circuit with M-2 and N-4 in embodiment 1 of the present invention.
Fig. 3 is a schematic structural diagram of a delay unit in embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a delay unit with J2 and K4 in embodiment 1 of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
The technical solution of the present invention will be clearly and completely described below with reference to the specific embodiments and the accompanying drawings.
Example 1
Fig. 1 is a schematic structural diagram of a delay circuit in embodiment 1 of the present invention.
The delay circuit includes: n-1 delay units 1 connected in sequence, wherein each delay unit 1 is provided with an input end and an output end, and each delay unit 1 can generate K types of delay time; n is 2MM is not less than 1, M is an integer, and K is an integer; n logic and gates 2, each logic and gate 2 having a first input Y, a second input X and an output W; an M-N line decoder 3 having M input terminals A1、A2、A3、…、AMAnd N output terminals P1、P2、P3、…、PN(ii) a The M input ends are used for inputting M-bit binary numbers; 1 logical OR gate 4 having N inputs B1、B2、B3、…、BNAnd 1 output terminal Q; wherein, an input signal f (t) is input to an input end of a first delay unit in the N-1 delay units and a first input end of a first logic AND gate in the N logic AND gates, an output end of an ith delay unit in the N-1 delay units is connected to an input end of an i +1 th delay unit and a first input end of an i +1 th logic AND gate in the N logic AND gates, i is more than or equal to 1 and less than or equal to N-2, and is an integer, and an output end of an N-1 th delay unit in the N-1 delay units is connected with a first input end of an Nth logic AND gate in the N logic AND gates; the second input end of the L-th logical AND gate in the N logical AND gates is connected with the L-th output end of the M-N line decoder 3, the output ends of the N logical AND gates are sequentially connected with the N input ends of the logical OR gate 4 in a one-to-one mode, L is more than or equal to 1 and less than or equal to N, L is an integer, and the logical AND gates are connected with the N input ends of the logical OR gate 4 in a one-The output Q of the OR gate 4 is connected to the output of the delay circuit, the output signal of which is f [ t- (L-1) taus]S is not less than 1 and not more than K, and s is an integer.
The input signal f (t) in the present invention is a pulse signal of a digital circuit.
Next, M is 2, N is 4, that is, M-N line decoder 3 is 2-4 line decoder 31, and the delay time generated by each delay cell is τ1The delay circuit in embodiment 1 will be described in detail.
As shown in fig. 2, the signal f (t) is simultaneously inputted to the input terminal of the first delay unit 11 and the first input terminal Y of the first logic and gate 211The output of the first delay unit 11 outputs a signal f (t- τ)1) The signal f (t-tau)1) Are simultaneously input to the input of the second delay cell 12 and to the first input Y of the second logical and gate 222(ii) a The output of the second delay unit 12 outputs a signal f (t-2 τ)1) The signal f (t-2 τ)1) Are simultaneously input to the third delay element input and to the first input Y of the third logical AND-gate 233(ii) a The output of the third delay unit 13 outputs a signal f (t-3 τ)1) The signal f (t-3 τ)1) A first input terminal Y to a fourth logical AND gate 244. On the other hand, a 2-bit binary code is passed through a first input terminal A of a 2-4-line decoder 311And a second input terminal A2The 2-bit binary code is converted by a 2-4-line decoder 31 and then passes through a first output terminal P1A second output terminal P2A third output terminal P3And a fourth output terminal P4Output the conversion result, the first output terminal P1A second output terminal P2A third output terminal P3And a fourth output terminal P4Second input terminals X of respective AND-gates 211Second input terminal X of second logic AND gate 222A second input terminal X of the third logic AND gate 233And a second input X of the fourth logical AND gate 244Connected to control a first logic AND gate 21, a second logic AND gate 22, a third logic AND gate 23 and a fourth logic AND gate 24So that the output W of the first logical AND gate 211Output W of the second and gate 222Output W of the third and-gate 233And the output W of the fourth logical AND gate 244Different delay signals are output to the or gate 41, and then the output Q of the or gate 41 realizes the output of the different delay signals.
In particular, when the second input terminal A of the 2-4 line decoder 312A first input terminal A1When the input 2-bit binary code is "00", the first output terminal P1, the second output terminal P2, the third output terminal P3 and the fourth output terminal P4 of the 2-4-line decoder 31 output "0001", and the first logic and gate 21 outputs the "0001" signal to the first input terminal B of the logic or gate 41The output of the other AND gate is '0', so that the signal f (t) is output through the output end Q of the logic OR gate 4; when the second input terminal A of the 2-4 line decoder 312A first input terminal A1When the input 2-bit binary code is "01", the outputs of the first output terminal P1, the second output terminal P2, the third output terminal P3 and the fourth output terminal P4 of the 2-4-line decoder 31 are "0010", and the first logic and gate 21 outputs a signal to the second input terminal B of the logic or gate 42Input signal f (t-tau)1) The output of the other AND gate is "0", so that the signal f (t- τ) is1) Output through the output end Q of the logic OR gate 4; similarly, when the 2-bit binary code is "11", the first output terminal P1, the second output terminal P2, the third output terminal P3 and the fourth output terminal P4 of the 2-4-line decoder 31 output "1000", and the first logic and gate 21 outputs a signal to the fourth input terminal B of the logic or gate 44Input signal f (t-3 τ)1) The output of the other AND gate is "0", so that the signal f (t-3 τ)1) Output via the output Q of the logic or gate 4. Therefore, when M is 2, N is 4, and the delay time generated by each delay unit is τ1The delay circuit can generate 3 kinds of delay signals.
It is understood that when N is 2MM is more than or equal to 1 and is an integer, and the delay time generated by each delay unit is tau1When the Lth output terminal P of the M-N line decoder 3LAt high level, M-N lineThe other output ends of the decoder 3 are all low level, and then are connected with the Lth output end P of the M-N line decoder 3LThe connected Lth logic AND gate is opened, and the output end Q of the logic OR gate 4 outputs f [ t- (L-1) tau1]L ═ 1, 2, …, N. The delay circuit can generate 2M-1 delayed signal.
In embodiment 1, as shown in fig. 3, the delay unit includes: connected to the input end IN of the delay unit and the 1-to-K analog switch U2Of the input terminal Y1Buffer U1The time delay units are used for isolation and driving, so that the time delay units are mutually independent; 1 pair of K-path analog switch U2Having 1 input terminal T, K output terminals and J control terminals, where K is 2JJ is not less than 1 and is an integer; buffer U1And 1 pair of K-path analog switches U2Is connected with the input end Y; j strobe control terminals E1、E2、E3、…、EJFor inputting J-bit binary code to control 1-pair K-way analog switch U2Simulating the gating of the switch; the output end of the s-th resistor in the K output ends is connected with the first end of the s-th resistor in the K resistors, the second ends of all the K resistors are connected with the first end of the capacitor C, the second end of the capacitor C is grounded, the connection point of any one of all the K resistors and the capacitor C is the output end OUT of the delay unit, and s is 1, 2, 3, …, K, and any one of the K resistors is connected with the capacitor C in series to form a low-pass delay sub-circuit.
Preferably, in order to generate different delay times for the low-pass delay subcircuit composed of K resistors and the capacitor C, the K resistors can be selected as resistors with different resistance values.
Next, the operation of the delay unit will be described by taking J2 and K4 as examples.
As shown in fig. 3 and 4, when J is 2 and K is 4, 1 pair of K analog switches U in the delay unit2Is a 1-to-4-way analog switch U21The 1-to-4-way analog switch U21Having 1 input terminal Y, 2 control terminals E1And E24 outputsTerminal D1、D2、D3And D4First output terminal D of the 4 output terminals1Is connected to a first resistor R1First terminal, second output terminal D2Is connected to a second resistor R2First terminal, third output terminal D3Is connected to a third resistor R3First terminal, fourth output terminal D4Is connected to a fourth resistor R4A first terminal of (1), a first resistor R1A second resistor R2A third resistor R3And a fourth resistor R4The second end of the capacitor C is connected with the first end of the capacitor C, and the second end of the capacitor C is grounded; wherein the first resistor R1A second resistor R2A third resistor R3And a fourth resistor R4The connection point of any one of the resistors and the capacitor C is the output end OUT of the delay unit. The input signal f (t) is input from the input end IN of the delay unit, and the second gating control end E of the 2 gating control ends2And a first strobe control terminal E1For inputting a 2-bit binary digital control signal. When the second strobe control terminal E2A first strobe control terminal E1When the input 2-bit binary number is '00', 1 pair of 4-way analog switches U21Y-D of (1)1The circuit simulation switch is turned on, and the signals f (t) pass through the buffer U in sequence11-to-4-path analog switch U21And a first low-pass delay sub-circuit (formed by a first resistor R)1In series with a capacitor C) to produce a delay time τ1＝t1+t2+αR1C, the output signal f (t-tau) of the first low-pass time-delay sub-circuit1) Wherein, t1Is a buffer U1Time delay of t2Is a 1-to-4-way analog switch U21Time delay of α R1C is the delay time of the first low-pass delay sub-circuit, α is the delay time coefficient used to represent the design value of the delay sub-circuit, when the second gating control end E2A first strobe control terminal E1When the input 2-bit binary number is '01', 1 pair of 4-way analog switches U21Y-D of (1)2The circuit simulation switch is turned on, and the signals f (t) pass through the buffer U in sequence11-to-4-path analog switch U21A second low-pass delay sub-circuit (composed of a second circuit)Resistance R2In series with a capacitor C) to produce a delay τ1＝t1+t2+αR2C, the output signal f (t-tau) of the second low-pass time-delay sub-circuit2) Wherein, t1Is the delay time of the buffer, t2Is a 1-to-4-way analog switch U21Time delay of α R2C is the delay time of the second low-pass delay sub-circuit; and so on, when the second gating control terminal E2A first strobe control terminal E1When the input 2-bit binary number is '11', 1 pair of 4-way analog switches U21Y-D of (1)4The circuit switch is turned on, and the signal f (t) passes through the buffer U in sequence11-to-4-path analog switch U21A fourth low-pass delay sub-circuit (composed of a fourth resistor R)4And capacitor C in series) to produce a delay τ1＝t1+t2+αR4C, wherein, t1Is the delay time of the buffer, t2Is a 1-to-4-way analog switch U21Time delay of α R4And C is the delay time of the fourth low-pass delay sub-circuit. Therefore, when J is 2 and K is 4, each delay unit can generate 4 kinds of delay time; the delay circuit of the present invention can generate 12 kinds of delay signals when M is 2, N is 4, J is 2, and K is 4.
Preferably, in order to generate the same delay time for each delay unit in the delay circuit of the present invention, J strobe control terminals of N delay units can input the same J-bit binary number.
Understandably, the 1-pair K-path analog switch U2Where K is 2JJ is more than or equal to 1, and J is an integer, when the S-th analog switch is controlled to be gated through J gating control terminals, 1 pair of K analog switches U2Y-D of (1)kThe circuit simulation switch is turned on, and the signals f (t) pass through the buffer U in sequence11 pair of K-path analog switch U2The output of the s low-pass delay sub-circuit generates a delay taus＝t1+t2+αRsC, s low-pass time-delay sub-circuit output signal f (t-tau)s) Wherein, t1Is a buffer U1Time delay of t2Is 1 pair of K-way modePseudo switch U2Time delay of α RsC is the delay time of the s-th low-pass delay sub-circuit, and s is 1, 2, …, K.
Therefore, in the delay circuit of the present invention, when different M-bit binary numbers and J-bit binary numbers are set by the program control circuit, 2 can be obtainedJ(2MAnd (2) the delayed signals with the dead delay time are (1), namely, when the input signal is f (t), K (N-1) different delay processing can be carried out on f (t), and K (N-1) signal outputs with different delay times are obtained. In addition, the delay circuit of the present invention can directly output the input signal f (t), and the total of the delay circuit is 2J(2M-1) +1 output signals. Taking J-4 and M-4 as an example, the delay circuit can generate 340 delay signal outputs with different delay times; the delay circuit has 341 different signal outputs in total, plus a non-delayed signal output.
Compared with the prior art, the delay circuit has the following beneficial effects:
(1) the delay time is generated by adopting N-1 delay units which are connected in sequence, the range of the delay time is large, and the input signals can generate N-1 delay signals; the input signal and the N-1 delay signals are sequentially input to the N logic AND gates one by one, the N logic AND gates are controlled by the M-N line decoder, and the input signal or any one of the N-1 delay signals is output through the logic OR gate, so that the delay signals with different delay times can be effectively generated through one delay circuit; moreover, the delay time in the N-1 delay signals is generated by the delay unit, so that the delay circuit has higher delay precision and more selection of the delay time; in addition, because the output of the delay signal can be realized by controlling the M input ends of the M-N line decoder to input different M-bit binary numbers, the flexibility and the convenience of the adjustment of the delay time of the delay signal are improved;
(2) the delay unit adopts a buffer, a 1-pair K-path analog switch and a low-pass delay sub-circuit to generate delay time so as to generate a delay signal, so that the accuracy of the delay time can be further improved;
(3) the front end of each delay unit is isolated and driven by a buffer, so that the delay units cascaded in the delay circuit work independently, and the delay time precision is prevented from being reduced due to the influence of the delay units.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, so that any simple modification, equivalent change and modification made to the above embodiment according to the technical spirit of the present invention will still fall within the scope of the technical solution of the present invention without departing from the content of the technical solution of the present invention.
Claims (6)
1. A delay circuit, comprising:
n-1 delay units connected in sequence, wherein each delay unit is provided with an input end and an output end, and each delay unit is provided with K delay times; n is 2MM is not less than 1 and is an integer; k is an integer;
n logic AND gates, each logic AND gate having a first input terminal, a second input terminal and an output terminal;
an M-N line decoder having M input terminals and N output terminals; the M input ends are used for inputting M-bit binary numbers;
1 logic or gate having N inputs and 1 output; wherein,
an input signal is input to an input end of a first delay unit in N-1 delay units and a first input end of a first logic AND gate in the N logic AND gates, an output end of an ith delay unit in the N-1 delay units is connected to an input end of an i +1 th delay unit and a first input end of an i +1 th logic AND gate in the N logic AND gates, i is greater than or equal to 1 and less than or equal to N-2, i is an integer, and an output end of an N-1 th delay unit in the N-1 delay units is connected with a first input end of an Nth logic AND gate in the N logic AND gates;
the second input end of the L-th logical AND gate in the N logical AND gates is connected with the L-th output end of the M-N line decoder, the output ends of the N logical AND gates are sequentially connected with the N input ends of the logical OR gate in a one-to-one manner, L is larger than or equal to 1 and smaller than or equal to N, and L is an integer; and the output end of the logic OR gate is used for signal output.
2. The delay circuit of claim 1, wherein the delay unit comprises:
the 1-pair K-path analog switch is provided with 1 input end, K output ends and J gating control ends, wherein the J gating control ends are used for inputting J-bit binary numbers to control gating of the switch in the 1-pair K-path analog switch, and K is 2JJ is not less than 1 and is an integer;
k delay sub-circuits; wherein,
the output end of the s-th delay sub-circuit outputs a delayed signal; s is more than or equal to 1 and less than or equal to K, and s is an integer.
3. The delay circuit of claim 2, wherein the delay sub-circuit comprises:
k resistors and 1 capacitor;
the first end of the s-th resistor in the K resistors is connected with the s-th output end, the second ends of all the K resistors are connected with the first end of the capacitor, the second end of the capacitor is grounded, and the connection point of any resistor in the K resistors and the capacitor is the output end of the delay sub-circuit.
4. The delay circuit of claim 2, wherein the delay cell further comprises:
and the buffer is connected between the input end of the delay unit and the input ends of the 1 pair of K-path analog switches.
5. The delay circuit of claim 2, wherein the K resistors have different resistance values.
6. The delay circuit of claim 2, wherein J strobe control terminals of the N delay cells are for inputting the same J-bit binary number.
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Cited By (4)
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| WO2020239027A1 (en) * | 2019-05-29 | 2020-12-03 | 深圳市紫光同创电子有限公司 | Fpga circuit, system, configuration method, and computer readable medium |
| CN113505553A (en) * | 2021-06-28 | 2021-10-15 | 海光信息技术股份有限公司 | Delay circuit, driving method thereof, integrated circuit and electronic equipment |
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