CN108390666A - A kind of delay circuit - Google Patents

Abstract

The invention discloses a kind of delay circuits, including：The delay units connected in sequence of N 1, N number of logical AND gate, M-N lines decoder and 1 logic sum gate；Input signal is input to the input terminal of the first delay unit and the first input end of the first logical AND gate in 1 delay unit of N, the output end of the i-th delay unit in 1 delay unit of N is connected to the input terminal of i+1 delay unit and the first input end of i+1 logical AND gate in N number of logical AND gate, and the output end of 1 delay units of N is connect with the first input end of N logical AND gates in N number of logical AND gate in 1 delay unit of N；The second input terminal of L logical AND gates is connect with the L output ends of M-N line decoders in N number of logical AND gate, the output end of N number of logical AND gate and the one-to-one connection successively of N number of input terminal of logic sum gate.Delay circuit using the present invention can be generated with different delayed time time and the high time delayed signal of delay precision.

Description

a delay circuit

technical field

The invention relates to the technical field of digital circuit signal processing, in particular to a delay circuit.

Background technique

As a key circuit in signal processing, delay circuits are widely used in frequency conversion control, automatic measurement and control, phase control radar, electronic countermeasures and other occasions. In the process of simulating or testing the measurement and control system, a delay circuit is usually required to generate delay signals with different delay times.

Existing delay circuits are divided into digital delay circuits and analog delay circuits. Among them, the digital delay circuit usually controls the delay time by controlling the modulus of the counter, and the analog delay circuit allows the signal to propagate along the conductor. to control the delay time. However, because the counter in the digital delay circuit is limited by the counting frequency; and the analog delay circuit is limited by the volume of the conductor, the delay time range and selection of the delay circuit are limited. Therefore, the existing delay circuit cannot generate delayed signals with different delay times and high delay accuracy through one delay circuit to meet the requirements of simulation or testing in the measurement and control system.

Contents of the invention

In view of the above problems, a delay circuit of the present invention can generate delay signals with different delay times and high delay accuracy, which can effectively meet the requirements of simulation or testing in the measurement and control system.

In order to solve the problems of the technologies described above, a delay circuit of the present invention includes:

N-1 sequentially connected delay units, each delay unit has an input end and an output end, and each delay unit has K kinds of delay time; N= ^2M , M≥1, and M is an integer; K is an integer;

N logical AND gates, each logical AND gate has a first input terminal, a second input terminal and an output terminal;

The M-N line decoder has M input terminals and N output terminals; the M input terminals are used to input M-bit binary numbers;

1 logical OR gate with N inputs and 1 output; where,

The input signal is input to the input end of the first delay unit in the N-1 delay units and the first input end of the first logic AND gate, and the output of the i-th delay unit in the N-1 delay units terminal is connected to the input end of the i+1th delay unit and the first input end of the i+1th logic AND gate in the N logical AND gates, 1≤i≤N-2, and i is an integer, the said The output terminal of the N-1 delay unit in the N-1 delay units is connected to the first input terminal of the N logic AND gate in the N logic AND gates;

The second input terminal of the L logic AND gate in the N logic AND gates is connected to the L output terminal of the M-N line decoder, and the output terminals of the N logic AND gates are connected to the logic OR The N input ends of the gate are sequentially connected one-to-one, 1≤L≤N, and L is an integer; the output end of the logic OR gate is used for signal output.

Compared with the prior art, the delay circuit of the present invention adopts N-1 sequentially connected delay units to generate the delay time, and the range of the delay time is large, so that the input signal can generate N-1 kinds of delay signals ; and the input signal and N-1 kinds of delayed signals are sequentially input to N logical AND gates one by one, combined with the control of the M-N line decoder on the N logical AND gates, the input signal is output through the logical OR gate or Any one of the N-1 kinds of delayed signals can effectively realize the delayed signals with different delay times through a delay circuit; and, because the delay time in the N-1 kinds of delayed signals is determined by the delay unit, so that the delay circuit has higher delay accuracy and more options for delay time; in addition, because the output of the delay signal can be input by controlling the M input terminals of the M-N line decoder to input different It is realized by M-bit binary numbers, which improves the flexibility and convenience of adjusting the delay time of the delay signal.

As an improvement of the above solution, the delay unit includes:

1 pair of K-channel analog switches, having 1 input terminal, K output terminals and J strobe control terminals, the J strobe control terminals are used to input J-bit binary numbers to control the 1 pair of K-channel analog switches The gating of the middle switch, K=2 ^J , J≥1, and J is an integer;

K delay sub-circuits; where,

The sth output terminal among the K output terminals is connected to the sth delay subcircuit in the K delay subcircuits, and the output terminal of the sth delay subcircuit outputs a delayed signal; 1 ≤s≤K, and s is an integer.

As an improvement of the above scheme, the delay subcircuit includes:

K resistors and 1 capacitor;

The first terminal of the sth resistor among the K resistors is connected to the sth output terminal, the second terminals of all the K resistors are connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded , the connection point between any one of the K resistors and the capacitor is the output end of the delay sub-circuit.

As an improvement of the above solution, the delay unit also includes:

A buffer connected between the input end of the delay unit and the input end of the 1 pair of K-way analog switches.

As an improvement of the above solution, the K resistors have different resistance values.

As an improvement of the above solution, the J gate control terminals in the N delay units are used to input the same J-bit binary code.

Description of drawings

FIG. 1 is a schematic structural diagram of a delay circuit according to Embodiment 1 of the present invention.

FIG. 2 is a schematic structural diagram of a delay circuit when M=2 and N=4 in Embodiment 1 of the present invention.

FIG. 3 is a schematic structural diagram of a delay unit in Embodiment 1 of the present invention.

FIG. 4 is a schematic structural diagram of a delay unit when J=2 and K=4 in Embodiment 1 of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from this description, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

The technical solution of the present invention will be clearly and completely described below in combination with specific embodiments and accompanying drawings.

Example 1

As shown in FIG. 1 , it is a schematic structural diagram of a delay circuit in Embodiment 1 of the present invention.

The delay circuit comprises: N-1 delay units 1 connected in sequence, each delay unit 1 has an input end and an output end, and each delay unit 1 can produce K kinds of delay time; N= ^2M , M≥1, and M is an integer, K is an integer; N logical AND gates 2, each logical AND gate 2 has a first input terminal Y, a second input terminal X and an output terminal W; M-N line decoding The device 3 has M input terminals A ₁ , A ₂ , A ₃ , ..., A _M and N output terminals P ₁ , P ₂ , P ₃ , ..., P _N ; the M input terminals are used to input M bits Binary digital; 1 logical OR gate 4, with N input terminals B ₁ , B ₂ , B ₃ ,..., B _N and 1 output terminal Q; wherein, the input signal f(t) is input to N-1 delayed The input end of the first delay unit in the time unit and the first input end of the first logic AND gate in the N logic AND gates, the output end of the i delay unit in the N-1 delay units is connected to the i The input end of the +1 delay unit and the first input end of the i+1th logic AND gate in the N logic AND gates, 1≤i≤N-2, and i is an integer, and the first input end of the N-1 delay units The output end of the N-1 delay unit is connected to the first input end of the Nth logic AND gate in the N logic AND gates; the second input end of the L logic AND gate in the N logic AND gates is connected to the M-N The Lth output terminal of the line decoder 3 is connected, and the output terminals of the N logical AND gates are sequentially connected one-to-one with the N input terminals of the logical OR gate 4, 1≤L≤N, and L is an integer, the logical OR gate The output terminal Q of 4 is connected to the output terminal of the delay circuit, the output signal of the output terminal of the delay circuit is f[t-(L-1)τ _s ], 1≤s≤K, and s is an integer.

The input signal f(t) in the present invention is the pulse signal of the digital circuit.

Next, with M=2, N=4, that is, the M-N line decoder 3 is a 2-4 line decoder 31, and the delay time generated by each delay unit is τ ₁ , for example 1 The delay circuit is described in detail.

As shown in Figure 2, the signal f(t) is input to the input terminal of the first delay unit 11 and the first input terminal Y ₁ of the first logic AND gate 21 at the same time, and the output terminal of the first delay unit 11 outputs the signal f (t-τ ₁ ), the signal f(t-τ ₁ ) is input to the input terminal of the second delay unit 12 and the first input terminal Y ₂ of the second logic AND gate 22 at the same time; the second delay unit 12 The output terminal outputs signal f(t-2τ ₁ ), and the signal f(t-2τ ₁ ) is simultaneously input to the input terminal of the third delay unit and the first input terminal Y ₃ of the third logic AND gate 23; the third delay The output of unit 13 outputs a signal f(t−3τ ₁ ), which is fed to a first input Y _{4 of} a fourth logical AND gate 24 . On the other hand, the 2-bit binary code is input through the first input terminal _A1 and the second input terminal _A2 of the 2-4 line decoder 31, and the 2-bit binary code is converted by the 2-4 line decoder 31 and passed through The first output terminal P ₁ , the second output terminal P ₂ , the third output terminal P ₃ and the fourth output terminal P ₄ output conversion results, the first output terminal P ₁ , the second output terminal P ₂ , and the third output terminal P ₃ and the fourth output terminal P ₄ are respectively connected with the second input terminal X ₁ of the first logic AND gate 21, the second input terminal X ₂ of the second logic AND gate 22, and the second input terminal X of the third logic AND gate 23. ₃ and the second input terminal _X4 of the fourth logic AND gate 24 are connected, and then the first logic AND gate 21, the second logic AND gate 22, the third logic AND gate 23 and the fourth logic AND gate 24 are controlled, so that The output terminal W ₁ of the first logic AND gate 21, the output terminal W ₂ of the second logic AND gate 22, the output terminal W 3 of the third logic AND gate 23, and the output terminal W ₄ of the fourth logic AND gate ₂₄ direct to the logic OR The gate 41 outputs different delay signals, and then the output terminal Q of the logical OR gate 41 realizes the output of different delay signals.

Specifically, when the 2-bit binary code input to the second input terminal A ₂ and the first input terminal A ₁ of the 2-4 line decoder 31 is "00", the first output of the 2-4 line decoder 31 The output of terminal P1, second output terminal P2, third output terminal P3, and fourth output terminal P4 is "0001", and the first logic AND gate 21 inputs signal f(t) to the first input terminal _B1 of logic OR gate 4 , the output of the other AND gate is "0", so that the signal f(t) is output through the output terminal Q of the logical OR gate 4; when the second input terminal A ₂ and the first input terminal A of the 2-4 line decoder 31 _1. When the 2-bit binary code input is "01", the output of the first output terminal P1, the second output terminal P2, the third output terminal P3 and the fourth output terminal P4 of the 2-4 line decoder 31 is "0010" , the first logical AND gate 21 inputs the signal f(t-τ ₁ ) to the second input terminal B ₂ of the logical OR gate 4, and the output of the other AND gates is "0", so that the signal f(t-τ ₁ ) is logically The output terminal Q of the OR gate 4 is output; by analogy, when the 2-bit binary number is "11", the first output terminal P1, the second output terminal P2, and the third output terminal P3 of the 2-4 line decoder 31 , the output of the fourth output terminal P4 is "1000", the first logical AND gate 21 inputs the signal f(t-3τ ₁ ) to the fourth input terminal _B4 of the logical OR gate 4, and the output of other AND gates is "0", The signal f(t-3τ ₁ ) is output through the output terminal Q of the logical OR gate 4 . Therefore, when M=2, N=4, and the delay time generated by each delay unit is _τ1 , the delay circuit can generate three kinds of delay signals.

It can be understood that when N= ^2M , M≥1, and M is an integer, and the delay time generated by each delay unit is _τ1 , when the Lth output terminal of the M-N line decoder 3 When _PL is high level, the other output terminals of the M-N line decoder 3 are all low level, then the L logic AND gate connected to the L output terminal _PL of the M-N line decoder 3 is opened, The output Q of the logic OR gate 4 is f[t-(L-1)τ ₁ ], L=1, 2, . . . , N. The delay circuit can generate 2 ^M -1 delay signals.

In Embodiment 1, as shown in Figure 3, the delay unit includes: a buffer U1 connected between the input terminal IN of the delay unit and _the input terminal Y of a pair of K-way analog switches _U2 , the buffer U ₁ is used for isolation and driving, so that each delay unit is independent of each other; a pair of K analog switches U ₂ has 1 input terminal T, K output terminals and J control terminals, where K=2 ^J , J ≥1, and J is an integer; the output terminal of the buffer U ₁ is connected to the input terminal Y of a pair of K analog switches U ₂ ; J gate control terminals E ₁ , E ₂ , E ₃ ,..., E _J are used Inputting J-bit binary numbers to control the strobe of the analog switch in 1 pair of K analog switches _U2 ; wherein, the sth output terminal in the K output terminals is connected to the first end of the sth resistance in the K resistances, The second ends of all the K resistors are connected to the first end of the capacitor C, and the second end of the capacitor C is grounded, and the connection point between any one of the K resistors and the capacitor C is the output terminal OUT of the delay unit, s =1, 2, 3, ..., K, any one of the K resistors is connected in series with the capacitor C to form a low-pass delay sub-circuit.

Preferably, in order to make the low-pass delay sub-circuit composed of K resistors and capacitors C generate different delay times, the K resistors can be selected from resistors with different resistance values.

Next, taking J=2 and K=4 as examples, the working process of the delay unit will be described.

As shown in Figure 3 and Figure 4, when J=2 and K=4, the 1 pair of K-way analog switches U ₂ in the delay unit is 1 pair of 4-way analog switches U ₂₁ , and the 1 pair of 4-way analog switches U 21 U ₂₁ has 1 input terminal Y, 2 control terminals E ₁ and E ₂ , 4 output terminals D ₁ , D ₂ , D ₃ and D ₄ , the first output terminal D ₁ of the 4 output terminals is connected to the first The first terminal of a resistor _R1 , the second output terminal _D2 is connected to the first terminal of the second resistor _R2 , the third output terminal _D3 is connected to the first terminal of the third resistor _R3 , and the fourth output terminal D ₄ is connected to the first terminal of the fourth resistor _R4 , the second terminal of the first resistor _R1 , the second resistor _R2 , the third resistor _R3 and the fourth resistor _R4 is connected to the first terminal of the capacitor C, and the capacitor The second end of C is grounded; wherein, the connection point between any one of the first resistor R ₁ , the second resistor R ₂ , the third resistor R ₃ and the fourth resistor R ₄ and the capacitor C is the output terminal OUT of the delay unit . The input signal f(t) is input by the input terminal IN of the delay unit, and the second strobe control terminal _E2 and the first strobe control terminal _E1 of the two strobe control terminals are used to input 2-bit binary digital control signals . When the 2-bit binary code input by the second strobe control terminal E ₂ and the first strobe control terminal E ₁ is "00", the YD ₁ -way analog switch in the 1-to-4-way analog switch U ₂₁ is turned on, and the signal f(t) sequentially passes through the buffer U ₁ , the 1-to-4 analog switch U ₂₁ and the first low-pass delay sub-circuit (composed of the first resistor R ₁ and the capacitor C in series) to generate a delay time τ ₁ =t ₁ +t ₂ +αR ₁ C, the first low-pass delay sub-circuit output signal f(t-τ ₁ ), where t ₁ is the delay time of the buffer U ₁ , t ₂ is the 1-to-4 analog switch U ₂₁ delay time, αR ₁ C is the delay time of the first low-pass delay sub-circuit, and α is the delay time coefficient, which is used to represent the design value of the delay sub-circuit; when the second gate control terminal E ₂ 1. When the 2-bit binary number input by the first strobe control terminal E ₁ is "01", the YD _2- way analog switch in the 1-to-4-way analog switch U ₂₁ is turned on, and the signal f(t) passes through the buffer U in turn. _1. 1 pair of 4-way analog switch U ₂₁ , the second low-pass delay sub-circuit (composed of the second resistor R ₂ and capacitor C connected in series) generates a delay τ ₁ =t ₁ +t ₂ +αR ₂ C, the second The low-pass delay sub-circuit outputs the signal f(t-τ ₂ ), where t ₁ is the delay time of the buffer, t ₂ is the delay time of 1 pair of 4-way analog switch U ₂₁ , and αR ₂ C is the second The delay time of the low-pass delay sub-circuit; by analogy, when the 2-bit binary code input by the second strobe control terminal E ₂ and the first strobe control terminal E ₁ is "11", then 1 pair of 4-way The YD ₄ -way switch in the analog switch U ₂₁ is turned on, and the signal f(t) passes through the buffer U ₁ , 1 pair of 4-way analog switch U ₂₁ , the fourth low-pass delay sub-circuit (by the fourth resistor R ₄ and Capacitor C is connected in series to form) output, resulting in delay τ ₁ =t ₁ +t ₂ +αR ₄ C, wherein, t ₁ is the delay time of the buffer, t ₂ is the delay time of 1 pair of 4-way analog switch U ₂₁ , αR ₄ C is the delay time of the fourth low-pass delay sub-circuit. Therefore, when J=2, K=4, each delay unit can produce 4 kinds of delay times; Then when M=2, N=4, J=2, K=4, the delay circuit of the present invention Can generate 12 kinds of delayed signals.

Preferably, in order to make each delay unit in the delay circuit of the present invention generate the same delay time, the J gating control terminals in the N delay units can input the same J-bit binary code.

It can be understood that when K=2 ^J in a pair of K-way analog switches U ₂ , J≥1, and J is an integer, when the gate of the s-th analog switch is controlled by J gating control terminals, a pair of K The YD _k -way analog switch in the analog switch U ₂ is turned on, and the signal f(t) is sequentially output through the buffer U ₁ , a pair of K-way analog switches U ₂ , and the s-th low-pass delay sub-circuit to generate a delay τ _s ＝t ₁ +t ₂ +αR _s C, the output signal f(t-τ _s ) of the sth low-pass delay subcircuit, among them, t ₁ is the delay time of the buffer U ₁ , and t ₂ is 1 pair of K channels The delay time of the analog switch U ₂ , αR _s C is the delay time of the sth low-pass delay sub-circuit, s=1, 2, . . . , K.

Therefore, in the time-delay circuit of the present invention, when different M binary numbers and J-bit binary numbers are set by the program control circuit, just can obtain 2 ^J (2 ^M -1) kinds of time-delayed signals with unreasonable delay time, also That is, when the input signal is f(t), K(N-1) different delay processes can be performed on f(t), and K(N-1) signal outputs with different delay times can be obtained. In addition, the delay circuit of the present invention can also directly output the input signal f(t), and the delay circuit has a total of 2 ^J (2 ^M −1)+1 output signals. Taking J=4, M=4 as an example, the delay circuit can generate 340 kinds of delayed signal outputs with different delay times; plus the signal output without delay, the delay circuit has 341 different signal outputs in total.

Compared with the prior art, the delay circuit of the present invention has the following beneficial effects:

(1) N-1 sequentially connected delay units are used to generate the delay time. The range of the delay time is large, and the input signal can generate N-1 kinds of delay signals; and the input signal and N-1 kinds Delayed signals are input one-to-one to N logical AND gates one by one, combined with the control of N logical AND gates by the M-N line decoder, the input signal or any of the N-1 delayed signals are output through the logical OR gate One, can effectively realize the delay signal with different delay times by a delay circuit; and, because the delay time in the N-1 kinds of delay signals is produced by the delay unit, the delay circuit has a higher Delay accuracy and more choices of delay time; in addition, because the output of the delay signal can be realized by controlling the M input terminals of the M-N line decoder to input different M-bit binary numbers, the improvement of the The flexibility and convenience of delay time adjustment for delayed signals;

(2) The delay unit adopts a buffer, a pair of K-way analog switches and a low-pass delay sub-circuit to generate a delay time, and then generate a delay signal, which can further improve the accuracy of the delay time;

(3) The front end of each delay unit is isolated and driven by a buffer, so that the cascaded delay units in the delay circuit work independently, avoiding mutual influence and reducing the accuracy of the delay time.

The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Therefore, any content that does not depart from the technical solution of the present invention, any changes made to the above embodiments according to the technical essence of the present invention Simple modifications, equivalent changes and modifications all still fall within the scope of the technical solutions of the present invention.

Claims (6)

1. A delay circuit, characterized in that, comprising: N-1 sequentially connected delay units, each delay unit has an input end and an output end, and each delay unit has K kinds of delay time; N= ^2M , M≥1, and M is an integer; K is an integer; N logical AND gates, each logical AND gate has a first input terminal, a second input terminal and an output terminal; The M-N line decoder has M input terminals and N output terminals; the M input terminals are used to input M-bit binary numbers; 1 logical OR gate with N inputs and 1 output; where, The input signal is input to the input end of the first delay unit in the N-1 delay units and the first input end of the first logic AND gate in the N logic AND gates, and in the N-1 delay units The output end of the i delay unit is connected to the input end of the i+1 delay unit and the first input end of the i+1 logic AND gate among the N logic AND gates, 1≤i≤N-2 , and i is an integer, the output end of the N-1 delay unit in the N-1 delay units is connected to the first input end of the N logic AND gate in the N logic AND gates; The second input terminal of the L logic AND gate in the N logic AND gates is connected to the L output terminal of the M-N line decoder, and the output terminals of the N logic AND gates are connected to the logic OR The N input ends of the gate are sequentially connected one-to-one, 1≤L≤N, and L is an integer; the output end of the logic OR gate is used for signal output. 2. The delay circuit according to claim 1, wherein the delay unit comprises: 1 pair of K-channel analog switches, having 1 input terminal, K output terminals and J strobe control terminals, the J strobe control terminals are used to input J-bit binary numbers to control the 1 pair of K-channel analog switches The gating of the middle switch, K=2 ^J , J≥1, and J is an integer; K delay sub-circuits; where, The sth output terminal among the K output terminals is connected to the sth delay subcircuit in the K delay subcircuits, and the output terminal of the sth delay subcircuit outputs a delayed signal; 1 ≤s≤K, and s is an integer. 3. delay circuit as claimed in claim 2, is characterized in that, described delay sub-circuit comprises: K resistors and 1 capacitor; The first terminal of the sth resistor among the K resistors is connected to the sth output terminal, the second terminals of all the K resistors are connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded , the connection point between any one of the K resistors and the capacitor is the output end of the delay sub-circuit. 4. delay circuit as claimed in claim 2, is characterized in that, described delay unit also comprises: A buffer connected between the input end of the delay unit and the input end of the 1 pair of K-way analog switches. 5. The delay circuit according to claim 2, wherein the K resistors have different resistance values. 6. The delay circuit according to claim 2, wherein the J gate control terminals in the N delay units are used to input the same J-bit binary code.