CN112543019A - Low-level reset circuit resisting single-particle transient - Google Patents
Low-level reset circuit resisting single-particle transient Download PDFInfo
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- CN112543019A CN112543019A CN202011554124.6A CN202011554124A CN112543019A CN 112543019 A CN112543019 A CN 112543019A CN 202011554124 A CN202011554124 A CN 202011554124A CN 112543019 A CN112543019 A CN 112543019A
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- 230000001052 transient effect Effects 0.000 title claims abstract description 45
- 239000002245 particle Substances 0.000 title description 30
- 239000000872 buffer Substances 0.000 claims abstract description 107
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000002787 reinforcement Effects 0.000 description 5
- 230000003014 reinforcing effect Effects 0.000 description 5
- 238000001914 filtration Methods 0.000 description 3
- 238000010849 ion bombardment Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- LPLLVINFLBSFRP-UHFFFAOYSA-N 2-methylamino-1-phenylpropan-1-one Chemical compound CNC(C)C(=O)C1=CC=CC=C1 LPLLVINFLBSFRP-UHFFFAOYSA-N 0.000 description 1
- 240000003023 Cosmos bipinnatus Species 0.000 description 1
- 235000005956 Cosmos caudatus Nutrition 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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Abstract
The invention discloses a single-event transient resistant low-level reset circuit, which comprises more than two levels of buffer units, wherein the buffer units at all levels are sequentially connected in series, a final buffer unit at the tail end position in the buffer units at all levels is a reinforced buffer unit, the reinforced buffer unit comprises a NOR gate circuit and an inverter circuit which are sequentially connected, the NOR gate circuit comprises a first transistor, a second transistor, a delay unit and a first resistor which are mutually connected, the inverter circuit comprises a third transistor and a second resistor which are mutually connected, and when an input signal is in a high level, the first transistor, the second transistor and the third transistor are all in an open state.
Description
Technical Field
The invention relates to the technical field of CMOS (complementary metal oxide semiconductor) integrated circuits, in particular to a low-level reset circuit resisting single-event transient.
Background
In the cosmos space, there are a large number of energetic particles (protons, electrons, heavy ions, etc.). After being bombarded by the high-energy particles, the integrated circuit can generate single-particle transient pulses. For example, when the single-event transient pulse is transmitted to a reset port of the time sequence unit, the time sequence unit adopts an asynchronous reset mode, and the time sequence unit can be immediately reset only by meeting the minimum pulse width of a reset signal, so that the data value stored by the time sequence unit is changed. Because the reset signal is a global signal, if a single-event transient pulse is generated at the root node of the reset circuit, the whole integrated circuit is reset, thereby causing errors. Single event transients have now become a major source of soft errors. Therefore, it is necessary to perform single event transient resistance reinforcement for the reset circuit.
CMOS integrated circuit reset circuits are typically formed by CMOS buffers, which conventionally consist of a plurality of transistors, which must be turned off when the CMOS buffer is in operation, and which are sensitive to particle bombardment. When the high energy particles bombard the transistors in the off state in the CMOS buffer, a single event transient occurs, and thus the CMOS buffer is more sensitive to the single event transient. As shown in fig. 1, a conventional CMOS buffer at least includes 2 PMOS transistors and 2 NMOS transistors, and when the CMOS buffer is in operation, at least 1 PMOS transistor and 1 NMOS transistor are in an off state, and the 2 transistors in the off state are sensitive to heavy ion bombardment, which is a sensitive node. As shown in FIG. 2, the transistor P1 and the transistor N2 are sensitive nodes. The conventional reset circuit is shown in fig. 3, wherein buffers of different levels are connected in sequence to form a link, and a trigger is connected to an end buffer. For a low-level reset circuit, for example, when the low-level reset circuit is formed by a CMOS buffer as shown in fig. 1, the CMOS buffer is started to operate, when the input is at a high level, the transistor P1 and the transistor N2 are both in an off state, and when particles bombard the two transistors in any stage of buffer in the circuit, a single-particle transient is generated, which may affect the stability of the whole circuit. Therefore, it is desirable to provide a low-level reset circuit capable of resisting a Single-Event Transient (SET) so as to improve the Single-Event Transient resistance of the low-level reset circuit.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the low-level reset circuit which has the advantages of simple structure, low cost, single-event transient resistance, stability and reliability.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a low-level reset circuit resisting single-particle transient comprises more than two levels of buffer units, wherein the buffer units at each level are sequentially connected in series, a final buffer unit at the tail end position in the buffer units at each level is a reinforced buffer unit, the reinforced buffer unit comprises a NOR gate circuit and an inverter circuit which are sequentially connected, the NOR gate circuit comprises a first transistor N1, a second transistor N2, a delay unit and a first resistor R1 which are connected with each other, the inverter circuit comprises a third transistor P1 and a second resistor R2 which are connected with each other, and when an input signal is at a high level, the first transistor N1, the second transistor N2 and the third transistor P1 are all in an open state.
Further, in the nor gate circuit, the gate of the first transistor N1 and the input terminal of the delay unit are both connected to an input signal terminal, the sources of the first transistor N1 and the second transistor N2 are both grounded, the drains of the first transistor N1 and the second transistor N2 are both connected to the input terminal of the inverter circuit and a power supply through the first resistor R1, respectively, and the output terminal of the delay unit is connected to the gate of the second transistor N2.
In the inverter circuit, a gate of the third transistor P1 is connected to an output terminal of the nor gate, a drain of the third transistor P1 is connected to an output signal terminal and to ground via the second resistor, and a source of the third transistor P1 is connected to a power supply.
Further, the first transistor N1 and the second transistor N2 are both NMOS transistors, and the third transistor P1 is a PMOS transistor.
Further, the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
Furthermore, the number of nodes in each level of buffer unit is gradually increased, and each node corresponds to one buffer unit.
Further, the final stage buffer unit at the end position is connected with a flip-flop.
Compared with the prior art, the invention has the advantages that:
1. according to the invention, the reinforced buffer unit is formed by the NOR gate circuit and the inverter circuit, the resistor is used at the sensitive node position of the buffer, when the input signal is at a high level, each transistor in the circuit is in an open state, and the transistor in the closed state does not exist, so that the sensitive node sensitive to heavy ion bombardment can be eliminated, the sensitive node does not exist in the buffer unit, the buffer unit has the function of filtering the single-particle transient pulse, the single-particle transient cannot be generated, and the single-particle transient reinforcement resistance of the reset circuit can be realized.
2. After the functional circuit normally works, the particles bombard the reinforced buffer unit and cannot generate single-particle transient pulse, and the reset circuit outside the particle bombarded reinforced buffer unit can generate the single-particle transient pulse but can be filtered by the reinforced buffer unit positioned at the tail end of the reset circuit, so that the normal work of the functional circuit can be ensured.
3. According to the invention, only the reinforcing buffer unit is arranged at the tail end of the reset circuit, so that the tail end of the reset circuit chain has a single-event transient pulse function and can not generate single-event transient, and other links can retain the original circuit structure, therefore, the single-event transient-resistant reinforcement of the low-level reset circuit can be realized only by small simple modification, and the low-level reset circuit has good compatibility and is easy to be compatible with the design process of the traditional reset circuit.
Drawings
Fig. 1 is a circuit configuration diagram of a buffer unit in the prior art.
FIG. 2 is a diagram illustrating a sensitive node when a buffer unit outputs a high level in the prior art.
Fig. 3 is a schematic circuit diagram of a reset circuit in the prior art.
Fig. 4 is a schematic circuit diagram of a reinforced buffer unit in the single-event-transient-resistant low-level reset circuit of the present embodiment.
Fig. 5 is a schematic circuit structure diagram of the low-level reset circuit for resisting the single-event transient according to the embodiment.
Fig. 6 is a diagram of simulated waveforms for particle bombardment when tested using a conventional low-level reset circuit.
FIG. 7 is a waveform diagram of a low level reset circuit for single event transient resistance according to the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 4 and 5, the single-event-transient-resistant low-level reset circuit of this embodiment includes more than two stages of buffer units, the buffer units of each stage are sequentially connected in series, a last buffer unit at an end position of each buffer unit is a reinforced buffer unit, the reinforced buffer unit includes a nor gate circuit and an inverter circuit, the nor gate circuit includes a first transistor N1, a second transistor N2, a DELAY unit (DELAY) and a first resistor R1, the nor gate circuit includes a third transistor P1 and a second resistor R2, the first transistor N1, the second transistor N2 and the third transistor P1 are all in an open state when an input signal is at a high level.
In the present embodiment, a sensitive node in a buffer of the low level reset circuit is determined, as shown in fig. 2, when the low level reset circuit is formed by the CMOS buffer shown in fig. 1, the CMOS buffer is enabled to operate, when the input is high level, the transistor P1 and the transistor N2 are in an off state, and the transistor P1 and the transistor N2 are sensitive nodes. In this embodiment, after determining the sensitive node in the low-level reset circuit buffer, a resistor is used at the sensitive node, a reinforced buffer unit is formed by a nor gate circuit and an inverter circuit, when the input signal is at a high level, each transistor in the circuit is in an open state, and there is no transistor in a closed state, so that the sensitive node sensitive to heavy ion bombardment can be eliminated, that is, there is no sensitive node in the reinforced buffer unit, and the reinforced buffer unit has a function of filtering a single-particle transient pulse and cannot generate a single-particle transient, so that the reinforcement against the single-particle transient of the reset circuit can be realized, after the functional circuit normally works, particles bombard the reinforced buffer unit, and cannot generate the single-particle transient, and the reset circuits outside the reinforced buffer unit, which generate the single-particle transient, can be filtered by the reinforced buffer unit located at the tail end of the reset circuit, thereby ensuring the normal operation of the functional circuit.
The reset circuit is provided with the reinforcing buffer unit only at the tail end of the reset circuit, so that the tail end of a reset circuit chain has the function of filtering single-particle transient pulses and cannot generate single-particle transients, and other links can retain the original circuit structure, so that the single-particle transient-resistant reinforcement of the reset circuit can be realized only by small simple transformation, and the reset circuit is good in compatibility and easy to be compatible with the design flow of the traditional reset circuit.
As shown in fig. 4, in the nor gate circuit of the present embodiment, the gate of the first transistor N1 and the input terminal of the delay unit are both connected to the input signal terminal, the sources of the first transistor N1 and the second transistor N2 are both grounded, the drains of the first transistor N1 and the second transistor N2 are both connected to the input terminal of the inverter circuit and the power supply through the first resistor R1, respectively, and the output terminal of the delay unit is connected to the gate of the second transistor N2; in the inverter circuit, the gate of the third transistor P1 is connected to the output terminal of the nor gate, the drain of the third transistor P1 is connected to the output signal terminal and to the ground via the second resistor, and the source of the third transistor P1 is connected to the power supply. The first transistor N1 and the second transistor N2 are both NMOS transistors, and the third transistor P1 is a PMOS transistor.
In this embodiment, the first resistor R1 and the second resistor R2 are specifically polysilicon resistors. The polysilicon resistor has good stability and high precision, can further improve the single-particle transient resistance of the buffer by using the polysilicon resistor at the sensitive node of the buffer unit, and is more suitable for engineering application.
Referring to fig. 4, the reinforced buffer unit in this embodiment has an input a, an output Y, a power supply VDD, and a ground GND, wherein the nor circuit is composed of 2 NMOS transistors (N1 and N2), 1 DELAY unit (DELAY), and 1 polysilicon resistor (R1), and the inverter circuit is composed of 1 polysilicon resistor (R2) and 1 PMOS transistor (P1). In the NOR gate circuit, the sources of the transistors N1 and N2 are both grounded GND, the drains are both connected with the output X0 of the NOR gate, the gate of the transistor N1 is connected with the input A of the NOR gate (which is also the input of the reinforced buffer unit), the gate of the transistor N1 is connected with the DELAY unit DELAY, and the output end of the DELAY unit DELAY is connected with the gate of the transistor N2; one end of the resistor R1 is connected with the output end X0 of the NOR gate circuit, and the other end is connected with the power supply VDD; in the inverter circuit, the gate of the transistor P1 is connected to the input terminal X1 of the inverter circuit (or the output terminal X0 of nor gate current at the same time), the drain of the transistor P1 is connected to the output terminal Y of the inverter circuit (or the output of the reinforcing buffer unit at the same time), the source of the transistor P1 is connected to the power supply VDD, one end of the resistor R2 is connected to the GND, and the other end is connected to the output terminal Y of the inverter circuit (or the output terminal of the reinforcing buffer unit at the same time). When the input of the reinforced buffer unit is in a high level state, the N1 transistor, the N2 transistor and the P1 transistor are all in an open state, and a single-event transient sensitive node does not exist, so that the single-event transient resistance can be realized.
In a specific application embodiment, a NOR gate circuit is formed by 2 NMOS transistors, 1 delay unit and 1 polysilicon resistor according to the connection mode, and an inverter circuit is formed by 1 polysilicon resistor and 1 PMOS transistor according to the connection mode; the reinforced buffer unit is formed by connecting a NOR gate circuit and an inverter circuit; and constructing a low-level reset circuit, wherein except for a final-stage buffer in the reset circuit, each stage of buffer can use a common buffer unit, the final-stage buffer is a buffer which is positioned at a terminal position stage and connected with a trigger, and the final-stage buffer uses the reinforced buffer unit, namely constructing the required low-level reset circuit capable of resisting the single-event transient, as shown in fig. 5.
In this embodiment, the number of nodes in each level of buffer unit of the reset circuit is gradually increased, and each node corresponds to one buffer unit. As shown in fig. 5, for the leftmost reset buffer unit link, the input of the level 1 buffer unit is 1 node, and the output is 2 nodes; the input of the 2 nd-level buffer unit is 2 nodes, and the output is 3 nodes; the input of the i-th stage buffer unit is an i-node, and the output is an i + 1-node, wherein the final stage (reset buffer unit connected with the trigger) adopts the reinforced buffer unit.
In order to verify the function of the reset circuit of the present invention, in the embodiment of the present invention, the reset circuit formed by the conventional buffer shown in fig. 1 and the low level reset circuit of the present invention are respectively particle bombarded, and the results are compared.
A prior art low level reset circuit as in fig. 3, where for the leftmost reset buffer link, the input of the level 1 buffer is 1 node and the output is 2 nodes; the input of the 2 nd-level buffer is 2 nodes, and the output is 3 nodes; the input of the ith stage buffer is an i node, and the output of the ith stage buffer is an i +1 node. In the low-level reset circuit in fig. 3, when i is 97, the leftmost reset buffer chain shares the 99-stage reset buffer, the input voltage waveform of the 1 st-stage reset buffer is denoted by v (1), the output voltage waveform of the 2 nd-stage reset buffer is denoted by v (2), the output voltage waveform of the 98 th-stage reset buffer is denoted by v (99), and the output voltage waveform of the 99 th-stage reset buffer is denoted by v (100). When the functional circuit works normally, the reset circuit inputs high level and outputs high level. The N2 transistor of the reset buffer of the 1 st stage of the reset circuit is bombarded by simulated particles of an exponential current source, and a SET pulse of 1ns is injected and continuously propagates. The SPICE simulation waveform obtained in the specific application embodiment is as shown in fig. 6, and the output voltage waveform of the 99 th-stage reset buffer has a single-event transient pulse, so that the trigger reset can be caused, and further, the functional circuit is caused to make an error.
In the low-level reset circuit of the present invention shown in fig. 5, when i is 97, the leftmost reset buffer chain shares the 99-stage reset buffer, the input voltage waveform of the 1 st-stage reset buffer is denoted by v (1), the output voltage waveform of the 2 nd-stage reset buffer is denoted by v (2), the output voltage waveform of the 98 th-stage reset buffer is denoted by v (99), and the output voltage waveform of the 99 th-stage reset buffer is denoted by v (100). When the functional circuit works normally, the reset circuit inputs high level and outputs high level. A SPICE simulation waveform obtained in a specific application embodiment is shown in FIG. 7, although the SET pulse can propagate in an existing buffer chain (a buffer from a 1 st stage to a 98 th stage), when the SET pulse passes through a 99 th stage reinforcing buffer, the SET pulse disappears, the trigger reset is not triggered, and a functional circuit can work normally. Namely, the low-level reset circuit for resisting the single-event transient is immune to the single-event transient.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (7)
1. The low-level reset circuit is characterized in that the final buffer unit at the tail end position in each level of buffer units is a reinforced buffer unit, the reinforced buffer unit comprises a NOR gate circuit and an inverter circuit which are sequentially connected, the NOR gate circuit comprises a first transistor N1, a second transistor N2, a delay unit and a first resistor R1 which are connected with each other, the inverter circuit comprises a third transistor P1 and a second resistor R2 which are connected with each other, and when an input signal is in a high level state, the first transistor N1, the second transistor N2 and the third transistor P1 are all in an open state.
2. The single event transient resistant low level reset circuit of claim 1, wherein: in the nor gate circuit, the gate of the first transistor N1 and the input end of the delay unit are both connected to an input signal end, the sources of the first transistor N1 and the second transistor N2 are both grounded, the drains of the first transistor N1 and the second transistor N2 are both connected to the input end of the inverter circuit and a power supply through the first resistor R1, respectively, and the output end of the delay unit is connected to the gate of the second transistor N2.
3. The single event transient resistant low level reset circuit of claim 1, wherein: in the inverter circuit, the gate of the third transistor P1 is connected to the output terminal of the nor gate, the drain of the third transistor P1 is connected to the output signal terminal and to ground via the second resistor, and the source of the third transistor P1 is connected to a power supply.
4. The single event transient resistant low level reset circuit of claim 1, wherein: the first transistor N1 and the second transistor N2 are both NMOS transistors, and the third transistor P1 is a PMOS transistor.
5. The single event transient resistant low level reset circuit of any one of claims 1 to 4, wherein: the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
6. The single event transient resistant low level reset circuit of any one of claims 1 to 4, wherein: the final buffer unit at the end position is connected to a flip-flop.
7. The single event transient resistant low level reset circuit of any one of claims 1 to 4, wherein: the number of the nodes in each level of buffer unit is gradually increased, and each node corresponds to one buffer unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011554124.6A CN112543019A (en) | 2020-12-24 | 2020-12-24 | Low-level reset circuit resisting single-particle transient |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011554124.6A CN112543019A (en) | 2020-12-24 | 2020-12-24 | Low-level reset circuit resisting single-particle transient |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4651029A (en) * | 1982-12-27 | 1987-03-17 | Fujitsu Limited | Decoder circuit |
| US6362669B1 (en) * | 2000-04-10 | 2002-03-26 | Xilinx, Inc. | Structure and method for initializing IC devices during unstable power-up |
| US20030025527A1 (en) * | 2001-08-03 | 2003-02-06 | Porter John D. | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and methods, circuits and systems including same |
| US20030189450A1 (en) * | 2002-04-08 | 2003-10-09 | Yoshihiko Kamata | Power on reset circuit |
| US7688117B1 (en) * | 2008-04-21 | 2010-03-30 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| CN203150081U (en) * | 2013-03-12 | 2013-08-21 | 上海贝岭股份有限公司 | Power-on resetting circuit used in liquid crystal drive circuit |
-
2020
- 2020-12-24 CN CN202011554124.6A patent/CN112543019A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4651029A (en) * | 1982-12-27 | 1987-03-17 | Fujitsu Limited | Decoder circuit |
| US6362669B1 (en) * | 2000-04-10 | 2002-03-26 | Xilinx, Inc. | Structure and method for initializing IC devices during unstable power-up |
| US20030025527A1 (en) * | 2001-08-03 | 2003-02-06 | Porter John D. | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and methods, circuits and systems including same |
| US20030189450A1 (en) * | 2002-04-08 | 2003-10-09 | Yoshihiko Kamata | Power on reset circuit |
| US7688117B1 (en) * | 2008-04-21 | 2010-03-30 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| CN203150081U (en) * | 2013-03-12 | 2013-08-21 | 上海贝岭股份有限公司 | Power-on resetting circuit used in liquid crystal drive circuit |
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