CN203150081U - Power-on resetting circuit used in liquid crystal drive circuit - Google Patents
Power-on resetting circuit used in liquid crystal drive circuit Download PDFInfo
- Publication number
- CN203150081U CN203150081U CN 201320112392 CN201320112392U CN203150081U CN 203150081 U CN203150081 U CN 203150081U CN 201320112392 CN201320112392 CN 201320112392 CN 201320112392 U CN201320112392 U CN 201320112392U CN 203150081 U CN203150081 U CN 203150081U
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- mos switches
- electrify restoration
- liquid crystal
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Abstract
The utility model discloses a power-on resetting circuit used in a liquid crystal drive circuit, which belongs to the intelligent power grid field. The power-on resetting circuit comprises a NOR gate, a postpositive inverter and M MOS switch groups which are sequentially serially connected. Each MOS switch group comprises an NMOS switch tube having a source electrode connected with the ground terminal of the power-on resetting circuit and a PMOS switch tube having a source electrode connected with the power supply terminal of the power-on resetting circuit. The drain electrode of the NMOS switch tube is connected with the drain electrode of the PMOS switch tube to form the output end of the MOS switch group. The grid electrode of the NMOS switch tube is connected with the grid electrode of the PMOS switch tube to form the input end of the MOS switch group. The output ends of the first MOS switch group to the last MOS switch group are respectively connected with a capacitor which is further connected with the ground terminal of the power-on resetting circuit. The power-on resetting circuit has the technical effects that the time period for keeping a high level of power-on resetting signals RST output by the power-on resetting circuit is prolonged.
Description
Technical field
The utility model relates to a kind of electrify restoration circuit for liquid crystal display drive circuit in intelligent grid field.
Background technology
See also Fig. 1, the electrify restoration circuit that is used for liquid crystal display drive circuit at present comprises M the MOS switches set of series connection successively, rejection gate 25 and rearmounted phase inverter 26, each MOS switches set comprises that a root utmost point connects the nmos switch pipe of this electrify restoration circuit power end (vdd terminal) and the PMOS switching tube that a root utmost point connects this electrify restoration circuit earth terminal (VSS end), the drain electrode of the drain electrode of described nmos switch pipe and described PMOS switching tube is joined and is formed the output terminal of described MOS switches set, the grid of the grid of described nmos switch pipe and described PMOS switching tube joins and forms the input end of described MOS switches set, the first input end of the input termination rejection gate 25 of first MOS switches set, second input end of the output termination rejection gate 25 of last MOS switches set, the input end of the rearmounted phase inverter 26 of the output termination of rejection gate 25, rearmounted phase inverter 26 output power-on reset signal RST.The defective that should be used for the electrify restoration circuit of liquid crystal display drive circuit is: the power-on reset signal RST of its output is difficult to keep for a long time high level; therefore this electrify restoration circuit is difficult under the situation about slowly powering on; guarantee that whole liquid crystal display drive circuit can reset reliably; the requirement that this has increased for electrostatic discharge protective circuit in the whole liquid crystal display drive circuit has increased the cost of whole liquid crystal display drive circuit.
The utility model content
The purpose of this utility model is in order to overcome the deficiencies in the prior art, a kind of electrify restoration circuit for liquid crystal display drive circuit is provided, the time that its power-on reset signal RST that can effectively prolong its output keeps high level, whole liquid crystal display drive circuit can reset reliably under the situation that guarantees slowly to power on.
A kind of technical scheme that realizes above-mentioned purpose is: a kind of electrify restoration circuit for liquid crystal display drive circuit comprises rejection gate, rearmounted phase inverter and M the MOS switches set of series connection successively;
Each described MOS switches set comprises that a root utmost point connects the nmos switch pipe of this electrify restoration circuit earth terminal and the PMOS switching tube that a root utmost point connects this electrify restoration circuit power end, the drain electrode of the drain electrode of described nmos switch pipe and described PMOS switching tube is joined and is formed the output terminal of described MOS switches set, and the grid of the grid of described nmos switch pipe and described PMOS switching tube joins and forms the input end of described MOS switches set;
First output terminal to M-1 described MOS switches set all is provided with an electric capacity that is connected with this electrify restoration circuit earth terminal.
Adopted the technical scheme of a kind of electrify restoration circuit for liquid crystal display drive circuit of the present utility model, namely first output terminal to M-1 MOS switches set all arranges an electric capacity that connects this electrify restoration circuit earth terminal in this electrify restoration circuit.Its technique effect is: the time that its power-on reset signal RST that can effectively prolong its output keeps high level, whole liquid crystal display drive circuit can reset reliably under the situation that guarantees slowly to power on, thereby reduces the cost that whole liquid crystal display drive circuit is made.
Description of drawings
Fig. 1 is the synoptic diagram of a kind of electrify restoration circuit for liquid crystal display drive circuit of prior art.
Fig. 2 is the synoptic diagram of a kind of electrify restoration circuit for liquid crystal display drive circuit of the present utility model.
Embodiment
See also Fig. 2, inventor of the present utility model be in order to understand the technical solution of the utility model better, below by embodiment particularly, and is described in detail by reference to the accompanying drawings:
See also Fig. 2, a kind of electrify restoration circuit for liquid crystal display drive circuit of the present utility model comprises a MOS switches set 21, the 2nd MOS switches set 22, the 3rd MOS switches set 23, the 4th MOS switches set 24, rejection gate 25 and rearmounted phase inverter 26.
The one MOS switches set 21 comprises that source electrode meets the first nmos switch pipe N1 of this electrify restoration circuit earth terminal (VSS end) and the PMOS switching tube P1 that source electrode connects this electrify restoration circuit power end (vdd terminal), the drain electrode of the first nmos switch pipe N1 connects the drain electrode of a PMOS switching tube P1, form the output terminal of a MOS switches set 21, the grid of the first nmos switch pipe N1 connects the grid of a PMOS switching tube P1, forms the input end of a MOS switches set 21.
The 2nd MOS switches set 22 comprises that source electrode meets the second nmos switch pipe N2 of this electrify restoration circuit earth terminal (VSS end) and the 2nd PMOS switching tube P2 that source electrode connects this electrify restoration circuit power end (vdd terminal), the drain electrode of the second nmos switch pipe N2 connects the drain electrode of the 2nd PMOS switching tube P2, form the output terminal of the 2nd MOS switches set 22, the grid of the second nmos switch pipe N2 connects the grid of the 2nd PMOS switching tube P2, forms the input end of the 2nd MOS switches set 22.
The 3rd MOS switches set 23 comprises that source electrode meets the 3rd nmos switch pipe N3 of this electrify restoration circuit earth terminal (VSS end) and the 3rd PMOS switching tube P3 that source electrode connects this electrify restoration circuit power end (vdd terminal), the drain electrode of the 3rd nmos switch pipe N3 connects the drain electrode of the 3rd PMOS switching tube P3, form the output terminal of the 3rd MOS switches set 23, the grid of the 3rd nmos switch pipe N3 connects the grid of the 3rd PMOS switching tube P3, forms the input end of the 3rd MOS switches set 23.
The 4th MOS switches set 24 comprises that source electrode meets the 4th nmos switch pipe N4 of this electrify restoration circuit earth terminal (VSS end) and the 4th PMOS switching tube P4 that source electrode connects this electrify restoration circuit power end (vdd terminal), the drain electrode of the 4th nmos switch pipe N4 connects the drain electrode of the 4th PMOS switching tube P4, form the output terminal of the 4th MOS switches set 24, the grid of the 4th nmos switch pipe N4 connects the grid of the 4th PMOS switching tube P4, forms the input end of the 4th MOS switches set 24.
The output terminal of input termination the one MOS switches set 21 of the 2nd MOS switches set 22, the output terminal of input termination the 2nd MOS switches set 22 of the 3rd MOS switches set 23, the output terminal of input termination the 3rd MOS switches set 23 of the 4th MOS switches set 24, therefore a MOS switches set 21 to the 4th MOS switches set 24 are connected successively.The first input end of the input termination rejection gate 25 of the one MOS switches set 21, second input end of the output termination rejection gate 25 of the 4th MOS switches set 24.The input end of the rearmounted phase inverter 26 of the output termination of rejection gate 25.The output terminal output power-on reset signal RST of rearmounted phase inverter 26.
Significant improvement for prior art in the present embodiment is, is provided with first capacitor C 1 that is connected with this electrify restoration circuit earth terminal (VSS end) at the output terminal of a MOS switches set 21; Be provided with this electrify restoration circuit earth terminal (VSS end) at the output terminal of the 2nd MOS switches set 22 and be connected second capacitor C 2; Output terminal in the 2nd MOS switches set 23 is provided with the 3rd capacitor C 3 that is connected with this electrify restoration circuit earth terminal (VSS end).
Improved like this purpose is: the output terminal of a MOS switches set 21 to the 3rd MOS switches set 23 on this electrify restoration circuit all is provided with the electric capacity that is connected with this electrify restoration circuit earth terminal (VSS end) to be come for energy storage.Under the situation that liquid crystal display drive circuit slowly powers on, effectively prolong the time that power-on reset signal RST keeps high level like this, guarantee that whole liquid crystal display drive circuit can reset reliably, guarantee that whole liquid crystal display drive circuit satisfies the needs that intelligent grid is used.
Those of ordinary skill in the art will be appreciated that, above embodiment illustrates the utility model, and be not to be used as restriction of the present utility model, as long as in connotation scope of the present utility model, all will drop in claims scope of the present utility model variation, the modification of the above embodiment.
Claims (1)
1. an electrify restoration circuit that is used for liquid crystal display drive circuit comprises rejection gate, rearmounted phase inverter and M the MOS switches set of series connection successively;
Each described MOS switches set comprises that a root utmost point connects the nmos switch pipe of this electrify restoration circuit earth terminal and the PMOS switching tube that a root utmost point connects this electrify restoration circuit power end, the drain electrode of the drain electrode of described nmos switch pipe and described PMOS switching tube is joined and is formed the output terminal of described MOS switches set, and the grid of the grid of described nmos switch pipe and described PMOS switching tube joins and forms the input end of described MOS switches set; It is characterized in that:
First output terminal to M-1 described MOS switches set all is provided with an electric capacity that is connected with this electrify restoration circuit earth terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320112392 CN203150081U (en) | 2013-03-12 | 2013-03-12 | Power-on resetting circuit used in liquid crystal drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320112392 CN203150081U (en) | 2013-03-12 | 2013-03-12 | Power-on resetting circuit used in liquid crystal drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203150081U true CN203150081U (en) | 2013-08-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320112392 Expired - Lifetime CN203150081U (en) | 2013-03-12 | 2013-03-12 | Power-on resetting circuit used in liquid crystal drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203150081U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945824A (en) * | 2017-11-21 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | Reset circuit and repositioning method for SONOS memories |
| CN108111150A (en) * | 2017-12-21 | 2018-06-01 | 上海贝岭股份有限公司 | Electrification reset circuit and integrated circuit and EEPROM systems |
| CN110634454A (en) * | 2019-09-25 | 2019-12-31 | 京东方科技集团股份有限公司 | Switch time sequence control circuit and method and display device |
| CN112543019A (en) * | 2020-12-24 | 2021-03-23 | 中国人民解放军国防科技大学 | Low-level reset circuit resisting single-particle transient |
-
2013
- 2013-03-12 CN CN 201320112392 patent/CN203150081U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945824A (en) * | 2017-11-21 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | Reset circuit and repositioning method for SONOS memories |
| CN108111150A (en) * | 2017-12-21 | 2018-06-01 | 上海贝岭股份有限公司 | Electrification reset circuit and integrated circuit and EEPROM systems |
| CN110634454A (en) * | 2019-09-25 | 2019-12-31 | 京东方科技集团股份有限公司 | Switch time sequence control circuit and method and display device |
| CN112543019A (en) * | 2020-12-24 | 2021-03-23 | 中国人民解放军国防科技大学 | Low-level reset circuit resisting single-particle transient |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130821 |
|
| CX01 | Expiry of patent term |