CN1949288A - Variable length coding method and circuit thereof - Google Patents
Variable length coding method and circuit thereof Download PDFInfo
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- CN1949288A CN1949288A CN 200610149071 CN200610149071A CN1949288A CN 1949288 A CN1949288 A CN 1949288A CN 200610149071 CN200610149071 CN 200610149071 CN 200610149071 A CN200610149071 A CN 200610149071A CN 1949288 A CN1949288 A CN 1949288A
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Abstract
The invention relates to a variable length coding method and its circuit. It includes address coding. When the address coding length is not more than 20 bits, one moment high level impulse signal can make the counter reset and recount. The method can realize multi-digit address coding without adding trigger. The circuit has simple application circuit structure, can realize 20, 22, 23, 24 bits address coding, reduce chip area, and reduce coding recurrence rate. The method and circuit can be used in wireless coding remote controller chip, various fields that anti-theft device, industry remote control, toy remote control etc.
Description
Technical field
The invention belongs to the address coding technique field of wireless remote control emission data, be specifically related to a kind of circuit of realizing the optional coding method of address size and using this method.
Background technology
Along with development of integrated circuits, particularly have the popularizing of consumer electronics product of wireless remote control, make people more and more can enjoy the convenience that science and technology is brought.The principle of wireless remote control is that a string data that has the high level carrier wave is sent, and goes to control corresponding apparatus by receiving trap.The basic format of its emission data is: address code+key set code.
Key set code is generally fixed, and its variation is very little.So the difference of the data of different remote depends primarily on address code.Now most widely used is HS2262 series coding chip, it is the low-power consumption universal coding circuit that a kind of CMOS of utilization technology is made, each circuit all is made up of the address code and the numeric data code of user's flexibly changing, can be used for vehicle, household theftproof system, remote-control toy and other industrial remote controls, but its data (address+button) are changed to 3 at most
12=531,141 kinds, and the coding circuit complexity, cost is higher.If realize 1,000,000 groups, 4,000,000 groups, 8,000,000 codings that make up 1,600 ten thousand groups of different lengths, the coding repetition rate of HS2262 series coded system and circuit thereof is: 1/3
12=1/531441=1.88E-6.Therefore, though the HS2262 family chip can suppress certain coding repetition rate, also can not meet the need of market far away.
Summary of the invention
The purpose of this invention is to provide a kind of method and circuit thereof that can be applicable to wireless encoding telepilot chip, the simple variable length code of circuit, can realize the geocoding of 1,000,000 groups, 4,000,000 groups, 8,000,000 groups, 1,600 ten thousand groups different lengths, reduce the repetition rate of coding of chip greatly, save chip area simultaneously, the reliability height.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of variable length decoding method is used for wireless encoding telepilot chip, comprises geocoding.When this address coding length is not more than 20, make the counter reset New count of laying equal stress on by flashy high level pulse signal, Ji Shuo length is adjusted for number according to the address again.This method is implemented in the multidigit geocoding under the situation that does not increase trigger.
Specifically, the method for this variable length code adopts the output of the input sum counter of mode selection module to control the high level pulse signal.Control the high level pulse signal again by the output of the logic after this high level pulse signal effect.Process is as follows: when the input of mode selection module all was logical zero, its output all was logical zero, and the high level pulse signal is always logical zero, selected 20 bit address code lengths this moment; When the input of mode selection module has one to be logical one, decontrol restriction, under the effect of counter output to the high level pulse signal, produce logical one, after current 20 bit address are finished, make the counter reset New count of laying equal stress on, finish 22,23 or 24 s' geocoding.
Adopt the circuit of above-mentioned variable length decoding method, comprise d type flip flop, mode selection module, counter, address load module and high level pulse generation module, it is characterized in that: the high level pulse generation module, mode selection module, counter is connected with address load module difference logic, link to each other with the CLR end of a d type flip flop after the output signal clr_c of described high level pulse generation module and the rSt_ signal NOR-operation, link to each other with the CLR end of two d type flip flops after a clr_S01 signal and the clr_c signal NOR-operation simultaneously, output signal after the CLR end connection rSt_ of all the other d type flip flops is anti-phase, the Q of described d type flip flop end is that the output terminal of circuit signal, described model selection select module and comprise two input end SEL0 and SEL1.
Concretely, described variable length code circuit adopts 5 d type flip flop outputs, the Q end of each d type flip flop is as signal output part, the D end of d type flip flop is connected with its Q_ end, the Q end of each d type flip flop is respectively as the output terminal of counter, and the CP of Q_ termination second trigger of first d type flip flop holds; The CP end of Q_ termination the 3rd trigger of second trigger; The Q_ end of the 3rd trigger and the output signal of RS trigger circuit are held with the CP that the 4th trigger is received in output; The 4th and the CLR termination rSt_ of the 5 two the trigger output signal after anti-phase, the CLR termination clr_c of the 3rd trigger and rSt_ mutually or non-output, clr_c and a clr_S01 signal and rSt_ mutually or non-output connect the CLR end of the first and second two triggers.
Described high level pulse generation module comprises a d type flip flop, the D termination power end of d type flip flop, after the output signal process logic gates computing of counter, produce signal dataclr, it links to each other with the clk end of d type flip flop, link to each other with the clk_ end through a non-dataclr_=0 who produces behind the door again, the CLP of d type flip flop end is connected by two rejection gate calculated result with an output signal of signal dataclr sum counter, and the output signal of non-end of the Q of d type flip flop and mode selection module mutually or non-generation clr_c signal; When two input signal SEL0=SEL1=0 of mode selection module, through with the not sum inverse after, output signal Saddr0=Saddr1=0, by rejection gate output=1, clr_c equals 0 all the time again, selects 1,000,000 group addresss this moment; When SEL0 or SEL1 had one to be 1 between the two, the restriction to clr_c was decontroled in rejection gate output=0; After current 20 bit address were covered, under the effect of the output signal S0～S4 of counter, by logical operation, signal dataclr can export high level, and dataclr_=0 also keeps, and d type flip flop Q_ end can output 0, then clr_c=1; Through the RS trigger circuit, its input signal is clr_c and S2, and S2 becomes 0 after the logical operation, under the acting in conjunction of S2 and dataclr_, and another rejection gate output=1, d type flip flop resets, and makes its Q_ end=1, and then clr_c equals 0, produces the high level pulse signal.
Described address load module includes 24 bit address input ports and one 5 digit counter, carries out the logic connection by logic gates between described each module and between the inside modules.
Described RS trigger circuit circuit comprises the rejection gate of one three input and the rejection gate of one two input, two input ends of three input rejection gates are respectively clr_c signal and rSt_ signal, the 3rd input end is connected with the output terminal of another two inputs rejection gate, the input signal of another two inputs rejection gate is respectively the output signal and the S2 signal of three input rejection gates, is used for controlling clr_c by the logic output of clr_c effect again with signal S2 effect.
This variable length code circuit comprises that also a fuse burns demodulation circuit, and fuse burns the corresponding connection of input port of an end with the address load module of each the fuse point in the demodulation circuit, and the other end is connected with the ground common port; The output signal of the counter in the load module of address is burnt the selection signal of demodulation circuit as fuse, with so that address bit progressively export.
The number that described fuse burns the fuse point of demodulation circuit is 24, can finish the address of 24 code lengths at most.
The input signal S1_ of the generation circuit of described clr_S01 signal passes through a non-signal behind the door as input signal of first Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of first Sheffer stroke gate, again with must go out the result, as an input signal of second rejection gate; Input signal S0_ and S1 mutually or the result after non-as an input signal of the 3rd Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of the 3rd Sheffer stroke gate, again with non-after, as another input signal of second Sheffer stroke gate, by the input signal of the second Sheffer stroke gate calculated result as the 6th Sheffer stroke gate; Input signal S0_ and S1_ with non-after output as the input signal of the 4th Sheffer stroke gate, another input end of this Sheffer stroke gate is connected with the output terminal of the 5th Sheffer stroke gate, the input end of the 5th Sheffer stroke gate is the S2 signal, the output of another input termination the 4th Sheffer stroke gate of this Sheffer stroke gate, this output result is as another input of the 6th Sheffer stroke gate; At last mutually or non-output result by the result after the 6th Sheffer stroke gate and input signal dataclr_ signal.When 20 of selections or 24 bit address, this invalidating signal; When selecting 22, when 23 or 24, S2～S0 count down to 01 or at 02 o'clock from 00, and this signal can produce a high level pulse signal, makes S1～S0 zero clearing.
Owing to the coded system of coding circuit and there is reason such as numeric data code, 5 digit counters can only be finished 20 bit address promptly 2
20=1,048,576 (1,000,000) group coding.When selecting 2
22, 2
23, 2
24When promptly 4,000,000 groups, 8,000,000 groups or 1,600 ten thousand groups, circuit can be when distributing the 20th bit address sign indicating number, clr_c can produce the high level pulse signal of a moment, 5 digit counters are resetted, again count, counting step can be adjusted according to 2,3 or 4, under the situation that does not increase trigger, only just can finish the realization of encoding like this than multidigit with a spot of logical circuit.The clr_c signal is wanted to change address size and is produced, and the high level pulse width of the generation of clr_c is the nS level, and it can make counter rework, so that can provide corresponding counting step.The validity of its width guarantees by self-locking structure, and its generation and width are worked as SEL0 by the output S0～S4 signal deciding of SEL0, SEL1 and 5 counters, and SEL1 equals at 0 o'clock, and the clr_c signal does not have the high level pulse generation.When SEL0=SEL1=0, Saddr0=Saddr1=0, then rejection gate output=1, so clr_c equals 0 all the time, selects 1,000,000 group addresss this moment.When SEL0 or SEL1 had one to be 1 between the two, the restriction to clr_c was decontroled in rejection gate output=0.After current 20 bit address were covered, under the effect of S0～S4, dataclr_=0, dataclr can export high level and keep, and d type flip flop Q_ end can output 0, then clr_c=1.So just make the S2 signal become 0.Under the acting in conjunction of S2 and dataclr_, rejection gate I367 output=1 causes the d type flip flop among this figure to reset, and makes its Q_ end=1, and then clr_c equals 0, and clr_c has just produced high level pulse like this.Control clr_c again by the logic output of clr_c effect like this, can make the clr_c level pulse minimize the validity that also can guarantee its effect by this self-locking method.
This variable length code circuit adopts 5 d type flip flops (DFFR trigger) output, and the Q end of each d type flip flop is exported S0, S1, S2, S3 and S4 signal as signal output part.Use this coding circuit and fuse burning demodulation circuit and can make clear coding circuit chip simple in structure.The fuse that fuse burns demodulation circuit can be 24, can realize 24 bit address coding, when in circuit, surveying, and when test machine can need to strengthen current signal on the fuse again, corresponding fuse failure, this logic state is 1, Rong Duan logic state is not 0.
This variable length code circuit adopts flashy high level pulse signal to make counter reset, again the method for counting has realized the more address coding length of long number then, its application circuit is simple in structure, can realize 20,22,23 and 24 bit address coding, reduced chip area, and effectively reducing the coding repetition rate, this variable length decoding method and circuit thereof can be used for being applied to fields such as various burglary-resisting installations, industrial remote control, toy remote control in the wireless encoding telepilot chip.
Description of drawings
The invention will be further elaborated below in conjunction with drawings and Examples
Fig. 1 is the circuit theory diagrams that the present invention adopts variable length decoding method;
Fig. 2 is that the present invention adopts rest-set flip-flop output signal and clr_s01 signal generating circuit figure in the circuit of variable length decoding method;
Fig. 3 is the generation circuit diagram that the present invention adopts clr_c signal in the circuit of variable length decoding method;
Fig. 4 is that the Dian Lu Zhong Rong silk of employing variable length decoding method of the present invention burns the demodulation circuit schematic diagram;
Fig. 5 is the embodiments of the invention circuit theory diagrams;
Fig. 6 is that address decoder is exported a frame sign indicating number format chart in the embodiments of the invention.
Embodiment
As Fig. 5, this variable length decoding method can be applicable in the wireless encoding telepilot chip, and its concrete circuit application is: this chip can realize 2 by the coding of built-in 24 fuse point control 24 bit address
24Group coding is applied in the various burglary-resisting installations, can realize the coding of 1,000,000 groups, 4,000,000 groups, 8,000,000 groups and 1,600 ten thousand groups different lengths simultaneously, reaches anti-theft feature.
As shown in Figure 2, this telepilot chip circuit has 28 input ports.24 are used as the address input end mouth in these 28 input ports, and 4 as the keyboard-coding input port.24 are used as in the circuit of address input end mouth, and each address input end mouth connects a fuse and burns demodulation circuit.When this fuse circuit is used, a termination GND, a termination internal circuit, during application, 24 fuses are carried out programming successively, are unsettled when blowing, and not blowing is 0, realize being logical one when blowing by the pull-up resistor in the button address decoding circuitry, do not blow and be logical zero, utilize SEL0, SEL1 to carry out model selection, thereby multipotency is realized the different geocoding of 1,600 ten thousand chips, as the button input port time spent, just need be connected with remote keypad.Each input port all is connected to pull-up circuit.
The principle of work of telepilot chip circuit shown in Figure 2 is as described below.After circuit powered on, reset circuit resetted each data latch unit, and circuit enters the power saving standby mode.If there is not key to press, circuit will be in the power saving waiting status always.If there is key to press, crystal oscillating circuit will be waken up circuit and wake up, starting oscillation, and produce the needed clock signal of chip operation.The button address decoding circuitry will be by the address size and the push button signalling decoding of actual needs under pattern control, and decode results offered address code numeric data code ROM (read-only memory) (ROM), ROM outwards provides a string binary code, i.e. a frame sign indicating number in order by turn according to address decoder.The composition form of each frame sign indicating number as shown in Figure 3.Initial code and end code are sent out a fixing sign indicating number shape.Address code is corresponding with the connected mode of geocoding input port.Numeric data code is corresponding with the button input port, the corresponding one group of data of each button input port, if the compound keys definition is arranged, then the combination of available several keys defines one group of data.
Code element generation circuit produces the code element waveform.The signal that alternative circuit (MUX) provides according to ROM is selected from " 0 " sign indicating number of code element generation circuit or " 1 " sign indicating number waveform signal and this signal is amplified the back outwards to send.
When having key to press, circuit just outwards sends a frame sign indicating number or a few frame sign indicating number.If according to not putting, it is the binary code of unit that circuit just will constantly outwards send with a frame to button, till button discharges always.After button discharges, the crystal oscillating circuit failure of oscillations, all data latch unit reset, and circuit enters power saving standby mode (dormant state).
The coding method that this telepilot chip adopts is specific as follows: when this address coding length is not more than 20, make the counter reset New count of laying equal stress on by flashy high level pulse signal, Ji Shuo length is adjusted for several according to the address again.This method is implemented in the multidigit geocoding under the situation that does not increase trigger.The method of this variable length code adopts the output of the input sum counter of mode selection module to control the high level pulse signal.Control the high level pulse signal again by the output of the logic after this high level pulse signal effect.Process is as follows: when the input of mode selection module all was logical zero, its output all was logical zero, and the high level pulse signal is always logical zero, selected 20 bit address code lengths this moment; When the input of mode selection module has one to be logical one, decontrol restriction, under the effect of counter output to the high level pulse signal, produce logical one, after current 20 bit address are finished, make the counter reset New count of laying equal stress on, finish 22,23 or 24 s' geocoding.
The physical circuit principle of the coding circuit of this telepilot chip is as follows: adopt 5 d type flip flops as output, the Q of each d type flip flop holds as signal output part.Utilize fuse to burn being connected of demodulation circuit and address input end mouth circuit, as the input of address code.Utilize SEL0, SEL1 input, can realize from 1,000,000 to 1,600 ten thousand different geocodings as model selection.Also comprise a level pulse signal moment generation high level pulse signal clr_c, change to 1,600 ten thousand process from 1,000,000 in order to the control address code length.
When described fuse circuit is used, a termination common, a termination address input end mouth circuit is during the input of address, 24 fuses are carried out programming successively, are logical one when blowing, and do not blow to be logical zero, utilize SEL0, SEL1 to carry out 1,000,000,4,000,000,8,000,000 to 1,600 ten thousand model selection.The generation of high level pulse signal is controlled by the input SEL0 of model selection, the output of SEL1 sum counter, controls the high level pulse signal again by the logic output of high level pulse signal effect.When the input of mode selection module all was logical zero, its output all was logical zero, and the high level pulse signal is always logical zero, selected 1,000,000 address coding length this moment; When the input of mode selection module has one to be logical one, relieving is to the restriction of high level pulse signal, under the effect of counter output, generation moment high level pulse is a logical one, after finish current 1,000,000 addresses, make the counter reset New count of laying equal stress on, finish 4,000,000,8,000,000 even 1,600 ten thousand geocoding, the length of this coding are selected the input signal decision by model selection.
Concrete circuit connecting relation: the Q end of 5 d type flip flops is as signal output part, and the D of each d type flip flop end is connected with its Q_ end, and the Q end of each d type flip flop is respectively as the output terminal of counter, and the CP of Q_ termination second trigger 2 of first d type flip flop 1 holds.The CP end of Q_ termination the 3rd trigger 3 of second trigger 2.The Q_ end of the 3rd trigger 3 and the output signal of RS trigger circuit are held with the CP that the 4th trigger 4 is received in output.The 44 and the CLR termination rst_ of the 55 two the trigger output signal after anti-phase, the CLR termination high level pulse signal of the 3rd trigger 3 and rst_ mutually or non-output, high level pulse signal and a clr_S01 signal and rst_ mutually or non-output connect the one 1 and the CLR end of the 22 two trigger.
The input signal S1_ of the generation circuit of described clr_S01 signal passes through a non-signal behind the door as input signal of first Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of first Sheffer stroke gate, again with must go out the result, as an input signal of second rejection gate; Input signal S0_ and S1 mutually or the result after non-as an input signal of the 3rd Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of the 3rd Sheffer stroke gate, again with non-after, as another input signal of second Sheffer stroke gate, by the input signal of the second Sheffer stroke gate calculated result as the 6th Sheffer stroke gate; Input signal S0_ and S1_ with non-after output as the input signal of the 4th Sheffer stroke gate, another input end of this Sheffer stroke gate is connected with the output terminal of the 5th Sheffer stroke gate, the input end of the 5th Sheffer stroke gate is the S2 signal, the output of another input termination the 4th Sheffer stroke gate of this Sheffer stroke gate, this output result is as another input of the 6th Sheffer stroke gate; At last mutually or non-output result by the result after the 6th Sheffer stroke gate and input signal dataclr_ signal.
Comprise a d type flip flop in the generation circuit of high level pulse, the D termination power end of d type flip flop, after the output signal process logic gates computing of counter, produce signal dataclr, it links to each other with the clk end of d type flip flop, link to each other with the clk_ end through a non-dataclr_=0 who produces behind the door again, the CLP of d type flip flop end is connected by two rejection gate calculated result with an output signal of signal dataclr sum counter, and the output signal of non-end of the Q of d type flip flop and mode selection module mutually or non-generation clr_c signal; When two input signal SEL0=SEL1=0 of mode selection module, through with the not sum inverse after, output signal Saddr0=Saddr1=0, by rejection gate output=1, clr_c equals 0 all the time again, selects 1,000,000 group addresss this moment; When SEL0 or SEL1 had one to be 1 between the two, the restriction to clr_c was decontroled in rejection gate output=0; After current 20 bit address were covered, under the effect of the output signal S0～S4 of counter, by logical operation, signal dataclr can export high level, and dataclr_=0 also keeps, and d type flip flop Q_ end can output 0, then clr_c=1; Through the combinational logic circuit of clr_c signal and S2 signal, S2 becomes 0, under the acting in conjunction of S2 and dataclr_, and another rejection gate output=1, d type flip flop resets, and makes its Q_ end=1, and then clr_c equals 0, produces the high level pulse signal.Wherein said RS trigger circuit circuit comprises the rejection gate of one three input and the rejection gate of one two input, two input ends of three input rejection gates are respectively clr_c signal and rst_ signal, the 3rd input end is connected with the output terminal of another two inputs rejection gate, the input signal of another two inputs rejection gate is respectively the output signal and the S2 signal of three input rejection gates, be used for controlling clr_c again with signal S2 effect by the logic output of clr_c effect, form the clr_c self-locking structure, the clr_c level pulse is minimized and can guarantee that counter resets fully and do not influence the width of code value by this self-locking method.
The foregoing description only is a particular instance of the present invention, must not be considered as limitation of the present invention.
Claims (10)
1, a kind of method of variable length code, be used for wireless encoding telepilot chip, comprise geocoding, it is characterized in that: address coding length is during greater than 20, make counter reset by flashy high level pulse signal, count again, counting step is according to the address size adjustment again, under the situation that does not increase trigger, finish coding than multidigit.
2, the method for a kind of variable length code according to claim 1, it is characterized in that this method adopts the output of the input sum counter of mode selection module to control the high level pulse signal, control the high level pulse signal again by the logic output of high level pulse signal effect; When the input of mode selection module all was logical zero, its output all was logical zero, and the high level pulse signal is always logical zero, selected 20 bit address code lengths this moment; When the input of mode selection module has one to be logical one, decontrol restriction, under the effect of counter output to the high level pulse signal, produce logical one, after current 20 bit address are finished, make the counter reset New count of laying equal stress on, finish geocoding greater than 20.
3. the method for a kind of variable length code according to claim 2 is characterized in that described geocoding greater than 20 is 22,23 or 24 s' a geocoding.
4. adopt the coding circuit of the method for the described a kind of variable length code of claim 1, comprise d type flip flop, mode selection module, counter, address load module and high level pulse generation module, it is characterized in that: the high level pulse generation module, mode selection module, counter is connected with address load module difference logic, link to each other with the CLR end of a d type flip flop after the output signal clr_c of described high level pulse generation module and the rSt_ signal NOR-operation, link to each other with the CLR end of two d type flip flops after a clr_S01 signal and the clr_c signal NOR-operation simultaneously, output signal after the CLR end connection rSt_ of all the other d type flip flops is anti-phase, the Q of described d type flip flop end is that the output terminal of circuit signal, described model selection select module and comprise two input end SEL0 and SEL1.
5. variable length code circuit according to claim 4, it is characterized in that described variable length code circuit adopts 5 d type flip flop outputs, the Q end of each d type flip flop is as signal output part, the D end of d type flip flop is connected with its Q_ end, the Q end of each d type flip flop is respectively as the output terminal of counter, and the CP of Q_ termination second trigger of first d type flip flop holds; The CP end of Q_ termination the 3rd trigger of second trigger; The Q_ end of the 3rd trigger and the output signal of RS trigger circuit are held with the CP that the 4th trigger is received in output; The 4th and the CLR termination rSt_ of the 5 two the trigger output signal after anti-phase, the CLR termination clr_c of the 3rd trigger and rSt_ mutually or non-output, clr_c and clr_S01 signal mutually or non-output connect the CLR end of the first and second two triggers.
6. a kind of variable length code circuit according to claim 1, it is characterized in that described high level pulse generation module comprises a d type flip flop, the D termination power end of d type flip flop, after the output signal process logic gates computing of counter, produce signal dataclr, it links to each other with the clk end of d type flip flop, link to each other with the clk_ end through a non-dataclr_=0 who produces behind the door again, the CLP of d type flip flop end is connected by two rejection gate calculated result with an output signal of signal dataclr sum counter, and the output signal of non-end of the Q of d type flip flop and mode selection module mutually or non-generation clr_c signal; When two input signal SEL0=SEL1=0 of mode selection module, through with the not sum inverse after, output signal Saddr0=Saddr1=0, by rejection gate output=1, clr_c equals 0 all the time again, selects 1,000,000 group addresss this moment; When SEL0 or SEL1 had one to be 1 between the two, the restriction to clr_c was decontroled in rejection gate output=0; After current 20 bit address were covered, under the effect of the output signal S0～S4 of counter, by logical operation, signal dataclr can export high level, and dataclr_=0 also keeps, and d type flip flop Q_ end can output 0, then clr_c=1; Through described RS trigger circuit, its input signal is clr_c signal and S2 signal, and S2 becomes 0 after the logical operation, under the acting in conjunction of S2 and dataclr_, another rejection gate output=1, d type flip flop resets, make its Q_ end=1, then clr_c equals 0, produces the high level pulse signal; Described RS trigger circuit comprise the rejection gate of one three input and the rejection gate of one two input, two input ends of three input rejection gates are respectively clr_c signal and rSt_ signal, the 3rd input end is connected with the output terminal of another two inputs rejection gate, the input signal of another two inputs rejection gate is respectively the output signal and the S2 signal of three input rejection gates, is used for controlling clr_c by the logic output of clr_c effect again with signal S2 effect.
7. a kind of variable length code circuit according to claim 4, it is characterized in that described address load module includes 24 bit address input ports and one 5 digit counter, carry out the logic connection by logic gates between described each module and between the inside modules.
8. a kind of variable length code circuit according to claim 4, it is characterized in that also comprising that a fuse burns demodulation circuit, fuse burns the corresponding connection of input port of an end with the address load module of each the fuse point in the demodulation circuit, and the other end is connected with the ground common port; The output signal of the counter in the load module of address is burnt the selection signal of demodulation circuit as fuse, with so that address bit progressively export.
9. a kind of variable length code circuit according to claim 4 is characterized in that the number of the fuse point of described fuse burning demodulation circuit is 24, can finish the address of 24 code lengths at most.
10. a kind of variable length code circuit according to claim 4, the input signal S1_ that it is characterized in that the generation circuit of described clr_S01 signal passes through the input signal of a non-signal behind the door as first Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of first Sheffer stroke gate, again with must go out the result, as an input signal of second rejection gate; Input signal S0_ and S1 mutually or the result after non-as an input signal of the 3rd Sheffer stroke gate, the output of mode selection module as a result Saddr0 and Saddr1 mutually or the result after non-as another input signal of the 3rd Sheffer stroke gate, again with non-after, as another input signal of second Sheffer stroke gate, by the input signal of the second Sheffer stroke gate calculated result as the 6th Sheffer stroke gate; Input signal S0_ and S1_ with non-after output as the input signal of the 4th Sheffer stroke gate, another input end of this Sheffer stroke gate is connected with the output terminal of the 5th Sheffer stroke gate, the input end of the 5th Sheffer stroke gate is the S2 signal, the output of another input termination the 4th Sheffer stroke gate of this Sheffer stroke gate, this output result is as another input of the 6th Sheffer stroke gate; At last mutually or non-output result by the result after the 6th Sheffer stroke gate and input signal dataclr_ signal; When 20 of selections or 24 bit address, this invalidating signal; When selecting 22, when 23 or 24, S2～S0 count down to 01 or at 02 o'clock from 00, and this signal can produce a high level pulse signal, makes S1～S0 zero clearing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101490713A CN100498863C (en) | 2006-11-24 | 2006-11-24 | Variable length coding method and circuit thereof |
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| CNB2006101490713A CN100498863C (en) | 2006-11-24 | 2006-11-24 | Variable length coding method and circuit thereof |
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| CN1949288A true CN1949288A (en) | 2007-04-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100583177C (en) * | 2007-10-19 | 2010-01-20 | 中山市泰宝电子科技有限公司 | Floating coding method of electric-controlled toy |
| CN102629236A (en) * | 2012-02-22 | 2012-08-08 | 哈尔滨工程大学 | Memory protection method based on unequal-length counter |
| CN105703780A (en) * | 2016-01-05 | 2016-06-22 | 湖南工业大学 | Matrix type keyboard scanning positioning circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2214051Y (en) * | 1994-02-03 | 1995-11-29 | 黄智伟 | Radio control switch with address coding |
| EP1203452B1 (en) * | 1999-07-13 | 2008-09-17 | Samsung Electronics Co., Ltd. | Address generating device for use in multi-stage channel interleaver/deinterleaver |
| CN2572478Y (en) * | 2002-07-24 | 2003-09-10 | 北京自动化仪表二厂 | Laser remote control address code setting device |
| CN2641982Y (en) * | 2003-09-05 | 2004-09-15 | 王永利 | 12-route digital code radio remote controlled lamp set |
| CN100392682C (en) * | 2005-04-01 | 2008-06-04 | 合肥工业大学 | Decoding chip for remote control switch of electrical appliance |
| CN200993819Y (en) * | 2006-11-24 | 2007-12-19 | 苏州市华芯微电子有限公司 | Variable length coding circuit |
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2006
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100583177C (en) * | 2007-10-19 | 2010-01-20 | 中山市泰宝电子科技有限公司 | Floating coding method of electric-controlled toy |
| CN102629236A (en) * | 2012-02-22 | 2012-08-08 | 哈尔滨工程大学 | Memory protection method based on unequal-length counter |
| CN102629236B (en) * | 2012-02-22 | 2015-02-25 | 哈尔滨工程大学 | Memory protection method based on unequal-length counter |
| CN105703780A (en) * | 2016-01-05 | 2016-06-22 | 湖南工业大学 | Matrix type keyboard scanning positioning circuit |
| CN105703780B (en) * | 2016-01-05 | 2018-09-11 | 湖南工业大学 | Matrix keyboard Scan orientation circuit |
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| CN100498863C (en) | 2009-06-10 |
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