CN105680873B - Independent keyboard scanning encoding circuit - Google Patents
Independent keyboard scanning encoding circuit Download PDFInfo
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- CN105680873B CN105680873B CN201610003266.0A CN201610003266A CN105680873B CN 105680873 B CN105680873 B CN 105680873B CN 201610003266 A CN201610003266 A CN 201610003266A CN 105680873 B CN105680873 B CN 105680873B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
Abstract
A kind of independent keyboard scanning encoding circuit is made of independent keyboard, the first shift register, the second shift register, state Code memory, encoder.The circuit is via the control for meeting scanning pulse, shift pulse that specific time sequence requires, scan the state that single key stroke, combination key operation and independent keyboard maintain, and the effective status code of same binary length and invalid state code are converted into, effective key number corresponding with each effective status code is exported after encoder encodes and either exports invalid key number corresponding with all invalid state codes；The state that different single key stroke, combination key operation and independent keyboards maintains only is embodied in not being same as above for conditional code；Button operation function is either adjusted if necessary to increase and decrease button operation function, does not need to modification keyboard scanning circuit structure, only need to encoder be changed according to the correspondence between the conditional code after increase and decrease and key number.The invention circuit does not have to write and run program, reliable operation.
Description
Technical field
The present invention relates to a kind of scanning circuit of keyboard, especially a kind of independent keyboard scanning encoding circuit.
Background technology
With the continuous development of embedded technology, current each electronic product is generally using microcontroller as control core
The heart, keyboard are widely used as main input equipment.
Current keyboard scan is mainly controlled by microcontroller, need by run the program in microcontroller come into
Row, encounters interference, program is caused to run fast, and scanning imaging system is by cisco unity malfunction.
Patent of invention " a kind of fast scanning and positioning method of matrix keyboard " application No. is CN201010153560.2 is adopted
Enter the Scan orientation process of keyboard with the mode that keyboard interrupt triggers, judged using the method that keyboard scan step is repeated several times
Whether button is effective, and the key assignments to being obtained carries out condition adjudgement；If multiple repairing weld state is identical, it is in and stablizes shape
State, key assignments are effective；If multiple repairing weld state is different, key assignments is invalid.Single key stroke or combination key operation need individually judgement, such as
It is single key stroke, then into singly-bound tupe；Key operation is combined in this way, then into Macintosh tupe.Described in the patent
Method solves since keyboard caused by the mechanical property of keyboard itself is shaken and causes the Problem-Errors such as wrong key, continuous touching,
And the support issue to Macintosh and repeat key.But the method single key stroke needs to handle respectively with combining key operation；
Not accounting for keyboard state maintains a period of time just to perform the keyboard operation function of effectively operating after；Increase and decrease button operation function
When either adjusting button operation function, need to change keyboard scan finder structure.
Invention content
In order to solve above-mentioned technical problem existing for existing keyboard scan localization method, the present invention provides a kind of stand alone types
Keyboard scan coding circuit, by independent keyboard, the first shift register, the second shift register, state Code memory, coding
Device forms.
The independent keyboard scanning encoding circuit synchronizes control by scanning pulse, shift pulse.
The independent keyboard shares N number of button, equipped with N bit keyboard status signal outputs；The N bit keyboards state letter
Number be level signal.
First shift register has the function of the input of N parallel-by-bits, the output of N parallel-by-bits and Serial output；Described second
Shift register has serial input, N parallel-by-bit output functions.
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second displacement
The serial input terminal of register is connected to the serial output terminal of the first shift register；First shift register, the second displacement are posted
The shift pulse input terminal of storage is connected to shift pulse, and the presetting pulse input terminal of the first shift register is connected to scanning
Pulse.The presetting pulse of first shift register is used to carry out the N parallel-by-bits input data of the first shift register defeated
Enter to latch.
The state Code memory is 2 × N binary registers；N positions data input pin in state Code memory connects
The N parallel-by-bit output terminals of the first shift register are connected to, in addition N data input pins are connected to the N positions of the second shift register
Parallel output terminal；The reception pulse input end of the state Code memory is connected to scanning pulse.
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to state Code memory
2 × N data output ends.
The scanning pulse, shift pulse sequential meet it is claimed below：In one cycle, scanning pulse has 1 arteries and veins
Punching, shift pulse have N number of pulse；The scanning pulse, shift pulse are all according to the sequence of 1 scanning pulse, N number of shift pulse
And it renews.
The period of the scanning pulse is 20~100ms.
First shift register, the shift pulse edge of the second shift register are effective；First shift LD
When the presetting pulse of device is that edge is effective and scanning pulse is positive pulse, it is desirable that the presetting pulse of the first shift register is rises
Along effectively, the reception pulse of state Code memory is effective for failing edge；The presetting pulse of first shift register is edge
When effectively and scanning pulse is negative pulse, it is desirable that the presetting pulse of the first shift register is effective for failing edge, conditional code deposit
The reception pulse of device is effective for rising edge.When the presetting pulse of first shift register is that high level is effective, it is desirable that scanning
Pulse is positive pulse, and the reception pulse of state Code memory is effective for failing edge；The presetting pulse of first shift register is low
When level is effective, it is desirable that scanning pulse is negative pulse, and the reception pulse of state Code memory is effective for rising edge.
The encoder is read-only memory.
2 × N positions data output end of the state Code memory exports the conditional code of 2 × N；The conditional code is by effective
Conditional code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；It is described effective
Conditional code is generated by effective keyboard operation or state, and encoder corresponds to output when inputting each effective status code corresponding effective
Key number；The invalid state code is generated by invalid keyboard operation or state, and encoder inputs all corresponding during all invalid state codes
Export invalid key number.
The encoder has M key output terminals, and the selection of M values should meet 2MMore than or equal to effective key number and invalid key number
The sum of quantity.
The independent keyboard scanning encoding circuit further includes keyboard state change pulse and generates unit, for judging solely
Whether the key number of vertical keyboard output changes, and when the key number of independent keyboard output changes, exports keyboard state
Change pulse.
The keyboard state change pulse generate unit by or door, M delay buffer and M XOR gate form；M are prolonged
Slow buffer is used to carry out signal delay respectively to the M positions key number that independent keyboard exports；The input of M XOR gate is respectively M
The input of position delay buffer, output signal；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output of door
End output keyboard state change pulse.
Meet one-to-one relationship between the N bit keyboards status signal and N number of button.
The N positions, 2 × N, M refer both to binary digit data.
The beneficial effects of the invention are as follows：The Scan orientation of state will be maintained to single key stroke, combination key operation, keyboard, by
Meet scanning pulse, shift pulse that specific time sequence requires and control the conditional code for being converted into same binary length, using unified
The mode of coding is handled, and single key stroke, combination key operation, keyboard maintain state to operate the difference for being only embodied in conditional code
On；Button operation function is either adjusted if necessary to increase and decrease button operation function, does not need to modification keyboard scanning circuit structure,
Encoder need to be only changed according to the correspondence between the conditional code after increase and decrease and key number, re-writes depositing for read-only memory
Store up content.The invention circuit is not using microcontrollers such as microcontroller, ARM, without running program, reliable operation.
Description of the drawings
Fig. 1 is independent keyboard scanning encoding schematic block circuit diagram；
Fig. 2 is the independent keyboard circuit diagram of the embodiment of the present invention；
Fig. 3 is the scanning encoding circuit diagram of the embodiment of the present invention；
Fig. 4 is the first shift-register circuit figure of the embodiment of the present invention；
Fig. 5 is the pulse sequence figure of the embodiment of the present invention；
Fig. 6 is the impulse circuit schematic diagram of the embodiment of the present invention；
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit；
Fig. 8 is the waveform correlation schematic diagram that the keyboard of the embodiment of the present invention effectively operates.
Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is independent keyboard scanning encoding schematic block circuit diagram, by independent keyboard 400, the first shift register
100th, the second shift register 200, state Code memory 500, encoder 300 form.
Fig. 2 is the circuit diagram of the independent keyboard 400 of the embodiment of the present invention, shares 4 buttons, by button S1, button S2,
Button S3, button S4 and it is connected to the pull-up resistor R1 of power supply+VCC, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4 groups
Into.4 output terminals of independent keyboard 400 correspond the state of output key S1, button S2, button S3, button S4 respectively
Signal I1, I2, I3, I4, during by key pressing, the status signal of corresponding output end is low level；It is corresponding to export when button is not pressed
The status signal at end is high level.
The first shift register 100, the second shift register 200, state Code memory 500, encoder 300 in Fig. 1
Scanning encoding circuit is formed, embodiment circuit diagram is as shown in Figure 3.The status signal of embodiment independent keyboard circuit output has
4, therefore, the first shift register 100, the second shift register 200 are all 4 binary shift registers, wherein, first
Shift register 100 has the function of input, parallel output and Serial output parallel, and the second shift register 200 has serial defeated
Enter, parallel output function；4 parallel input terminal L0~L3 of the first shift register 100 are sequentially connected to I1, I2, I3, I4,
The serial input terminal D2 of second shift register 200 is connected to the serial output terminal Q13 of the first shift register 100.First moves
Bit register 100, the second shift register 200 shift pulse input terminal CLK1, CLK2 be connected to shift pulse CP2,
The presetting pulse input terminal CLK0 of one shift register 100 is connected to scanning pulse CP1.
Requirement 8 bit binary datas of deposit of state Code memory 500,4 companies in 8 data input pin D57~D50
Be connected to parallel output terminal Q13~Q10 of the first shift register 100, in addition 4 be connected to the second shift register 200 and
Row output terminal Q23~Q20；In embodiment, D57~D54 is connected to Q23~Q20, and D53~D50 is connected to Q13~Q10.State
The reception pulse input end CLK5 of Code memory 500 is connected to scanning pulse CP1.
8 input terminal A7~A0 of encoder 300 be connected to 8 data output end Q57 of state Code memory 500~
Q50.Encoder 300, which exports, is scanned through 4 determining binary system keys number of coding.
In Fig. 3 embodiments, the second shift register 200 can select to be made of various medium-scale integration shift registers,
Or it is made of edge triggered flip flop；When forming the second shift register 200 by edge triggered flip flop, preferably touched by the D of edging trigger
Send out device composition.State Code memory 500 is made of edge triggered flip flop, is preferably made of the d type flip flop of edging trigger, for example, choosing
Selecting double D trigger CD4013, either 4D triggers 74HC175 or 8D trigger 74HC273 is formed.
Fig. 4 is the circuit diagram of the first shift register 100 of the embodiment of the present invention, by the high electricity of 4 set, reset function
Flat effective 101~104,8 nor gates 105~112 of d type flip flop form.In embodiment, the double D of the selection of d type flip flop 101~104
Trigger CD4013, trigger pulse rising edge are effective.Scanning pulse CP1 controls d type flip flop by 8 nor gates 105~112
101~104 set, reset function.By taking d type flip flop 101 as an example, when scanning pulse CP1 is high level, nor gate 105 or non-
Door 106 exports low level, and the set of d type flip flop 101, reset function are invalid；Scanning pulse CP1 be low level and L0=0 when or
The output of NOT gate 105 isThe output of nor gate 106 is L0, i.e., the set function of d type flip flop 101 is invalid, reset function has
Effect, makes Q10=0；When scanning pulse CP1 is low level and L0=1, the output of nor gate 105 isThe output of nor gate 106
For L0, i.e. the set function of d type flip flop 101 is effective, reset function is invalid, makes Q10=1.The work of d type flip flop 102~104 is former
Reason is as d type flip flop 101, when scanning pulse CP1 is low level, Q10=L0, Q11=L1, Q12=L2, Q13=L3；When
Scanning pulse CP1 be high level when, due to trigger pulse input terminal CLK10, CLK11 of d type flip flop 101~104, CLK12,
CLK13 is connected to CP2, and therefore, in the rising edge of each shift pulse CP2, the first shift register 100 moves primary position, i.e.,
Q13=Q12, Q12=Q11, Q11=Q10, Q10=0.
In Fig. 3 embodiments, encoder 300 is read-only memory.Address input end A7~A0 of read-only memory is coding
The input terminal of device 300, data output end D3~D0 of read-only memory are coding output terminal C3~C0 of encoder 300.
The operation principle of independent keyboard scanning encoding circuit is as follows：
Scanning encoding circuit scanning pulse CP1, shift pulse CP2 control under work, relevant pulse sequence figure is such as
Shown in Fig. 5.
The sequential of CP1, CP2 meet claimed below in embodiment：In one cycle, CP1 has 1 pulse, and CP2 has 4
Pulse；Each pulse according to 1 CP1 pulse, 4 CP2 pulses sequence in cycles.
Meeting CP1, CP2 pulse of timing requirements can be generated by various pulsqe distributors, and Fig. 6 is the embodiment of the present invention
Impulse circuit schematic diagram is made of oscillator 801, counter 802, pulsqe distributor 803.Clock pulse CP in Fig. 5 is by shaking
Device generation is swung, CP send to counter 802 and counted, and counter 802 is 10 system Counters, and 10 states of result P (count
Value) P0 → P9 is followed successively by, as shown in Figure 5.Pulsqe distributor 803 in embodiment is realized using ROM memory, hereon referred to as arteries and veins
Punching distribution ROM memory.The address input of pulse distribution ROM memory is connected to the counting output of counter 802, pulse distribution
2 data output ends of ROM memory are exported respectively as CP1 pulses, CP2 pulses.The write-in content of pulse distribution ROM memory
It is shown in Table 1.
1 pulse distribution ROM memory tables of data of table
The output of ROM memory address in table 1, i.e. counter is at least 4 binary codes.Under normal circumstances, counter
If 802 is regular using binary addition, corresponding 4 binary codes 0000~1001 of P0~P9 sequences, i.e. ROM memory
Location ranging from 0000~1001, the storage content of address 0000~1001 is the corresponding contents of P0~P9 in table 1.
Pulse distribution ROM memory needs 2 data outputs.If the address input of pulse distribution ROM memory has R,
When independent keyboard has the output of N bit keyboards status signal, the selection of R needs satisfaction 2RMore than or equal to 2 × (N+1).
Oscillator 801 is multivibrator.The period of scanning pulse CP1 is 20~100ms.CP1, CP2 can also be by only
Circuit or device except vertical keyboard scan coding circuit provide.
First shift register 100 is under the control of scanning pulse CP1, to the status signal of the output of independent keyboard 400
I1, I2, I3, I4 carry out data latch, and the output of the first shift register 100 at this time is known as now state key assignments；Second shift LD
Upper periodic scanning pulses CP1, via the control of 4 CP2 pulses, was latching to the first shift register by device 200 in a upper period
100 output is displaced to 200 output terminal of the second shift register, therefore, before the output of the second shift register 200 at this time is known as
State key assignments.
Existing state key assignments that scanning pulse CP1 exports the first shift register 100, the second shift register 200 export
Preceding state key assignments is latched in the output terminal of state Code memory 500, and the output of state Code memory 500 is similarly preceding state key assignments with showing
State key assignments.
First shift register 100, the equal edge of shift pulse of the second shift register 200 are effective, and therefore, CP2 can be with
It is positive pulse or negative pulse.
When the presetting pulse of first shift register 100 is that edge is effective and scanning pulse CP1 is positive pulse, it is desirable that first
The presetting pulse of shift register 100 is effective for rising edge, and the reception pulse of state Code memory 500 is effective for failing edge；The
When the presetting pulse of one shift register 100 is that edge is effective and scanning pulse CP1 is negative pulse, it is desirable that the first shift register
100 presetting pulse is effective for failing edge, and the reception pulse of state Code memory 500 is effective for rising edge.First shift LD
The presetting pulse of device 100 for high level it is effective when, it is desirable that scanning pulse CP1 be positive pulse, the reception arteries and veins of state Code memory 500
It rushes effective for failing edge；When the presetting pulse of first shift register 100 is that low level is effective, it is desirable that scanning pulse CP1 is negative
Pulse, the reception pulse of state Code memory 500 are effective for rising edge.In embodiment, the preset arteries and veins of the first shift register 100
Rush effective for low level, so scanning pulse CP1 is negative pulse, the reception pulse of state Code memory 500 is effective for rising edge.
In embodiment, the 4 existing state key assignments and 4 preceding state key assignments of 500 data output end of state Code memory output are common
Form 8 conditional codes.8 conditional codes are used to identify the current state and mode of operation of independent keyboard.For example, this reality
It applies in example, the conditional code of no key pressing is 11111111；The conditional code of S1 key singly-bound pushes is 11111110；S1 key singly-bounds
The conditional code pressed and maintained is 11101110；The conditional code of S1 keys singly-bound release operation is 11101111；S2 key singly-bounds are pressed
The conditional code of operation is 11111101；The conditional code of S4 key singly-bound pushes is 11110111；The S1 of S2+S1 combination operations is pressed
Lower operation after expression first presses S2, presses the operation of S1, the conditional code of the operation is again in the state that S2 maintenances are pressed
11011100。
Encoder 300 is used to conditional code being converted to key number.In embodiment, equipped with 7 effective keyboard operations and state,
Including：
Operation 0：The singly-bound push of button S1, key number are 0000；
Operation 1：The singly-bound push of button S2, key number are 0001；
Operation 2：The singly-bound push of button S3, key number are 0010；
Operation 3：Button S3 singly-bounds press after maintenance state, key number be 0011；
Operation 4：After button S4 singly-bounds are pressed, then the combination key operation of S1 is pushed button, key number is 0100；
Operation 5：After button S4 singly-bounds are pressed, then the combination key operation of S2 is pushed button, key number is 0101；
Operation 6：The singly-bound release operation of button S1, key number is 0110.
The conditional code and key number obtained according to above-mentioned regulation is shown in coding schedule 2：
2 coding schedule of table
| Keyboard operation | Conditional code (address) | Key number (storage data) |
| S1 singly-bounds are pressed | 11111110 | 0000 |
| S2 singly-bounds are pressed | 11111101 | 0001 |
| S3 singly-bounds are pressed | 11111011 | 0010 |
| S3 singly-bounds press maintenance | 10111011 | 0011 |
| S4+S1 combination operations | 01110110 | 0100 |
| S4+S2 combination operations | 01110101 | 0101 |
| S1 singly-bounds discharge | 11101111 | 0110 |
| Other operations or state | ******** | 1111 |
Encoder 300 is combinational logic circuit, and the circuit of design meets the logical relation of table 2.
The encoder 300 of embodiment is preferably made of read-only memory.Selected read-only memory has 8 bit address, and totally 28A 4
Position binary storage cell.7 effective keyboard operations have 7 effective status codes, corresponding 7 effective keys number with state；It will
Address A7~A0 of the conditional code as read-only memory, in 7 corresponding storage units of effective status code, inciting somebody to action accordingly
Key number is as storage data write-in.The conditional code generated except 7 effective keyboard operations and state is invalid state code, i.e. table
It is invalid state code caused by other operations or state in 2；In other storage units, invalid key number, nothing is all written
Key number is imitated as a value except 7 effective keys number, in embodiment, invalid key number is 1111.
Read-only memory always works at data output state.When there is read-only memory piece selected control system, data output to delay
When rushing control function, its piece selected control system, data output cushioning control should be made to be in effective status.
Key number in embodiment is 4 binary codes.The number of bits of key number can increase or subtract as needed
It is few, at this point, need to only select the read-only memory to match with this.If the number of bits of key number is M, the selection of M values should
Meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.When independent keyboard has the output of N bit keyboards status signal
When, read-only memory needs the input of 2 × N bit address, M-bit data output.
Button operation function is either adjusted if necessary to increase and decrease button operation function, only need to change table 2 as needed, it will
Modified content re-writes the storage content of read-only memory.
The edge of scanning pulse CP1 at the time of state Code memory 500 is carried out data latch is known as state latch edge,
It is the rising edge of CP1 in embodiment.In embodiment, when independent keyboard S1 singly-bounds are pressed, encoder 300 is pressed in S1 singly-bounds
Under, by CP1 it is preset, latch after, since the state latch of CP1 along, to the state latch edge of next CP1 until, encode
Output terminal C3~C0 run-out keies number 0000；When independent keyboard S2 singly-bounds are pressed, encoder 300 is pressed in S2 singly-bounds, is passed through
CP1 is preset, after latch, since the state latch of CP1 along, until the state latch edge of next CP1, and run-out key number
0001；After independent keyboard first presses S4, then press S1, encoder 300 S1 combine key pressing, by CP1 it is preset, latch
Afterwards, since the state latch of CP1 along, until the state latch edge of next CP1, run-out key number 0100；When free-standing key
After disk first presses S4, then press S2, encoder 300 S2 combine key pressing, by CP1 it is preset, latch after, from the state of CP1
Edge is latched to start, until the state latch edge of next CP1, run-out key number 0101；When independent keyboard S1 singly-bounds discharge,
Encoder 300 is discharged in S1 singly-bounds, by CP1 it is preset, latch after, since the state latch of CP1 along, until next CP1
Until state latch edge, run-out key number 0110；It can therefore be seen that work as identification is effective button operation of independent keyboard
When, the state latch edge of CP1 of the encoder 300 after effective button operation starts, until the state latch edge of next CP1 is
Only, effective key number of the output duration for a CP1 periodic width.
In embodiment, when independent keyboard S3 singly-bounds are pressed, encoder 300 is pressed in S3 singly-bounds, by CP1 it is preset,
After latch, since the state latch of CP1 along, until the state latch edge of next CP1, run-out key number 0010；In the case where connecing
The state latch of the CP1 come terminates until S3 singly-bounds press maintenance state along starting, by CP1 it is preset, latch after, from the shape of CP1
State latches edge and starts, until the state latch edge of next CP1,300 run-out key number 0011 of encoder；It can therefore be seen that
When identification be the maintenance state of independent keyboard when, encoder 300 exports duration of effective key number and the maintenance state
Duration be adapted.
When except the state of keyboard or operation is 7 effective keyboard operations described in table 2 and states, encoder
300 output invalid keys number 1111.Effective key number or output invalid key number are either exported, encoder 300 changes output content
At the time of state latch edge for CP1；In embodiment, rising edge at the time of encoder 300 changes output content for CP1.
The period of CP1 is the scan period of independent keyboard.The keyboard scan period in more than 20ms, can effectively keep away
The influence of key point disk key jitter；The keyboard scan period in below 100ms, is unlikely to omit keyboard operation；Therefore, CP1
Period should be controlled in 20~100ms.
Fig. 7 is that the keyboard state change pulse of the embodiment of the present invention generates the circuit diagram of unit.What it is when identification is stand alone type
During effective button operation of keyboard, the state latch edge of CP1 of the encoder 300 after effective button operation starts, until next
Until the state latch edge of a CP1, effective key number of the output duration for a CP1 periodic width.Receive the stand alone type
The device of keyboard output, needs to inquire the output of independent keyboard constantly, obtains key number.The period distances of inquiry are necessarily less than
The period of CP1.
Circuit shown in Fig. 7 is used to judge whether the key number of independent keyboard output changes, when independent keyboard exports
Key number when changing, keyboard state change pulse is exported, for the reception device of independent keyboard to be assisted to receive stand alone type
The key number of keyboard output, for example, using keyboard state change pulse as the interrupt request singal of reception device.
Circuit shown in Fig. 7 by delay buffer 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or
Door 606 forms.Delay buffer 601 is made of 4 edge triggered flip flops only with Trigger Function, and 4 edge triggered flip flops touch
The reception pulse input end that input terminal is delay buffer 601 is sent out, is connected to CP1；Delay buffer 601 is in the state of CP1
It latches along progress data latch.
Delay buffer 601 is used to carry out at delay 4 data C3~C0 of the coding output terminal of encoder 300 respectively
Reason.4 data input pin D63~D60 of delay buffer 601 are connected to coding output terminal C3~C0 of encoder 300, delay
The data that 4 data output end Q63~Q60 of buffer 601 are accordingly exported are C31~C01；C31~C01 is buffered by delay
After the first-level buffer of device 601, signal postpones a CP1 pulse period than C3~C0, and Fig. 8 show the key of the embodiment of the present invention
The waveform correlation schematic diagram that disk effectively operates.The T1 sections of CP1 pulses are located at, independent keyboard has primary effectively operation, real
The effective operation for applying example includes：S1 singly-bounds are pressed, S2 singly-bounds are pressed, S3 singly-bounds are pressed, the S1 of S4+S1 combination operations is pressed, S4+
The S2 of S2 combination operations is pressed, the release of S1 singly-bounds.On the next state latch edge once effectively operated, i.e. CP1 pulses in Fig. 8
Rising edge after T1 sections, coding C3~C0 that encoder 300 exports change；In T2 sections, the output of encoder 300 one
Efficient coding C3~C0 of a CP1 pulse periods；In T3, T4 and section later, coding C3~C0 that encoder 300 exports is another
Secondary change and enter maintenance state, which may be that such as S1 singly-bounds press maintenance state below, export invalid key
Number, it is also possible to S3 singly-bounds press maintenance state below, export effective key number, until effectively operation next time.
Coding C3~C0 that D6 pulses in Fig. 8 schematically illustrate the output of encoder 300 is in maintenance state, is not become
Change, still change, the D6 pulses are not present in actual circuit.As shown in figure 8, D6 pulses are low level, illustrate table
Show that coding C3~C0 that encoder 300 exports is in maintenance state, do not change；D6 pulses are high level, schematically illustrate volume
Code device 300 exports efficient coding C3~C0 of a cycle.What the Q6 in Fig. 8 reflected is the situation of change of C31~C01, it is clear that
Q6 postpones a CP1 pulse period than D6.Equally, the Q6 pulses are not present in actual circuit.
In Fig. 8, coding C3~C0 that encoder 300 exports is in maintenance state, does not change, still changes,
Really by 606 4 delay buffers 601, XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 or door groups
Into logic circuit complete.1 corresponding, input point that 4 XOR gates encode in output terminal C3~C0 respectively with encoder 300
It Wei not the inputs of 4 delay buffers 601, output signal.For example, two input signals of XOR gate 602 be respectively C0 and
C01, C01 postpone a CP1 pulse period than C0, and therefore, when C0 changes, XOR gate 602 exports 1 CP1 pulses week
The positive pulse of phase width；When C0 is a CP1 pulse period change width signal, XOR gate 602 exports 2 CP1 pulses weeks
The positive pulse of phase width.XOR gate 603, XOR gate 604, XOR gate 605 judge whether C1~C3 changes respectively, principle with
It is identical to judge whether C0 changes.XOR gate 602, XOR gate 603, XOR gate 604, XOR gate 605 output terminal connect respectively
It is connected to or whether the input terminal of door 606 or door 606 changes for comprehensive descision C0~C3, as long as C0~C3 changes,
Or door 606 exports keyboard state change pulse F, which is positive pulse.
In embodiment, delay buffer 601 selects the 8D triggers 74HC273 of rising edge triggering.
Delay buffer 601 can also use other schemes, for example, using RC circuits, using 4 RC circuits respectively to C0
~C3 is postponed；If the delay time of RC circuits is less than a CP1 pulse period, encoder 300 exports a cycle
Efficient coding C3~C0 when, output efficient coding C3~C0 start and export efficient coding C3~C0 terminate all generation one
Keyboard state change pulse, the width of keyboard state change pulse are equal to RC circuit delay times；If during the delay of RC circuits
Between be more than or equal to a CP1 pulse period, then encoder 300 export a cycle efficient coding C3~C0 when, have in output
Effect coding C3~C0 generates a keyboard state change pulse when starting, which is more than or equal to 2 CP1 pulse periods.
It is required that the delay time of RC circuits is no more than 2 CP1 pulse periods, failed to report in order to avoid generating.
In the invention circuit, the positioning of state operation will be maintained to single key stroke, combination key operation, keyboard, by full
2 Pulse Width Controls of sufficient specific time sequence requirement are converted into the conditional code of same binary length, by the way of Unified coding into
Row processing, single key stroke, combination key operation, keyboard maintain state operation to be only embodied in not being same as above for conditional code；If necessary to increase
Subtract button operation function and either adjust button operation function, do not need to modification keyboard scanning circuit structure, it only need to be according to increase and decrease
State code table afterwards updates encoder 300, the storage content for re-writing update read-only memory.The invention circuit
Not using microcontrollers such as microcontroller, ARM, without running program, reliable operation.
Claims (10)
1. a kind of independent keyboard scanning encoding circuit, which is characterized in that by independent keyboard, the first shift register, second
Shift register, state Code memory, encoder composition；
The independent keyboard scanning encoding circuit synchronizes control by scanning pulse, shift pulse；
The independent keyboard shares N number of button, equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is
Level signal；
First shift register has the function of the input of N parallel-by-bits, the output of N parallel-by-bits and Serial output；Second displacement
Register has serial input, N parallel-by-bit output functions；
The N parallel-by-bit input terminals of first shift register are connected to N bit keyboard status signal outputs；Second shift LD
The serial input terminal of device is connected to the serial output terminal of the first shift register；First shift register, the second shift register
Shift pulse input terminal be connected to shift pulse, the presetting pulse input terminal of the first shift register is connected to scanning arteries and veins
Punching；
The state Code memory is 2 × N binary registers；N positions data input pin in state Code memory is connected to
The N parallel-by-bit output terminals of first shift register, in addition N data input pins be connected to the N parallel-by-bits of the second shift register
Output terminal；The reception pulse input end of the state Code memory is connected to scanning pulse；
The encoder has 2 × N coding input ends, and the 2 × N coding input end is connected to 2 × N of state Code memory
Position data output end；
The scanning pulse, shift pulse sequential meet it is claimed below：In one cycle, scanning pulse has 1 pulse, moves
Digit pulse has N number of pulse；The scanning pulse, shift pulse are according to 1 scanning pulse, the sequence Zhou Erfu of N number of shift pulse
Begin.
2. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：The period of the scanning pulse
For 20~100ms.
3. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：First shift LD
Device, the shift pulse edge of the second shift register are effective；The presetting pulse of first shift register for edge effectively and
When scanning pulse is positive pulse, it is desirable that the presetting pulse of the first shift register is effective for rising edge, and state Code memory connects
It is effective for failing edge to receive pulse；Either, the presetting pulse of first shift register is edge effectively and scanning pulse is
During negative pulse, it is desirable that the presetting pulse of the first shift register is effective for failing edge, and the reception pulse of state Code memory is upper
It rises along effective.
4. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：First shift LD
Device, the shift pulse edge of the second shift register are effective；The presetting pulse of first shift register is effective for high level
When, it is desirable that scanning pulse is positive pulse, and the reception pulse of state Code memory is effective for failing edge；Either, the first displacement is posted
When the presetting pulse of storage is that low level is effective, it is desirable that scanning pulse is negative pulse, and the reception pulse of state Code memory is upper
It rises along effective.
5. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：The encoder is deposited to be read-only
Reservoir.
6. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：The state Code memory
2 × N data output ends export the conditional code of 2 × N；The conditional code is made of effective status code and invalid state code；Institute
The key number for stating encoder output is made of effective key number and invalid key number；The effective status code is by effective keyboard operation or state
It generates, encoder corresponds to output corresponding effectively key number when inputting each effective status code；The invalid state code is by invalid
Keyboard operation or state generate, and encoder inputs all corresponding output invalid key number during all invalid state codes.
7. independent keyboard scanning encoding circuit according to claim 6, it is characterised in that：The encoder has M keys
Number output terminal, the selection of M values should meet 2MMore than or equal to the sum of effective key number and the quantity of invalid key number.
8. independent keyboard scanning encoding circuit according to claim 7, it is characterised in that：Further include keyboard state variation
Impulse generating unit, whether the key number for judging independent keyboard output changes, when the key number of independent keyboard output
When changing, keyboard state change pulse is exported.
9. independent keyboard scanning encoding circuit according to claim 8, it is characterised in that：The keyboard state changes arteries and veins
Punching generate unit by or door, M delay buffer and M XOR gate form；M delay buffers are used for defeated to independent keyboard
The M positions key number gone out carries out signal delay respectively；The input of M XOR gate is respectively the input of M delay buffers, output letter
Number；The output of M XOR gate is respectively connected to or the input terminal of door；Or the output terminal output keyboard state change pulse of door.
10. independent keyboard scanning encoding circuit according to claim 1, it is characterised in that：The N bit keyboards state letter
Number meet one-to-one relationship between N number of button.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003266.0A CN105680873B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning encoding circuit |
| CN201810455342.0A CN108649962B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning coding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003266.0A CN105680873B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning encoding circuit |
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|---|---|---|---|
| CN201810455342.0A Division CN108649962B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning coding method |
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| CN105680873A CN105680873A (en) | 2016-06-15 |
| CN105680873B true CN105680873B (en) | 2018-06-26 |
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| CN201610003266.0A Active CN105680873B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning encoding circuit |
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| CN201810455342.0A Expired - Fee Related CN108649962B (en) | 2016-01-05 | 2016-01-05 | Independent keyboard scanning coding method |
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| CN112306259B (en) * | 2020-10-30 | 2023-06-02 | 维沃移动通信有限公司 | Input device, input system and input method |
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| CN101158885A (en) * | 2007-10-22 | 2008-04-09 | 李玫 | User-defined keyboard and implementing method thereof |
| CN101344767A (en) * | 2008-04-18 | 2009-01-14 | 上海海事大学 | Non-encoded keyboard and display interface of watercraft embedded micro-controller |
| CN102637075A (en) * | 2011-02-14 | 2012-08-15 | 苏州巴米特信息科技有限公司 | Design method of special matrix keyboard |
| CN203590207U (en) * | 2013-11-25 | 2014-05-07 | 皖西学院 | Matrix keyboard |
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| US3886543A (en) * | 1973-11-29 | 1975-05-27 | Teletype Corp | Debounce logic for keyboard |
| JPS55103626A (en) * | 1979-02-02 | 1980-08-08 | Toshiba Corp | Regeneration device of switch operation |
| US4761762A (en) * | 1986-04-10 | 1988-08-02 | The United States Of America As Represented By The Secretary Of The Air Force | Interrupt control switch interface system |
| CN1159641C (en) * | 2001-07-11 | 2004-07-28 | 威盛电子股份有限公司 | Keyboard instruction fetch device for notebook computer |
| CN1192300C (en) * | 2002-11-20 | 2005-03-09 | 威盛电子股份有限公司 | Keyboard control circuit of universal serial bus interface |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN103226391B (en) * | 2013-05-22 | 2015-12-23 | 湖南工业大学 | A kind of Scan orientation method of independent keyboard |
| CN104393874B (en) * | 2014-12-05 | 2017-05-10 | 京东方科技集团股份有限公司 | Touch scanning circuit, touch driving circuit and touch display screen |
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- 2016-01-05 CN CN201810455342.0A patent/CN108649962B/en not_active Expired - Fee Related
- 2016-01-05 CN CN201610003266.0A patent/CN105680873B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158885A (en) * | 2007-10-22 | 2008-04-09 | 李玫 | User-defined keyboard and implementing method thereof |
| CN101344767A (en) * | 2008-04-18 | 2009-01-14 | 上海海事大学 | Non-encoded keyboard and display interface of watercraft embedded micro-controller |
| CN102637075A (en) * | 2011-02-14 | 2012-08-15 | 苏州巴米特信息科技有限公司 | Design method of special matrix keyboard |
| CN203590207U (en) * | 2013-11-25 | 2014-05-07 | 皖西学院 | Matrix keyboard |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108649962A (en) | 2018-10-12 |
| CN108649962B (en) | 2022-01-21 |
| CN105680873A (en) | 2016-06-15 |
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