TWI425878B - Driving circuit of light emitting diode - Google Patents

Description

Light-emitting diode driving circuit

The present invention relates to a driving circuit for a light emitting diode, and more particularly to a driving circuit having a double edge triggering function.

Light Emitting Diode (LED) is small, power-saving and durable, and as the process matures, the price drops. Recently, products using light-emitting diodes as light sources are becoming more and more popular. In addition, the light-emitting diode has a low operating voltage (only 1.5-3V), can actively emit light and has a certain brightness, and the brightness can be adjusted by voltage or current, and has the characteristics of impact resistance, vibration resistance and long life (100,000 hours). Light-emitting diodes are widely used in a variety of terminal equipment, from automotive headlights, traffic lights, text displays, billboards and large-screen video displays, to general and architectural lighting and LCD backlighting.

In the conventional LED driving device, the data transmission is only accessed by using a single rising edge of the timing signal. The schematic diagram of the data sampling is shown in FIG. 1 , and FIG. 1 is a schematic diagram of data sampling according to the prior art. As shown in FIG. 1, the rising edge of the timing signal CLK triggers the driving circuit to capture the data input signal DIN, and the sampling points (such as S1, S2) correspond to the rising edge of the timing signal CLK. However, as the application of the light-emitting diode has been widely used to display visual information such as patterns and images, in order to improve the gray scale change of the LED driving display or increase the number of serial connections of the LED driving device, The data transmission amount per unit time of the LED driving device is continuously increased, that is, the frequency of the timing signal must be continuously increased, from the previous digital MHz level to the current application exceeding 30 MHz, however, higher The operating frequency increases the influence of high frequency interference, resulting in overall system stability and increasing system design difficulties.

The invention provides a driving circuit for a light-emitting diode, which uses a double-edge triggering method to extract a data input signal, and uses a rising edge and a falling edge of the timing signal to perform triggering without adding an additional control signal. Double the amount of data. Under the transmission of the same data, the frequency of the timing signal required by the present invention requires only half of the data acquisition method of the conventional LED driving circuit.

In view of the above, the present invention provides a driving circuit for a light emitting diode, comprising a double edge data transfer unit, a signal processing unit, and a light emitting diode driving unit. The dual-edge data transmission unit receives a timing signal and a data input signal, and the dual-edge trigger data transmission unit is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the data. Take the data input signal. The signal processing unit is coupled to the dual-edge data transmission unit for storing the data input signal captured by the dual-edge data transmission unit and outputting a driving enable signal according to the stored data input signal. The LED driving unit is coupled to the signal processing unit and outputs at least one driving signal to drive the at least one LED according to the driving enable signal.

In an embodiment of the invention, the dual edge capture data transfer unit includes a pulse generation circuit and a single edge trigger shift register. The pulse generating circuit generates a pulse signal according to the timing signal, wherein the pulse signal has a plurality of first pulses and a plurality of second pulses, the timing of the first pulse corresponds to a rising edge of the timing signal, and the timing of the second pulse corresponds to the timing signal Falling edge. The single-edge trigger shift register performs data sampling on the data input signal according to the pulse signal and sequentially stores the captured data input signal.

In an embodiment of the invention, the double edge extraction data transfer unit includes a double edge trigger shift temporary The buffer is triggered by the rising edge and the falling edge of the timing signal to sample the data input signal and sequentially store the captured data input signal.

In an embodiment of the invention, the driving circuit further includes a timing processing unit for receiving the timing signal and outputting the in-phase or inverted timing signals.

In an embodiment of the invention, the dual-edge data acquisition unit includes a first dual-edge trigger shift register, a second dual-edge trigger shift register, a data input signal processing circuit, and a plurality of Work tool. The first double edge trigger shift register is configured to store one image data in the data input signal; the second double edge trigger shift register is configured to store one of the data input signals; the data input signal processing circuit coupled Connected to the data input signal for outputting the data input signal in phase or inversion; the three input ends of the multiplexer are respectively coupled to the first double edge trigger shift register and the second double edge trigger shift temporary The output of the memory and the data input signal processing circuit, an output end of the multiplexer is coupled to a data output end, and the output of the multiplexer is determined according to a selection signal.

In an embodiment of the invention, the signal processing unit includes a data storage circuit and a data operation circuit. The data storage circuit is configured to store the data input signal captured by the double edge data acquisition unit; the data operation circuit is configured to output the drive enable signal.

In an embodiment of the invention, the data storage circuit includes a first data storage circuit and a second data storage circuit. The first data storage circuit stores one of the data input signals according to a first latch signal, and the second data storage circuit stores one of the data input signals according to a second latch signal.

In an embodiment of the invention, the data operation circuit includes a counter and a plurality of comparators. The comparator is coupled to the counter and the data storage circuit for comparing the stored data input signal with the output of the counter to generate a drive enable signal to the LED driver unit.

In an embodiment of the present invention, the data operation circuit includes a plurality of gates, and the inputs of the gates are respectively coupled to the data storage circuit and the uniform energy signal, and the outputs of the gates are coupled to the light emitting diodes. Drive unit.

In an embodiment of the invention, the driving circuit further includes a detection and protection unit for detecting the state of the LED and the driving circuit and outputting a detection signal to the data transmission unit, and providing the detection result according to the detection result. Protective function.

In an embodiment of the invention, the LED driving unit further includes a LED driving circuit and a driving signal setting circuit. The LED driving circuit is coupled to the signal processing unit, and outputs a driving signal according to the driving enable signal to drive the LED. The driving signal setting circuit is coupled to the LED driving circuit for adjusting the driving signal output by the LED driving circuit.

In an embodiment of the invention, the double edge data acquisition unit includes a dual edge trigger shift register, a data input signal processing circuit and a multiplexer. The dual-edge trigger shift register is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the captured data input signal; the data input signal processing circuit receives the data input signal and Outputting the data input signal in phase or inversion; the input ends of the multiplexer are respectively coupled to the output of the dual-edge trigger shift register and the output of the data input signal processing circuit, and the output end of the multiplexer is coupled to Data output.

In an embodiment of the invention, the driving signal setting circuit includes a reference voltage generating circuit, a current voltage converting circuit and a digital analog converting circuit. The digital analog conversion circuit is coupled to the signal processing unit to receive one of the data input signals; the voltage current conversion circuit is coupled to the reference voltage generating circuit and the digital analog conversion circuit for adjusting the driving output of the LED driving unit. signal.

In an embodiment of the invention, the driving circuit further includes a control unit coupled to the dual-edge data transfer unit for transmitting the timing signal and the data input signal to the dual-edge data transfer unit. And generating a control signal by using the timing signal and the data input signal.

Based on the above, the present invention utilizes the dual-edge data acquisition unit to capture the driving data of the LED, and both the rising edge and the falling edge of the timing signal can trigger the dual-edge data transmission unit to perform data acquisition. Under the same data transmission amount, the frequency of the timing signal required by the invention can be reduced to half of the conventional technology, and Electromagnetic Interference (EMI) can be reduced to increase the stability of the whole system and simplify the system design complexity.

The above described features and advantages of the present invention will be more apparent from the following description.

200, 400, 500, 600‧‧‧ drive circuits

210, 410, 610‧‧‧Double-edge data transfer unit

220, 420‧‧‧ Signal Processing Unit

230, 430, 530, 630‧‧‧Lighting diode drive unit

440, 640‧‧‧Time Processing Unit

310‧‧‧Single edge trigger shift register

320‧‧‧Pulse generation circuit

413‧‧‧Double edge capture shift register circuit

415, 615‧‧‧ data input signal processing circuit

417, 617‧‧‧ multiplexers

421, 621‧‧‧ data storage circuit

422, 622‧‧‧ data operation circuit

432, 532, 632‧‧‧Lighting diode driving circuit

450, 650‧‧‧Detection protection unit

460, 660‧‧‧ control unit

470, 570, 670‧‧‧ drive signal setting circuit

510‧‧8-bit double-edge capture shift register

521‧‧8-bit data storage circuit

522‧‧8 bit data operation circuit

613, 614‧‧‧ double edge trigger shift register

623‧‧‧First data storage circuit

624‧‧‧Second data storage circuit

672‧‧‧Digital analog conversion circuit

674‧‧‧reference voltage generation circuit

676‧‧‧Voltage current conversion circuit

680‧‧‧Power Management System

CLK, CKI, CKI ₁ , CKI ₂ ‧‧‧ timing signals

CKO‧‧‧ timing output signal

DIN‧‧‧ data input signal

DO‧‧‧ data output signal

EN‧‧‧Enable signal

LAT, LAT ₁ , LAT ₂ ‧‧‧ latch signal

MODE‧‧‧ working mode signal

PUS‧‧‧ pulse signal

P1, P2‧‧‧ pulse

S1~S3‧‧‧ sampling point

SEL‧‧‧Selection signal

43b~43z‧‧‧ comparator

43a‧‧‧ counter

FIG. 1 is a schematic diagram of data sampling according to the prior art.

2A is a block diagram of a driving circuit of a light emitting diode according to a first embodiment of the present invention.

2B is a schematic diagram showing the timing of data sampling according to the first embodiment of the present invention.

3A is an internal circuit diagram of a dual-edge capture data transmission unit according to a first embodiment of the present invention.

Fig. 3B is a waveform diagram of a pulse signal according to the present embodiment.

4 is a driving circuit in accordance with a second embodiment of the present invention.

Figure 5 is a diagram showing a driving circuit in accordance with a third embodiment of the present invention.

Figure 6 is a diagram showing a driving circuit in accordance with a fourth embodiment of the present invention.

Figure 7 is a waveform diagram of a data output signal in accordance with a fourth embodiment of the present invention.

First embodiment

Referring to FIG. 2A, FIG. 2A is a block diagram of a driving circuit of a light emitting diode according to a first embodiment of the present invention. The driving circuit 200 includes a double edge data transfer unit 210, a signal processing unit 220, and a light emitting diode driving unit 230. The signal processing unit 220 is coupled between the dual-edge capture data transfer unit 210 and the LED driver unit 230 for storing data captured by the dual-edge capture data transfer unit 210 and performing data calculation functions. A plurality of sets of multi-bit data storage circuits are included in the signal processing unit 220 for data storage. The data storage circuit is, for example, a data latch, and the number of bits is determined by design requirements, and the embodiment is not limited.

The signal processing unit 220 stores the data input signal DIN captured by the dual-edge data transfer unit 210 and operates according to the stored data input signal DIN to output a drive enable signal to the LED driving unit 230. The LED driving unit 230 generates a plurality of driving signals (for example, K, K is a positive integer) according to the driving enable signal outputted by the signal processing unit 220 to drive the LED. The LED driving unit 230 can adjust the gray scale (brightness) of the LED by adjusting the driving voltage or current.

The dual-edge data acquisition unit 210 receives the data input signal DIN and the timing signal CKI, and is triggered by the rising edge and the falling edge of the timing signal CKI to sample the data input signal DIN and sequentially store the captured data input signal. DIN. Referring to FIG. 2B, FIG. 2B is a schematic diagram of the sampling timing of the data according to the first embodiment of the present invention, wherein the sampling points S1 to S3 indicate the time point of the DIN of the data input signal captured by the double-edge data transmission unit 210. The sampling points S1, S3 correspond to the rising edge of the timing signal CKI, and the sampling point S2 corresponds to the falling edge of the timing signal CKI. As can be seen from FIG. 2B, under the timing signal CKI of the same frequency, the double-edge data transmission unit 210 will double the data acquisition amount than the single-edge circuit. If the amount of data to be acquired is the same, the frequency of the timing signal CKI can be lowered. A low half of the conventional timing signal allows the dual edge capture data transfer unit 210 to capture the desired amount of data.

The internal circuit of the dual-edge data transmission unit 210 can be directly implemented by using a dual-edge trigger shift register, or can be realized by using a pulse generation circuit and a single-edge trigger shift register. Referring to FIG. 3A, FIG. 3A is an internal circuit diagram of a dual-edge capture data transmission unit according to a first embodiment of the present invention. The double edge capture data transfer unit 210 includes a pulse generation circuit 320 and a single edge trigger shift register 310. The pulse generating circuit 320 is coupled to the single-edge trigger shift register 310 for converting the received timing signal CKI. The pulse generating circuit 320 generates a pulse signal according to the timing signal CKI, when the timing signal CKI transitions from a low level to a high level (ie, a rising edge) or a high level to a low level (ie, a falling edge). The pulse generating circuit 320 generates a pulse.

Please refer to FIG. 3B. FIG. 3B is a waveform diagram of a pulse signal according to the embodiment. As can be seen from FIG. 3B, the pulse signal PUS will generate a corresponding pulse corresponding to the rising edge and the falling edge of the timing signal CKI. The timing of the pulse P1 corresponds to the rising edge of the timing signal CKI, and the timing of the pulse P2 corresponds to the falling edge of the timing signal. Among them, it is worth noting that the width of each pulse in the pulse signal PUS is less than half a cycle of the timing signal CKI, avoiding the overlap of the waveforms of adjacent pulses. When the clock period in the timing signal CKI is smaller, the corresponding pulse width must also be smaller.

Since the pulse generation circuit 320 can convert the timing signal CKI into a pulse signal PUS having twice the number of pulses, the single-edge trigger shift register 310 uses a positive edge trigger or a negative edge trigger to capture data. The effect of twice the amount of data acquisition can be achieved by the pulse signal PUS. In this embodiment, the single-edge trigger shift register 310 performs the method of positive edge triggering. Therefore, the rising edge of each pulse in the pulse signal PUS performs the data sampling operation, and the sampling is performed. Time and direct use of the dual edge trigger register to achieve the sampling time and data sampling rate of the dual edge data transfer unit 210 with.

Since a light-emitting diode display usually has a plurality of light-emitting diodes, if a single driving chip is insufficient to drive all of the light-emitting diodes, a plurality of driving wafers are usually connected in series for driving. At this time, the received data input signal DIN needs to be transmitted between the driving chips to achieve the function of driving the plurality of light emitting diodes. Therefore, in this embodiment, the double-edge capture data transfer unit 210 can transfer the data input signal DIN to the drive circuit of the next stage according to the circuit setting after the data input signal DIN is captured. The signal outputted by the dual-edge data transmission unit 210 at the data output end is referred to as a data output signal DO, wherein the data output signal DO may be an in-phase or inverted data input signal DIN, or may output a double-edge data acquisition. The data retrieved by unit 210. In addition, the driving circuit 200 can also output the in-phase or inverted timing signal CKI.

Second embodiment

Referring to FIG. 4 for the transmission of the data input signal DIN, FIG. 4 is a driving circuit according to a second embodiment of the present invention. The driving circuit 400 includes a dual edge data transmission unit 410, a signal processing unit 420, a light emitting diode driving unit 430, a timing processing unit 440, a detection protection unit 450, and a control unit 460. The signal processing unit 420 includes a data storage circuit 421 and a data operation circuit 422, and the LED driving unit 430 includes a light emitting diode driving circuit 432 and a driving signal setting circuit 470. The double edge capture data transfer unit 410 includes a double edge capture shift temporary storage circuit 413, a data input signal processing circuit 415, and a multiplexer 417. The input end of the multiplexer 417 is coupled to the output of the dual-edge capture shift register circuit 413 and the data input signal processing circuit 415, and the output of the multiplexer 417 is coupled to the data output end of the drive circuit 400, and The selection signal SEL outputted by the control unit 460 selects the output of one of the double-edge capture shift register circuit 413 and the data input signal processing circuit 415 to generate the data output signal DO.

The data input signal processing circuit 415 can output a positive or negative data input signal according to the setting. No. DIN, when outputting the inverted data input signal DIN, it can effectively reduce the attenuation of the data input signal DIN during transmission. After the data input signal DIN is transmitted through the drive circuit of several stages, the pulse width of the data input signal DIN and its waveform are still maintained. The timing processing unit 440 is configured to transmit the timing signal CKI, and may output a timing signal CKI of a positive phase or an inverted phase according to the setting to generate the timing output signal CKO. Similarly, when the inverted timing signal CKI is output, the attenuation problem of the timing signal CKI at the time of transmission can be effectively reduced. After the timing signal CKI is transmitted through the driving circuit of several stages, the pulse width of the timing signal CKI and its waveform are still maintained.

Since the variation of the process causes the drive circuit to have a difference between the rising edge time and the falling edge time when transmitting the signal, the signal can be effectively inverted to eliminate the difference between the rising edge time and the falling edge time by inverting the signal and then transmitting the signal. Problems such as signal attenuation or distortion.

In addition, in the circuit structure, the timing processing unit 440 can be directly coupled between the timing signal CKI and the clock output terminal for transmitting the in-phase or inverted timing signal CKI to the driving circuit of the next stage. That is, the driving circuit 400 can selectively transmit the data input signal DIN and the timing signal CKI to the driving circuit of the next stage or output the internal state value of the driving circuit 400 to the system through the data output terminal and the timing signal output terminal for monitoring. With adjustments.

The double edge capture shift register circuit 413 can be composed of a double edge shift register or a single edge shift register 310 and a pulse generating circuit 320 (as shown in FIG. 3). The double-edge capture shift register circuit 413 is triggered by the rising edge and the falling edge of the timing signal CKI, and samples the data input signal DIN in a double-edge manner and sequentially stores the captured data input signal. DIN.

The data storage circuit 421 is coupled between the data operation circuit 422 and the double edge capture shift register circuit 413, and is latched in the shift register circuit 413 according to the latch signal LAT outputted by the control unit 460. The temporarily stored data is then transferred to the data operation circuit 422 for calculation. The data operation circuit 422 is based on The extracted data input signal DIN outputs a drive enable signal to the LED circuit 432 to output a corresponding drive signal. The data operation circuit 422 may be composed of a gate or a digital comparator, but the present invention is not limited thereto. In this embodiment, the LED driving circuit outputs K driving signals, and K is a positive integer.

The driving diode setting unit 430 is mainly composed of the LED driving circuit 432 and the driving signal setting circuit 470. The driving signal setting circuit 470 is coupled to the LED driving circuit 432. The driving signal setting circuit 470 is mainly used. The magnitude of the drive current, voltage, or duty cycle of the LED driving circuit 432 is set. The drive signal setting circuit 470 can also set the required parameters according to the data input signal DIN received by the drive circuit 400 to adjust the drive signal output by the LED driver circuit 432. The drive signal setting circuit 470 can receive the required command material directly via the double edge capture data transfer unit 410 or receive a different work mode adjustment signal MODE via the control unit 460.

The control unit 460 is coupled to the dual edge capture data transfer unit 410, the data storage circuit 421, and the detection protection unit 450. The control unit 460 can output a control signal or a parameter setting signal such as the shackle signal LAT, the operation mode signal MODE, and the selection signal SEL according to the waveform combination of the data input signal DIN and the timing signal CKI or the transmitted data. In addition, when the data input signal DIN and the timing signal CKI are encoded data, the control unit 460 can also be used to decode the data input signal DIN and the timing signal CKI, and then input the decoded data input signal DIN and timing. The signal CKI is passed to the double edge capture data transfer unit 410.

Since the driving circuit 400 can have multiple driving modes, or a plurality of adjustment parameter values. The control unit 460 can determine its parameter value directly via the data input signal DIN and the timing signal CKI. In other words, the data input signal DIN includes image data and command data, the image data is used to determine the gray scale value of the light emitting diode, and the command data is used to set the parameter value in the driving circuit 400. The control unit 460 can The mode setting signal MODE is output according to the command data in the data input signal DIN to adjust the working mode of the detecting and protecting unit 450 to detect different circuit parameters and environmental state values.

The detection protection unit 450 can detect the internal state of the driving circuit according to the working mode signal MODE, such as temperature, voltage, current, whether the circuit is disabled, and the state of the LED, such as open circuit, short circuit, damage, aging. Degree and so on. The detection and protection unit 450 can add a detection component and a detection function required in a general circuit for circuit state monitoring and immediate adjustment. It should be noted that the detection and protection unit 450 can perform circuit detection and circuit protection according to parameters set by the designer, such as overheat protection or overvoltage protection, and the detection protection unit 450 can transmit the data transmission unit through the double edge. 410 or a specific signal pin outputs the detection result.

Third embodiment

Next, the driving circuit of the present invention will be further described by taking an 8-bit driving circuit as an example. Please refer to FIG. 5. FIG. 5 is a diagram of a driving circuit according to a third embodiment of the present invention. The driving circuit 500 includes an 8-bit dual-edge capture shift register 510, an 8-bit data storage circuit 521, an 8-bit data operation circuit 522, and a light-emitting diode driving unit 530, wherein the light-emitting diode driving unit 530 The illuminating diode driving circuit 532 and the driving signal setting circuit 570 are included. The 8-bit data operation circuit 522 is coupled between the LED driving unit 530 and the 8-bit data storage circuit 521, and the 8-bit data storage circuit 521 is provided. The other side is coupled to the 8-bit dual-edge capture shift register 510. It should be noted that the LED driving circuit 432 may include eight LED driving circuits to output eight driving signals.

The 8-bit data storage circuit 521 performs data latching according to the latch signal LAT to store the data captured by the 8-bit dual-edge capture shift register 510. The data operation circuit 522 is composed of a plurality of gates, and the input of the individual gates is coupled to the enable signal EN and the drive data output by the data storage circuit 521. The data operation circuit 522 determines the light emission according to the data stored in the 8-bit data storage circuit 521 and the enable signal EN, respectively. Whether the diode drive circuit 532 is enabled to output a drive signal. In this embodiment, the 8-bit dual-edge capture shift register 510 and the 8-bit data storage circuit 521 are illustrated by taking an 8-bit as an example. However, the above circuit structure is not limited to 8-bit. A circuit structure that can be applied to higher or lower bits. It should be noted that the latch signal LAT and the enable signal EN may be output by the control unit or externally input, and the embodiment is not limited. The remaining components of the drive circuit 500 and the manner of operation thereof are described with reference to the above-described embodiment of FIG. 4, and are not described herein.

Fourth embodiment

Since the data input signal can include a plurality of materials, including image data and command data for setting the working mode, the double-edge data transfer unit and the signal processing unit in the driving circuit can also be configured with two sets of data storage circuits. Please refer to FIG. 6. FIG. 6 is a circuit diagram of a driving circuit according to a fourth embodiment of the present invention. The driving circuit 600 includes a dual-edge data transfer unit 610, a data storage circuit 621, a data operation circuit 622, a light-emitting diode driving unit 630, a timing processing unit 640, a detection protection unit 650, a control unit 660, and a power management system 680. .

The double edge capture data transfer unit 610 includes double edge trigger shift registers 613, 614, a multiplexer 617, and a data input signal processing circuit 615. The three input ends of the multiplexer 617 are respectively coupled to the dual-edge trigger shift register 613, 614 and the data input signal processing circuit 615, and the control end thereof is coupled to the control unit 660, and the output end of the multiplexer 617 is connected. The data output end of the driving circuit 600 is coupled to output a data output signal DO. The data input signal processing circuit 615 can transmit the in-phase or in-phase of the data input signal DIN to the data output end of the driving circuit 600 through the multiplexer 617.

The control unit 660 outputs the timing signals CKI ₁ , CKI ₂ and the data input signal DIN to the double-edge trigger shift registers 613, 614 according to the timing signal CKI, respectively. The dual-edge trigger shift registers 613 and 614 retrieve the data input signal DIN according to the timing signals CKI ₁ and CKI ₂ and sequentially transmit the data of the captured data. The control unit 660 also outputs the data input signal DIN to the data input processing circuit 615, and the data input processing circuit 615 can output the in-phase or inverted data input signal DIN. The control unit 660 switches the multiplexer 617 with the selection signal SEL to selectively switch the data output signal DO to be output.

The dual-edge trigger shift registers 613 and 614 are all buffers belonging to the double-edge trigger, and can be triggered by the rising edge and the falling edge of the timing signals CKI ₁ and CKI ₂ for data sampling. In this embodiment, the double-edge trigger shift register 613 is, for example, M 12-bit dual-edge trigger shift registers, and the double-edge trigger shift register 614 is, for example, a 7-bit double. The edge triggers the shift register, where M is a positive integer representing the number of drive signals. It should be noted that the timing signals CKI ₁ , CKI ₂ can be generated by the control unit 660 according to the timing signal CKI.

The timing processing unit 640 is the same as the above embodiment, and is mainly used to transmit the timing signal CKI to generate the timing output signal CKO. In conjunction with the data output signal DO and the timing output signal CKO, the driving circuit 600 can output a state value inside the circuit or transfer the data input signal DIN and the timing signal CKI to the driving circuit of the next stage. The operation of the timing processing unit 640 is the same as that of the previous embodiment, and will not be described here.

The data storage circuit 621 and the data operation circuit 622 are combined to form a signal processing unit, which is coupled between the dual-edge capture data transfer unit 610 and the light-emitting diode drive unit 630. The data storage circuit 621 further includes a first data storage circuit 623 and a second data storage circuit 624. The first data storage circuit 623 and the second data storage circuit 624 can latch the data (such as image data or command data) captured by the double-edge trigger shift registers 613, 614 according to the latch signals LAT ₁ and LAT ₂ , respectively. . The first data storage circuit 623 can include M 12-bit data storage circuits to correspond to the data captured by the dual-edge trigger shift register 613. The second data storage circuit 624 is, for example, a 7-bit data storage circuit to correspond to the data captured by the dual edge trigger shift register 614. It should be noted that the latch signals LAT ₁ , LAT ₂ may be generated by the control unit 660, but are not limited to being generated by the control unit 660, and may also be provided by the outside (front end circuit or system).

The data operation circuit 622 includes a counter 43a and a plurality of comparators 43b to 43z (for example, digital comparators). The comparators 43b to 43z are used to compare the output of the counter 43a with the data latched in the first data storage circuit 623, and then So that the LED driving unit 630 outputs M driving signals. The data operation circuit 622 performs image data calculation by the counter 43a and the plurality of comparators 43b to 43z, and the function thereof can be regarded as a pulse width modulation unit for adjusting the LED driving unit. 630 received pulse width adjustment signal. At the same time, it also has a function of enabling the light-emitting diode driving unit 630 to output a driving signal.

The drive signal setting circuit 670 includes a digital analog conversion circuit 672, a reference voltage generation circuit 674, and a voltage current conversion circuit 676. The reference voltage generating circuit 674 is coupled to the voltage-current converting circuit 676, and the digital analog converting circuit 672 is coupled between the data storage circuit 624 and the voltage-current converting circuit 676. The digital analog conversion circuit 672 converts the command data stored in the data storage circuit 624 into an analog signal (eg, voltage) for output to the voltage current conversion circuit 676, and the voltage current conversion circuit 676 is based on the command data and the output of the reference voltage generation circuit 674. The driving signal of the light emitting diode driving circuit 632 is adjusted.

In addition, it should be noted that the components in the dual-edge data transfer unit 610, the data storage circuit 621, and the data operation circuit 622 can be designed as electronic components of different bits according to different usage requirements, and the transmission path and data transmission. The method is also adjusted according to the required number of data bits, and the present invention is not limited to the number of bits described in the above embodiments. In addition, the type of the data input signal DIN may be a general logic signal or a differential signal, and the embodiment is not limited.

The power management system 680 is mainly used to manage the power supply of the driving circuit 600, such as a PWM power manager or a linear power management system. Manager). The control unit 660 can obtain an operating mode data according to the combination of the received data input signal DIN and the timing signal CKI, and output an operating mode signal MODE to the detecting and protecting unit 650 to perform operation mode switching or parameter setting or circuit. Status detection. The detection protection unit 650 can restore the detected parameter values to the dual edge capture data transfer unit 610 and then output the data output signal DO.

In addition, it is worth noting that the clock output signal CKO and the data output signal DO can be set according to the parameter to output the in-phase timing signal CKI and the data input signal DIN or the output inverted timing signal CKI and the data input signal DIN. In addition, if the data input signal DIN and the data output signal DO need to be coded and decoded, a decoder may be added to the control unit 660, and an output of the driving circuit 600 may be provided with an encoder for encoding and decoding data. The remaining circuit operation details of the driving circuit 600 described in FIG. 6 are as described in the first and second embodiments above, and are not described here.

Next, please refer to FIG. 7 and FIG. 7 for waveform diagrams of data output signals according to a fourth embodiment of the present invention. Taking 12-bit image data and 8 driving signals (the LED driving circuit 630 can output 8 driving signals) as an example, when the driving circuit 600 sequentially outputs the double-edge capturing shift temporary storage circuit 613 When the data is retrieved, the data output signal DO is delayed by 96 bits from the data input signal DIN. Since the double-edge capture shift register circuit 613 performs data sampling in a double-edge trigger manner, the double-edge capture shift register circuit 613 can complete 96 bit data only by using the 48-cycle timing signal CKI. Sampling.

In summary, the LED driving circuit of the present invention has a dual-edge triggering circuit, so that data access can be performed with a lower frequency timing signal, thereby reducing the high frequency signal to the driving circuit. Electromagnetic interference and increased stability of the drive circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended patent application.

600‧‧‧ drive circuit

610‧‧‧Double-edge data transfer unit

613, 614‧‧‧ double edge trigger shift register

615‧‧‧Data input signal processing circuit

617‧‧‧Multiplexer

621‧‧‧Data storage circuit

622‧‧‧Data operation circuit

623‧‧‧First data storage circuit

624‧‧‧Second data storage circuit

630‧‧‧Lighting diode drive unit

632‧‧‧Lighting diode drive circuit

640‧‧‧Time Processing Unit

650‧‧‧Detection protection unit

660‧‧‧Control unit

670‧‧‧Drive signal setting circuit

672‧‧‧Digital analog conversion circuit

674‧‧‧reference voltage generation circuit

676‧‧‧Voltage current conversion circuit

680‧‧‧Power Management System

CKI, CKI ₁ , CKI ₂ ‧‧‧ timing signals

CKO‧‧‧ timing output signal

DIN‧‧‧ data input signal

DO‧‧‧ data output signal

LAT ₁ , LAT ₂ ‧‧‧ latch signal

MODE‧‧‧ working mode signal

SEL‧‧‧Selection signal

43b~43z‧‧‧ comparator

43a‧‧‧ counter

Claims (13)

A driving circuit for a light-emitting diode includes: a double-edge data transfer unit receiving a timing signal and a data input signal, wherein the double-edge data transfer unit is performed by rising and falling edges of the timing signal Triggering to perform data sampling on the data input signal and sequentially storing the captured data input signal; a signal processing unit coupled to the dual edge data transmission unit for storing the double edge data transmission The data input signal captured by the unit outputs a driving enable signal according to the stored data input signal; and a light emitting diode driving unit coupled to the signal processing unit and outputting according to the driving enable signal The at least one driving signal is used to drive the at least one light emitting diode; wherein the light emitting diode driving unit further comprises: a driving signal output circuit coupled to the signal processing unit, and outputting the driving signals according to the driving enable signal Driving the light emitting diodes; and a driving signal setting circuit coupled to the driving signal output circuit for adjusting the driving The output signal of the driving signal output circuit. The driving circuit of claim 1, wherein the dual-edge data transmission unit comprises: a pulse generating circuit, and generating a pulse signal according to the timing signal, wherein the pulse signal has a plurality of first pulses and a plurality of a second pulse, the timing of the first pulses corresponds to a rising edge of the timing signal, the timing of the second pulses corresponds to a falling edge of the timing signal; and a single edge trigger shift register, according to the second pulse The pulse signal samples the data input signal and sequentially stores the captured data input signal. The driving circuit of claim 1, wherein the double edge data transfer unit comprises: A dual edge trigger shift register is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the captured data input signal. The driving circuit of claim 1, wherein the double edge data transfer unit comprises: a double edge trigger shift register, triggered by the rising edge and the falling edge of the timing signal to the data The input signal is used for data sampling and sequentially stores the captured data input signal; a data input signal processing circuit receives the data input signal and outputs the data input signal in phase or inversion; and a multiplexer, the plurality A first input end of the multiplexer is coupled to the output of the dual-edge trigger shift register, and a second input end of the multiplexer is coupled to the output of the data input signal processing circuit, the multiplexer An output is coupled to a data output. The driving circuit of claim 1, further comprising: a timing processing unit, receiving the timing signal and outputting the timing signal in phase or inversion. The driving circuit of claim 1, wherein the dual edge data transfer unit comprises: a first double edge trigger shift register for storing one image data of the data input signal; a second dual-edge trigger shift register for storing one of the data input signals; a data input signal processing circuit for receiving the data input signal and outputting the data input signal in phase or inversion; and a multiplexer, wherein the three input ends of the multiplexer are respectively coupled to the output of the first double edge trigger shift register, the second double edge trigger shift register, and the data input signal processing circuit, An output end of the multiplexer is coupled to a data output end, and determines an output of the multiplexer according to a selection signal. The driving circuit of claim 1, wherein the signal processing unit comprises: a data storage circuit for storing the data input signal captured by the dual edge data transfer unit; and a data operation circuit for outputting the drive enable signal. The driving circuit of claim 7, wherein the data storage circuit comprises: a first data storage circuit, storing one image data in the data input signal according to a first latch signal; and a second data The storage circuit stores a command data in the data input signal according to a second latch signal. The driving circuit of claim 7, wherein the data operation circuit comprises: a counter; and a plurality of comparators coupled to the counter and the data storage circuit for comparing the stored data input signals And outputting the counter to generate the driving enable signal to the LED driving unit. The driving circuit of the seventh aspect of the invention, wherein the data operation circuit comprises: a plurality of gates, wherein the inputs of the gates are respectively coupled to the data storage circuit and the uniform energy signal, and the output of the gates The second LED driving unit is coupled to the LED. The driving circuit of claim 1, further comprising: a detecting and protecting unit for detecting the state of the light emitting diode and the driving circuit and outputting a detecting signal to the data transfer unit. The driving circuit of claim 1, wherein the driving signal setting circuit comprises: a reference voltage generating circuit; a digital analog conversion circuit coupled to the signal processing unit to receive one of the data input signals; and a voltage current conversion circuit coupled to the reference voltage generating circuit and the digital analog conversion And a circuit for adjusting the driving signals output by the LED driving unit. The driving circuit of claim 1, further comprising: a control unit coupled to the dual-edge data transfer unit for transmitting the timing signal and the data input signal to the dual-edge data And transmitting a unit and combining a timing signal with the data input signal to generate a control signal.