TW201041445A - Driving circuit of light emitting diode - Google Patents

Driving circuit of light emitting diode Download PDF

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Publication number
TW201041445A
TW201041445A TW98115406A TW98115406A TW201041445A TW 201041445 A TW201041445 A TW 201041445A TW 98115406 A TW98115406 A TW 98115406A TW 98115406 A TW98115406 A TW 98115406A TW 201041445 A TW201041445 A TW 201041445A
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Taiwan
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signal
circuit
data
edge
driving
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TW98115406A
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Chinese (zh)
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TWI425878B (en
Inventor
Chun-Ting Kuo
Chun-Fu Lin
Cheng-Han Hsieh
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My Semi Inc
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Abstract

A driving circuit of light emitting diode is provided in the present invention, which includes a double edge trigger data capturing transmission unit to sample a data input signal with double trigger manner. The present invention utilizes rising edge and falling edge of a clock signal to perform triggers to sample data so that twice data rate is obtained. Thereby, the frequency of the clock signal in the present application is reduced to half frequency of the clock signal in related art so that the stability of system is increased.

Description

201041445 30689twf.doc/n 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種發光二極體的驅動電路,且特別 是有關於一種具有雙緣觸發擷取功能的驅動電路。 【先前技術】 發光二極體(Light Emitting Diode,LED)的體積小、省 電且耐用,而且隨著製程的成熟,價格下降,近來以發光 —極體做為光源之產品越來越普遍。此外’發光二極體工 作電壓低(僅1.5-3V)、能主動發光且有一定亮度,亮度 可用電壓或電流調節,同時具備耐衝擊、抗振動、壽命長 (10萬小時)之特點,是以,發光二極體在各種終端設備 中被廣泛使用,從汽車前照燈、交通信號燈、文字顯示器、 看板及大螢幕視頻顯示器,到一般建築照明和LCD背光等 領域。 傳統的發光二極體驅動裝置,其資料傳遞僅利用時序 信號單一上升緣來進行存取,其資料取樣的示意圖如圖i 所示,圖1為根據習知技術之資料取樣示意圖。如圖i所 示’ B守序k號CLK的上升緣會觸發驅動電路揭取資料輸入 信號DIN,其取樣點(如S1、S2)會對應於時序信號cLK 的上升緣。然而,隨著發光二極體的應用已廣泛的被用來 顯示圖案:影像等視覺資訊,為了提高發光二極體驅動顯 不灰階的變化或是增加發光二極體驅動裝置的串接數目, 使得發=二極體驅動裝置單位時間内的資料傳輸量不斷的 增加’意㈣序錢頻率必須不斷的提升,由從前的數 201041445 30689twf.doc/n MHz等級提升舰在的超過3GMHz的應用,然而 的操作頻率會增加高頻干_影響,造成 = 定,也增加系統設計的困難。 的t 【發明内容】 本發明提供一種發光二極體的驅動電路,利 Ο Ο 發的方式來擷取資料輪入信號,在不增加額外的控制传號 的情況下,利用時序信號的上升緣與下降緣來進行觸^ 取得兩倍的育料量。在相同資料的傳輪量下,本發 的時序信號的頻率僅需傳統發光二極體驅動電㈣料 方法的一半。 、 承上述’本發明提供一種發光二極體的驅動電路,包 括一雙緣擷取資料傳遞單元、一信號處理單元以及一發光 ^極體驅動單元。雙緣擷取諸傳遞單元接收—時序信號 ^料輸入信號,上述雙緣觸發資料傳遞單元係由時序 升緣Γ降緣進行觸發崎龍輸人信號進行資 羡並錄稍存所擷取之_輸人錢。信號處理單 雙f擷取資料傳遞單元,用以儲存雙緣擷取資料 所擷取的資料輸人信號並根據所儲存之資料輸入 C:驅動致能信號。發光二極體驅動單元減於信 ΐΐϊ早兀 據驅動致能信號輪出至少一伽動信號 以驅動至少一個發光二極體。 括-月—貫施例中,上述雙緣擷取資料傳遞單元包 路與^緣觸發移位暫存器。脈衝產生電 乂 、 產生一脈衝信號,其中脈衝信號具有複數 201041445 30689twf.doc/n 個第一脈衝與複數個第二脈衝’第—脈衝的時序對應於時 序#號的上升緣,弟一脈衝的時序對應於時序信|虎的下降 緣。單緣觸發移位暫存器根據脈衝信號對資料輪入信號進 行資料取樣並且依序儲存所擷取之資料輸入信號。儿 在本發明一實施例中,上述雙緣擷取資料傳遞單元包 括一雙緣觸發移位暫存器,由時序信號的上升緣與下降= 進行觸發以對資料輸入信號進行資料取樣並且依序儲存 擷取之資料輸入信號。 在本發明一實施例中,上述驅動電路更包括一時序声 理單元,用以接收時序信號並用以輸出同相或反相之時J 4吕5虎0 在本發明一實施例中,上述雙緣擷取資料傳遞單元包 括第一雙緣觸發移位暫存器、一第二雙緣觸發移位暫存 器、一資料輸入信號處理電路以及一多工器。第—雙4觸 ,移位暫存器用以儲存該資料輸入信號中之一影像^料; 第二雙緣觸發移位暫存器用以儲存該資料輸人信號中之丄 :令資料;資料輸人信號處理電_接於f料輸入訊號, 用以輸出_或反相之該資料輪人信號;多H個輸 =端^_接於第-雙緣觸發移位暫存器、第二雙緣解 ^位暫存器與資料輸人信號處理電路的輪出,多工哭的^ 接於一資料輸出端’並根據—選擇信號決;多工 =本發明—實施射,上述信號處理單从括—資料 子電路與_資料運算電路。f料儲存電路用以儲存雙緣 201041445 j〇689twf.d〇c/n 貧:傳遞單元所擷取的該資 路用以輪出驅動致能信號。 t 4運异電 Ο ο 與-第二資料儲存電路。第—資料:存;: 第二資:儲存資料輸入信號中之-影像資料, 中之物料輪入_ 在本發明一實施例中,上述資料 器與複數他㈣爾 儲存之資料輸入信“ '•動致此彳5 5虎至發光二極體驅動單元。 在本發明一實施例中,上述資料運管泰 閑的輸入分職接於資料物;與 。虎該二及_輸出_接於發光二極體驅動單元。 在本發明—實施例中,上述驅動電路更包括—偵測保 in’ Μ偵測發光二極體與驅動電路的狀態並輸出-:'1。號至資料傳遞單元,並可根據偵測結果提供保護功 月hi 虹欲在本發明—實施例中,上述發光二極體驅動單元更包 一發光二極體驅動電路與驅動信號設定電路。立中,發光 t極體驅動電_接於信號處理單元,根據驅動致能信號 ^出驅動錢轉紅述發光二極體。驅動信號設定電路 輕接於發光二極體驅動電路,用以調整發光二極體驅 路所輸出之驅動信號。 201041445 30689twf.doc/n 在本發明-實施例中,上述之雙緣擷取資 包緣暫存器、一資料輸入信號處理電路: 存所擷取之該資料輪入信號;資料輸人信 == 麵入:號並輸出同相或反相之該資料輸入信;;: 裔的輸入端分別轉接於雙緣觸發 輸入信號處理電路的輸出,客與資料 輸出端。 増出’夕工爾出端則耦接於資料 电々丨厘轉換電路與一溆你絲 路。數位類比轉換電_接於信號處理 電難生電路與數二i二:電流轉換電路_參考 驅動單元所輸出==換電路,用以調整發光二極體 -,ίί發明—實施例中’上述驅動電路更包括-控制單 兀耦接於雙緣擷取資料傳遞單元,用以德、、,二 資料輪入信號至雙緣擷取資料號與 與資料輸入信號產生控制信號專遞早凡。並糟由時序信號 發光本發明利用雙緣掏取資料傳遞單元來掘取 皆可觸^’由於時相號的上升緣與下降緣 相同取’因此在 至傳統技術的—半,並可降⑽ 201041445 306S9twf.doc/n 1ΞΪΓΓΕΜΙ)輯加純整翻狀,也簡化系_ 為讓本發明之上述特徵和優點能更明顯易懂, 舉貫施例,並配合所附圖式作詳細說明如下。 寺 【實施方式】 第一實施例201041445 30689twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a driving circuit for a light-emitting diode, and more particularly to a driving circuit having a double-edge triggering function. [Prior Art] Light Emitting Diode (LED) is small, power-saving and durable, and as the process matures, the price drops. Recently, products using light-emitting bodies as light sources are becoming more and more popular. In addition, 'light-emitting diodes have low operating voltage (only 1.5-3V), can actively emit light and have a certain brightness, and the brightness can be adjusted by voltage or current. At the same time, it has the characteristics of impact resistance, vibration resistance and long life (100,000 hours). Light-emitting diodes are widely used in a variety of terminal equipment, from automotive headlights, traffic lights, text displays, billboards and large-screen video displays, to general architectural lighting and LCD backlighting. In the conventional LED driving device, the data transmission is only accessed by using a single rising edge of the timing signal. The schematic diagram of the data sampling is shown in Figure i, and Figure 1 is a schematic diagram of data sampling according to the prior art. As shown in Figure i, the rising edge of the 'b-sequence k number CLK triggers the drive circuit to extract the data input signal DIN, and its sampling points (such as S1, S2) correspond to the rising edge of the timing signal cLK. However, as the application of the light-emitting diode has been widely used to display visual information such as patterns: images, in order to improve the change of the gray-scale driving of the light-emitting diode or increase the number of serial connections of the light-emitting diode driving device , so that the amount of data transmission per unit time of the transmitter=diode drive device is constantly increasing. 'Italian (4) The frequency of the order money must be continuously improved. The previous number of 201041445 30689twf.doc/n MHz level enhances the application of the ship in excess of 3GMHz. However, the operating frequency will increase the high frequency dry _ effect, resulting in = fixed, but also increase the difficulty of system design. The present invention provides a driving circuit for a light-emitting diode, which utilizes a method of extracting data to enter a signal, and uses a rising edge of the timing signal without adding an additional control signal. Touch with the falling edge to get twice the amount of feed. Under the same amount of data, the frequency of the timing signal of this is only half of that of the conventional LED driving method. The invention provides a driving circuit for a light emitting diode, comprising a double edge data transfer unit, a signal processing unit and a light emitting body driving unit. The dual-edge transmission receiving unit receives the timing signal input signal, and the double-edge trigger data transmission unit triggers the signal of the Qilong input by the timing rising edge and the falling edge, and records the ___ Lose money. The signal processing unit double-fetch data transmission unit is configured to store the data input signal captured by the double-edge data and input the C: drive enable signal according to the stored data. The LED driver unit is deactivated by the driving enable signal to rotate at least one gamma signal to drive the at least one LED. In the case of a month-to-month-perform, the above-mentioned double-edge data transfer unit packet and the edge trigger shift register. The pulse generates electricity and generates a pulse signal, wherein the pulse signal has a complex number 201041445 30689twf.doc/n first pulse and a plurality of second pulses 'the first pulse' corresponds to the rising edge of the timing ##, the pulse of the pulse The timing corresponds to the timing letter | the falling edge of the tiger. The single-edge trigger shift register samples data according to the pulse signal and sequentially stores the captured data input signal. In an embodiment of the invention, the dual-edge data acquisition unit includes a dual-edge trigger shift register, which is triggered by the rising edge and falling of the timing signal to sample the data input signal and sequentially Store the captured data input signal. In an embodiment of the invention, the driving circuit further includes a timing sounding unit for receiving the timing signal and outputting the in-phase or inversion phase. In an embodiment of the invention, the double-edge The data transfer unit includes a first double edge trigger shift register, a second double edge trigger shift register, a data input signal processing circuit, and a multiplexer. The first-double 4-touch, the shift register is used to store one image of the data input signal; the second double-edge trigger shift register is used to store the data input signal: the data; the data input The human signal processing power is connected to the f input signal for outputting the _ or the inverted data wheel human signal; the multiple H outputs = the end ^_ connected to the first-double edge trigger shift register, the second double The edge solution and the data input signal processing circuit are turned out, the multiplexed crying ^ is connected to a data output terminal 'and according to the selection signal; the multiplex = the invention - the implementation of the signal processing From the data-circuit sub-circuit and _ data operation circuit. The material storage circuit is used to store the double edge. 201041445 j〇689twf.d〇c/n Poverty: The resource captured by the transfer unit is used to turn the drive enable signal. t 4transelectric Ο ο and - second data storage circuit. The first data: the second asset: the storage data input signal - the image data, the material in the wheel _ In an embodiment of the invention, the data device and the plurality of (four) er stored data input letter " ' • In this embodiment of the present invention, the above-mentioned data is managed by the input of the data to the data object; and the tiger is the second and the output_ In the embodiment of the present invention, the driving circuit further includes: detecting the in' Μ detecting the state of the LED and the driving circuit and outputting the -: '1. to the data transfer unit In the present invention, in the embodiment, the LED driving unit further includes a light emitting diode driving circuit and a driving signal setting circuit. The body drive circuit is connected to the signal processing unit, and drives the money to the red light emitting diode according to the driving enable signal. The driving signal setting circuit is lightly connected to the light emitting diode driving circuit for adjusting the light emitting diode driving circuit. The output drive signal. 201041 445 30689twf.doc/n In the present invention-embodiment, the above-mentioned double edge acquisition packet edge register, a data input signal processing circuit: the data wheeled signal captured by the deposit; data input letter = = face-in: the number and output the data input signal in phase or inversion;;: the input end of the descent is transferred to the output of the double-edge trigger input signal processing circuit, the guest and the data output end. The end is coupled to the data electric conversion circuit and a silk circuit. The digital analog conversion is connected to the signal processing electric hard circuit and the number two i: the current conversion circuit _ reference drive unit output == change The circuit is used to adjust the light-emitting diode-, ίί invention-in the embodiment, the above-mentioned driving circuit further includes a control unit coupled to the double-edge data transmission unit for deriving the signal to the German, The double-edge acquisition data number and the data input signal generation control signal are delivered in advance. And the time-series signal illumination is used. The present invention utilizes the double-edge data acquisition unit to excavate both of the touches due to the rising edge of the phase number. The falling edge is the same as 'therefore Technical-half, and can be reduced (10) 201041445 306S9twf.doc/n 1ΞΪΓΓΕΜΙ) Adding purely tumbling, and simplifying the system _ In order to make the above features and advantages of the present invention more obvious and easy to understand, The drawings are described in detail below. Temple [Embodiment] First Embodiment

請參照圖2Α,圖2Α為根據本發明第—實施例 的驅動電路方塊圖。驅動電路200包括雙緣擷ς ^專遞單元训、信號處理單元挪以及發光二極體驅動 早7L 230。仏號處理早凡22〇耦接於雙緣擷取資料傳遞 几训與發光二極體驅動單元23〇之間,用來儲存雙 取貧料傳遞單元210所擷取的資料以及進行資料運算功 能。信號處理單元22G中會包括多組多位^ f料儲存^路 以進行資料儲存。其中,資料儲存電路則例如是資料检鎖 器,其位元數則是設計需求而定,本實施例並不受限。 L號處理單元220會儲存雙緣擷取資料傳遞單元 所擷取的資料輸入信號DIN並根據所儲存之資料輪入信號 DIN進行運算以輸出驅動致能信號至發光二極體驅動單^ 23〇。發光二極體驅動單元230會根據信號處理單元22〇Referring to Figure 2, Figure 2 is a block diagram of a driving circuit in accordance with a first embodiment of the present invention. The driving circuit 200 includes a double-edge 撷ς ^ special unit training, a signal processing unit shift, and a light-emitting diode driving early 7L 230. The nickname processing is coupled between the dual-edge data transmission and the light-emitting diode driving unit 23〇, and is used for storing the data acquired by the double-picked material transfer unit 210 and performing data calculation functions. . The signal processing unit 22G includes a plurality of sets of multi-bit storage devices for data storage. The data storage circuit is, for example, a data check locker, and the number of bits is determined by design requirements, and the embodiment is not limited. The L processing unit 220 stores the data input signal DIN captured by the double edge data transfer unit and operates according to the stored data wheel signal DIN to output the drive enable signal to the LED driver unit. . The LED driving unit 230 will be based on the signal processing unit 22〇

所輸出的驅動致能信號產生多個驅動信號(例如κ個,K 為正整數)以驅動發光二極體。發光二極體驅動單元23〇可 透過調整驅動電壓或電流來調整發光二極體的灰階度(亮 度)。 雙緣擷取資料傳遞單元210接收資料輸入信號DIN與 201041445 30689twf.doc/n 時序信號CKI,由時序信號CKI的上升緣盘 發以對資賤人㈣圓撕㈣轉並城尉3 2,本發明第-實施例之資料取樣時序;L 4 取^點S1〜S3表示雙緣擷取資料傳輸單元21G揭取資料 入化號的DIN的時間點。取樣點S1、 ^The output drive enable signal generates a plurality of drive signals (e.g., κ, K is a positive integer) to drive the light emitting diode. The light emitting diode driving unit 23 can adjust the gray scale (brightness) of the light emitting diode by adjusting the driving voltage or current. The double edge extraction data transfer unit 210 receives the data input signal DIN and the 201041445 30689twf.doc/n timing signal CKI, and is sent by the rising edge of the timing signal CKI to the capitalist (four) round torn (four) and the city 3 2, this The data sampling timing of the first embodiment of the invention; L 4 takes the points S1 to S3 to indicate the time point at which the double-edge data transmission unit 21G extracts the DIN of the data entry number. Sampling point S1, ^

=上升緣,取樣點S2即對應於時序信號 緣。由圖2B可知’在相同頻率的時序信號㈤下, =,?單元210會比單緣觸發的電路增加-倍:資 。讀需擷取的資料量相同,則其時序信號CK! =,可降低為習知時序信號的—半即可讓雙緣擷取資料 傳輸早元210擷取到所需的資料量。= rising edge, sampling point S2 corresponds to the timing signal edge. It can be seen from Fig. 2B that under the timing signal (5) of the same frequency, the unit 210 will increase by - times the circuit triggered by the single edge. If the amount of data to be read is the same, then the timing signal CK! = can be reduced to a half of the conventional timing signal, so that the double-edge data can be transmitted to the required data amount.

雙緣擷取貧料傳輸單元21〇的内部電路可直接利用雙 緣觸發移㈣辟來實現,也可__產生電路與單緣 =發^暫存器來實現。請參照3A,圖3A為根據本發明 弟μ施例之雙緣擷取資料傳輸單元的内部電路圖。雙緣 擷取資料傳輪單元训包括脈衝產生電 3暫存器⑽。脈衝產生電路32❻接於單緣 ,存器310,用以轉換所接收到的時序信號cki。脈衝產 ^電路320會根據時序信號CKI產生一脈衝信號,當時序 2號CKI由低準位轉恶為尚準位(即上升緣)或由高準位轉 怨為低準位(即下降緣),脈·生電路320均會產生一個 脈衝。 請參照圖3B,圖3B為根據本實施例之脈衝信號波型 10 201041445 30689twf.doc/nThe internal circuit of the double-edge squeezing material transfer unit 21〇 can be directly realized by using the double-edge trigger shift (4), or can be realized by the __ generating circuit and the single edge=transmitting register. Please refer to FIG. 3A. FIG. 3A is an internal circuit diagram of a dual-edge data transmission unit according to the embodiment of the present invention. The double-edge data-carrying unit training includes a pulse generating electric 3 register (10). The pulse generating circuit 32 is coupled to the single edge buffer 310 for converting the received timing signal cki. The pulse generating circuit 320 generates a pulse signal according to the timing signal CKI, when the timing No. 2 CKI is converted from the low level to the still level (ie, the rising edge) or the high level is turned to the low level (ie, the falling edge) ), the pulse generating circuit 320 generates a pulse. Please refer to FIG. 3B, which is a pulse signal waveform according to the embodiment. 10 201041445 30689twf.doc/n

Ο 圖。由圖3B可知,脈衝信號PUS會對應於時序信號cKI 的上升緣與下降緣產生對應的脈衝。其中,脈衝ρι的時 序即對應於時序信號CKI的上升緣,而脈衝P2的時庠' 對應於時序信號的下降緣。其中,值得注意的是== 號PUS中每一個脈衝的寬度會小於時序信號CKI的半個 週期,避免相鄰脈衝的波形產生重疊的情況。當時序信號 CKI中的時脈週期愈小時,所對應產生的脈衝寬度也必須 越小。 由於脈衝產生電路320可將時序信號CKI轉換為具有 兩,脈衝個數的脈衝信號PUS,@此不論單緣觸發移位暫 存器31 〇疋採用正緣觸發或負緣觸發的方式來擷取資料, ^可藉由_錢PUS _祕f觸取量的效果i在本 ^施例f ’單緣觸鄉㈣存器310是採用正緣觸發的方 二來進行擷取,因此在脈衝信號PUS中的每個脈衝的上升 料取樣的動作,其取樣時間與直接利用雙緣Ο Figure. As can be seen from FIG. 3B, the pulse signal PUS will generate a corresponding pulse corresponding to the rising edge and the falling edge of the timing signal cKI. The timing of the pulse ρι corresponds to the rising edge of the timing signal CKI, and the time 庠' of the pulse P2 corresponds to the falling edge of the timing signal. Among them, it is worth noting that the width of each pulse in the == PUS will be less than half the period of the timing signal CKI, avoiding the overlap of the waveforms of adjacent pulses. When the clock period in the timing signal CKI is smaller, the corresponding pulse width must also be smaller. Since the pulse generating circuit 320 can convert the timing signal CKI into a pulse signal PUS having two, the number of pulses, @this can be obtained by using a positive edge trigger or a negative edge trigger regardless of the single edge trigger shift register 31 The data, ^ can be obtained by the effect of the _ money PUS _ secret f touch amount i in this example f 'single edge touch (four) register 310 is using the positive edge trigger square two to extract, so in the pulse signal The action of the rising material sampling of each pulse in the PUS, the sampling time and the direct use of the double edge

:存盗來實現雙緣擷取資料傳遞單元.210的取樣時間 與賢料取樣率相同。 T ™ —由於發光二極體顯示器通常具有多個發光二極體,若 彻二動曰θ片不足以驅動所有發光二極體,通常會串接多 所接收進行驅動。此時,驅動晶片之間便需要傳遞 的力戈1的貪料輪入信號din以達到驅動多個發光二極體 入信號Dm#之後,錢€路設定將資料輸 傳遞至下一級的驅動電路。雙緣擷取資料傳遞 201041445 30689twf.doc/n 早几21G在貝抖輪出蠕所輸出的信號稱 DO,其中資料輸出信,加心㈣十f^貝㈣出疲 咕削} M h £ΙΧ) 了為那或反相的資料輸入信 m 將雙緣擷取資料傳遞單元2ig所操取 動電路200也可以輸出同相或反相之時 序信號CKI。 第二實施例: Sampling to achieve the dual-edge data transfer unit. 210 sampling time and the same sampling rate. T TM — Since a light-emitting diode display usually has a plurality of light-emitting diodes, if the two-way θ θ sheets are insufficient to drive all of the light-emitting diodes, a plurality of receptions are usually driven in series. At this time, after the driving wafers need to transmit the greedy wheeling signal din of the force 1 to drive the plurality of LED input signals Dm#, the money path is set to transfer the data to the driving circuit of the next stage. . Double-edge data transmission 201041445 30689twf.doc/n The signal outputted by the 21G in the morning vibrating wheel is called DO, and the data output letter, the heart (4) ten f ^ shell (four) out of fatigue} M h £ΙΧ The input circuit m for the or inverted data input circuit 200 can also output the in-phase or inverted timing signal CKI. Second embodiment

關於”信號_的傳遞請參照圖4,圖4為根 據本發明第二貫施例的驅動電路。驅動電路彻 擷取資W«單元4丨0、信祕料元42()、發光二極ς驅 動單元樣、時序處理單元糊、偵測保護單元側以及控 制單元460。其中,信號處理單元42〇包括 421與資料運算電路422,而發光二極體驅動單元43〇包括 發光二極體驅動電路432與驅動信號設定電路47〇。雙緣 擷取資料傳遞單元41〇則包括雙緣擷取移位暫存電路 413、資料輸入信號處理電路415與多工器417。多工器417Please refer to FIG. 4 for the transmission of the "signal_". FIG. 4 is a driving circuit according to a second embodiment of the present invention. The driving circuit thoroughly draws the W« unit 4丨0, the secret element 42 (), and the light emitting diode. The driving unit, the timing processing unit paste, the detection protection unit side, and the control unit 460. The signal processing unit 42 includes a 421 and data operation circuit 422, and the LED driving unit 43 includes a LED driver. The circuit 432 and the drive signal setting circuit 47. The double edge data transfer unit 41 includes a double edge capture shift register circuit 413, a data input signal processing circuit 415 and a multiplexer 417. The multiplexer 417

的輸入端分別耦接於雙緣擷取移位暫存電路413與資料輸 入信號處理電路415的輸出,多工器417的輸出耗接於驅 動電路400的 > 料輸出端’並根據控制單元460所輪出的 選擇信號SEL選擇雙緣擷取移位暫存電路413與資料輸入 信號處理電路415其中之一的輸出以產生資料輸出信號 DO。 資料輸入信號處理電路415可依據設定輸出正相或反 相的資料輸入信號DIN,當輸出反相的資料輸入信號DIN 時,可有效降低資料輸入信號DIN在傳遞時的衰減問題。 12 201041445 30689twf.doc/n 讓資料輸入信號DIN在經過數級的驅動電路傳遞後,依然 保持資料輸入信號DIN的脈衝寬度與其波形。時序處理單 元440則是用來傳遞時序信號CKI,可依據設定輸出正相 或反相之時序信號cki以產生時序輸出信號CK〇。同樣 地,當輸出反相之時序信號CKI時,可有效降低時序信號 cki在傳遞時的衰減問題。讓時序信號CKI在經過數級的The input ends are respectively coupled to the outputs of the dual-edge capture shift register circuit 413 and the data input signal processing circuit 415, and the output of the multiplexer 417 is consumed by the > material output terminal of the drive circuit 400 and according to the control unit The selection signal SEL rotated by 460 selects the output of one of the double-edge capture shift register circuit 413 and the data input signal processing circuit 415 to generate the data output signal DO. The data input signal processing circuit 415 can output the positive or negative phase data input signal DIN according to the setting. When the inverted data input signal DIN is output, the attenuation problem of the data input signal DIN during transmission can be effectively reduced. 12 201041445 30689twf.doc/n After the data input signal DIN is transmitted through the drive circuit of several stages, the pulse width of the data input signal DIN and its waveform are still maintained. The timing processing unit 440 is configured to transmit a timing signal CKI, and may output a timing signal cki of a positive phase or an inverted phase according to the setting to generate a timing output signal CK〇. Similarly, when the inverted timing signal CKI is output, the attenuation problem of the timing signal cki at the time of transmission can be effectively reduced. Let the timing signal CKI go through several levels

Ο 驅動電路傳雜,健料時序㈣CKI的脈衝寬度與其 波形。 '、'、 田於製程的變異 …,成驅動電路在傳遞信號時有上 升緣時間與下降緣_的差異,因轉由將錢反相後再 進订傳遞’可有㈣除因上升料間與下降緣時間的差異 所造成的信號衰減或失真等問題。 “ 此外,在電路結構中’時序處理單元相可以直接耗 f於,信號CKI與時脈輸出端之間,用來傳遞 相的訏序信號CKI至下一級的驅動 - 性的將資料輸人信號din與時=號= 級的驅動電路或者透過資料輸出端 ==出驅動電路__部絲值給线以進行^ 移位暫存電路4丨3則可由雙緣移位暫存 、,且成或由早緣移位暫存哭盘 。σ厅 (如圖3所示)。雙‘ CKI , 料輸入信號疆進行資料取樣並且依;儲存 13 201041445 30689twf.doc/n 輸入信號DIN。 資料儲存電路421輕接於資料運算電路422與雙緣擷 取移位暫存電路413之間,並根據控制單元46〇所輸出的 栓鎖彳s號LAT拴鎖雙緣擷取移位暫存電路413中所暫存的 資料,然後傳送至資料運算電路422進行運算。資料運算 電路422根據所擷取之資料輸入信號din輸出驅動致能信 號至發光二極體動電路432以輸出對應的驅動信號。其 中,資料運算電路422可由及閘或數位比較器所組成,但 本發明並不限制於此。在本實施例中,發光二極體驅動電 路輸出K個驅動信號,κ為正整數。 發光一極體驅動單元43〇主要由發光二極體驅動電路 432與驅動仏號設定電路47〇所組成,驅動信號設定電路 470耦接於發光二極體驅動電路432,其中驅動信號設定電 =47〇主要是用來設定發光二極體驅動電路432的驅動電 =%壓或有效致能時間(duty cyCie)的大小。驅動信號設 =電路470同樣可根據驅動電路4〇〇所接收到的資料輪入 號DIN設定所需的參數以調整發光二極體驅動電路432 所輪出的驅動信號。驅動信號設定電路470可直接經由雙 ^取資料傳遞單元接收所需的命令資料或是經由控 單元460接收不同的工作模式調整信號MODE。 控制單元460耦接於雙緣擷取資料傳遞單元410、資 存電路421與偵測保護單元450。控制單元460可根 貝料輸入信號DIN與時序信號CKI的波形組合或所傳遞 、數據資料輪出拴鎖信號LAT、工作模式信號MODE與 14 201041445 30689twf.doc/n 選擇信號SEL等控制信號或參數設定信號。此外,當資料 輸入信號DIN與時序信號CKI係為編碼後之資料時,控制 單元460也可以用來對資料輸入信號DIN與時序信號CKI 進行解碼’然後再將解碼後之資料輸入信號DIN與時序信 號CKI傳遞至雙緣擷取資料傳遞單元410。 田%驅動電路400可具有多種驅動模式’或是多種調 ΟΟ Drive circuit transmission, health timing (4) CKI pulse width and its waveform. ', ', the variation of the process in the process..., the drive circuit has a difference between the rising edge time and the falling edge _ when transmitting the signal, because the transfer is reversed by the money and then the order is passed. 'There is a Problems such as signal attenuation or distortion caused by the difference in falling edge time. "In addition, in the circuit structure, the timing processing unit phase can directly consume the signal CKI and the clock output terminal, which is used to transmit the phase sequence signal CKI to the next stage of the drive-type data input signal. Din and time = number = level of the drive circuit or through the data output terminal == drive circuit __ wire value to the line to ^ shift register circuit 4 丨 3 can be temporarily stored by double edge, and Or by the early margin shift temporary storage crying disk. σ hall (as shown in Figure 3). Double 'CKI, material input signal Xinjiang data sampling and depend on; storage 13 201041445 30689twf.doc / n input signal DIN. Data storage circuit 421 is lightly connected between the data operation circuit 422 and the double edge capture shift register circuit 413, and is captured in the shift temporary storage circuit 413 according to the latch 彳s number LAT latched by the control unit 46〇. The temporarily stored data is then transferred to the data operation circuit 422 for calculation. The data operation circuit 422 outputs a drive enable signal to the LED body circuit 432 according to the extracted data input signal din to output a corresponding drive signal. , the data operation circuit 422 can be gated The digital comparator is composed of a digital comparator, but the present invention is not limited thereto. In the embodiment, the LED driving circuit outputs K driving signals, and κ is a positive integer. The light emitting body driving unit 43 is mainly composed of two light emitting diodes. The driving circuit setting circuit 470 is coupled to the driving diode setting circuit 432. The driving signal setting circuit 470 is coupled to the LED driving circuit 432. The driving signal setting voltage=47〇 is mainly used to set the LED driving. The driving power of the circuit 432 = the value of the % voltage or the effective enabling time (duty cyCie). The driving signal setting circuit 470 can also adjust the required parameters according to the data wheel number DIN received by the driving circuit 4 以 to adjust The driving signal set by the LED driving circuit 432. The driving signal setting circuit 470 can directly receive the required command data via the data receiving unit or receive the different working mode adjustment signal MODE via the control unit 460. The unit 460 is coupled to the dual edge data transfer unit 410, the resource storage circuit 421, and the detection protection unit 450. The control unit 460 can input the signal DIN and the timing signal CK. I waveform combination or transmission, data data rotation yoke signal LAT, operation mode signal MODE and 14 201041445 30689twf.doc/n selection signal SEL and other control signals or parameter setting signals. In addition, when the data input signal DIN and timing signals When the CKI is the encoded data, the control unit 460 can also be used to decode the data input signal DIN and the timing signal CKI. Then, the decoded data input signal DIN and the timing signal CKI are transmitted to the double edge data transmission. Unit 410. The field % drive circuit 400 can have multiple drive modes or multiple adjustments.

整參數值。控制單元460可直接經由資料輸入信號DIN與 #序彳σ號CKI來決定其參數值。換句話說’資料輸入信號 DIN包括影像資料與命令資料’影像資料用以決定發光二 極體的灰階值’而命令資料則是用來設定驅動電路4〇〇中 的f數值。控制單元46〇可根據資料輸入信號DIN中的命 令㈣輸城妓枝號M〇DE _整侧賴單元45〇 的工作模式以偵測不同的電路參數與環境狀態值。 馈測保護單元45〇可依照工作模式信號m〇de來 路的㈣狀態,例如溫度、電壓、電流、電路是否 二1態’以及發光二極體的狀態,例如開路、短路、 化程度等。偵測保護單元·中可增設—般電路 調整2=,與_功能以進行電路狀態監控與即時 膽值仲注意的是,偵測保護單元45 = 設定的參數進行電路價測貞電路 …又叶者所 麗保護等’同時偵測保護單元450可透二護或過 ίίί:广―號接聊輸二 料傳 接下來,進一步以8位元的顧動電路為例說明本發明 15 201041445 30689twf.doc/n 之驅動電路。請參昭圖< 之驅動電路圖。驅動電路遍本:明第三實 存器510、8位元資料儲存電路521兀又緣擷取移位嘴 522、發光二極體驅動單 〇 位元資料運异電路 530包括發光二極體驅 j中發光二極體驅動單元 570。8位元資料運算電 與驅動信號設定電路 53〇與8位元資料儲存電 於發光二極體驅動單元 切的另一側位元資料儲存電路The entire parameter value. The control unit 460 can determine its parameter value directly via the data input signal DIN and the #序彳σ number CKI. In other words, the data input signal DIN includes image data and command data 'image data is used to determine the gray scale value of the light-emitting diode' and the command data is used to set the f value in the drive circuit 4'. The control unit 46 can detect different circuit parameters and environmental state values according to the command in the data input signal DIN (4), the operation mode of the 妓 妓 M 〇 _ _ _ _ _ _ _ _ _ _ _ The feed protection unit 45 can be in accordance with the (four) state of the operating mode signal m〇de, such as temperature, voltage, current, whether the circuit is in a state of two or the state of the light emitting diode, such as an open circuit, a short circuit, a degree of oxidation, and the like. Detection protection unit · can be added - general circuit adjustment 2 =, and _ function for circuit status monitoring and immediate biliary attention, detection protection unit 45 = set parameters for circuit price measurement circuit... The protection of the protection unit, etc. 'simultaneous detection protection unit 450 can be through the second protection or over ί ί ί: 广 接 接 输 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来 接下来Doc/n drive circuit. Please refer to the drive circuit diagram of the map. The driving circuit is ubiquitously: the third real memory 510, the 8-bit data storage circuit 521, the edge-moving shifting nozzle 522, the light-emitting diode driving single-bit data-transporting circuit 530 including the light-emitting diode drive The light-emitting diode driving unit 570 in the j. The 8-bit data operation and driving signal setting circuit 53 and the 8-bit data are stored in the other side bit data storage circuit of the LED driving unit.

得注意的是,發光二極體驅動魏432=m^510。值 二極體驅動電路以輪出8個驅動㈣。°括8個發光 8位元資料儲存電路姑U 資料減/ 胃根據栓鎖信號LAT來進行 貝枓栓鎖以儲存8位元雙缘擷取移位: ,資料運算電路522由多個及心:== ===N與編存電路521所輪出= 儲;I·:% 522根據8位凡資料儲存電路521所 ϋ 2的貢料與致能信號ΕΝ分別決定發光二極體驅動電路 2是否航轉出驅動信號。本實施财,雖以8位元 為例來說明8位元雙緣擷取移位暫存器51()以及8位 料儲存電路5巧,然而上述電路結構並不受限於8位元,、 也可適狀更高或更低位元的電路結構。值·意的是, 检鎖信,LAT與致能信號EN可由控制單元輸出^外部輸 入,本實施例並不受限。關於驅動電路5〇〇的其餘構件盘 其操作方式參照上述圖4實施例中說明,在此^加累述' 第四實施例 16 201041445 3〇689twf.doc/n 由於= 貧料輸入信號可以包含多種資料’包括影像資料 與设定工作模式用的命令資料,因此上述轉電路中之錐 緣棟取貧料傳遞單元與信號處理單元亦可對應設置兩^ 料儲存電路。請參關6,s 6為根據本發明第四實施例 之驅動電路®。驅動電路_包括雙緣擷取資料傳遞It should be noted that the light-emitting diode drives Wei 432=m^510. The value of the diode drive circuit is to rotate 8 drives (four). ° 8 light-emitting 8-bit data storage circuit U / data subtraction / stomach according to the latch signal LAT to perform the Bellows lock to store the 8-bit double edge capture shift: , the data operation circuit 522 from multiple hearts :== ===N and the storage circuit 521 is rotated = stored; I·:% 522 according to the 8-bit data storage circuit 521 的 2 tribute and enable signal ΕΝ respectively determine the LED driving circuit 2 Whether to transfer the drive signal. In this implementation, although the 8-bit is used as an example to illustrate the 8-bit dual-edge capture shift register 51() and the 8-bit material storage circuit 5, the above circuit structure is not limited to 8-bit. It is also possible to adapt the circuit structure of higher or lower bits. The value means that the lock letter, the LAT and the enable signal EN can be output by the control unit, and the present embodiment is not limited. Regarding the operation mode of the remaining component disk of the driving circuit 5A, reference is made to the above description of the embodiment of FIG. 4, and the following description is repeated. Fourth Embodiment 16 201041445 3〇689twf.doc/n Since the = lean input signal can be included A variety of materials 'including image data and command data for setting the working mode, so the taper edge of the above-mentioned circuit can also be set to two storage circuits corresponding to the lean material transfer unit and the signal processing unit. Please refer to Fig. 6, s 6 is a driving circuit® according to a fourth embodiment of the present invention. Drive circuit _ including double edge data transfer

Ο 資料儲存電路621、資料運算電路622、發光二極體 =早元630、時序處理單元_、偵測保護單元65〇、控 制早兀660以及電源管理系統68〇。 工 雙緣擷取資料傳遞單元_包括雙緣觸發移位暫存界 =3、614 H 617以及資料輸人信號處理電路615。 夕工器617的三個輸人端分接於雙緣觸發移位暫存哭 與,輸入信號處理電路615,其控制端減^ 工fJ早兀660’夕工斋617的輸出端則耦接於驅動電路6⑻ 的資料輸出端以輸出資料輸出信號D〇。其中,資料輸入 信號處理電路615可透過多工器617將資料輸入信號 的同相或反相傳送至驅動電路6〇〇的資料輸出端。 控制單元660根據時序信號CKI分別輸出時序信號 ’、cki2以及資料輪人信號DIN i雙緣觸發移位暫存 器/13、614。雙緣觸發移位暫存器613、614會根據時序 ^號αα!、cKi2擷取資料輸入信號疆並依序傳遞出所 擷取資料的資.控制單元_也會將資料輸人信號丽 輸出至資料輸入處理電路615,資料輸入處理電路615可 輪出=相或反相的資料輪入信號DIN。控制單元66〇利用 選擇信號S E L城多卫器6丨7來選擇性切換所欲輸出的資 17 201041445 306E9twf.doc/n 料輸出信號DO。 雙,2㈣存器613、614皆是屬於雙緣觸發的 暫存斋,可由時序信號CKli、卿❺上升緣與下 ,觸發以進行f料取樣。在本實施射,雙緣觸發移= 存器613例如是]^個12位元的雙緣觸發移位暫存器, 發暫存器614則例如是7位元的雙緣觸發移位 暫子咨ΊΜ為正整數,表示驅動信號的個數。值 〇 意的是,時序信號CKIl、CKl2可由控制單元66 · 序信號CKI產生。 骤知 匕序處理單元_與上述實關朗,主要用來傳 時序信號CKI以產生時序輸出信號CK〇。配合資出 U虎DO與Βτ序輸出信號CK〇,驅動電路刪可輪出 =部的狀態值或將龍輸人信號顧㈣序信號cki傳遞 級的驅動電路。時序處理單^ _的操作方式盘前 述貫施例相同,在此不加累述。 、 〇 資料儲存電路⑵與資料運算電路622則組成信號處 早凡,_於雙賴取資料傳遞單元61G與發光二極體 =單元630之間。資料儲存電路621中尚包括第一“ ,存電路623與第二資料儲存魏。第一資料儲存電 ΤΔ^23與第二資料儲存電路624可分別根據栓鎖信號 LATl、LAI栓鎖雙緣觸發移位暫存器6ΐ3、614所擷取的 =料^如影像資料或命令資料)。第―f料儲存電路⑵ 旅M個12位元的資料儲存電路以對應儲存雙緣觸 天夕位暫存Is 6!3所擷取的資料。第二資料儲存電路· 18 201041445 30689twf.doc/n 智的貧料儲存電路以對應儲存雙緣觸發移位 „ 6Η所擷取的資料。值得注意的是,栓鎖信號 ,、LAT2可由控制單元働產生,但不受限於由控制 早兀_產生,亦可由外界(前端電路或系統)提供。 貢料運算電路622包括計數器杨與複數個比較器 秦叫例如數位比較器),比較器视〜43z用來比較^ ΟΟ Data storage circuit 621, data operation circuit 622, light-emitting diode = early 630, timing processing unit _, detection protection unit 65 〇, control early 660, and power management system 68 〇. The data acquisition unit _ includes a dual edge trigger shift temporary sector = 3, 614 H 617 and a data input signal processing circuit 615. The three input ends of the yoke 617 are tapped on the double-edge trigger shift temporary crying, and the input signal processing circuit 615 is controlled by the control end of the fJ 兀 660 夕 夕 斋 617 output is coupled At the data output end of the drive circuit 6 (8), a signal D is outputted as an output data. The data input signal processing circuit 615 can transmit the data input signal in phase or inversion to the data output terminal of the driving circuit 6 through the multiplexer 617. The control unit 660 outputs the timing signals '', cki2, and the data wheel human signal DIN i double-edge trigger shift register/13, 614, respectively, based on the timing signal CKI. The dual-edge trigger shift register 613, 614 will extract the data input signal according to the sequence number ^α!, cKi2 and sequentially transmit the extracted data. The control unit _ will also output the data input signal to The data input processing circuit 615, the data input processing circuit 615 can rotate the data in/out phase or inversion signal DIN. The control unit 66 uses the selection signal S E L City Multi-Guard 6丨7 to selectively switch the output signal DO to be output. The double and 2 (four) registers 613 and 614 are all temporary storages belonging to the double-edge trigger, and can be triggered by the timing signal CKli, the rising edge and the lower edge of the signal. In the present embodiment, the dual-edge trigger shift register 613 is, for example, a 12-bit dual-edge trigger shift register, and the register 614 is, for example, a 7-bit dual-edge trigger shift temporary. The consultation is a positive integer indicating the number of drive signals. The value is that the timing signals CKI1, CK12 can be generated by the control unit 66, the sequence signal CKI. It is known that the processing unit _ and the above-mentioned real-time processing are mainly used to transmit the timing signal CKI to generate the timing output signal CK〇. With the joint venture out U Tiger DO and Βτ sequence output signal CK 〇, the drive circuit can delete the state value of the = part or the driver circuit of the relay signal (four) sequence signal cki transmission stage. The operation mode of the sequence processing unit ^ _ is the same as that of the previous embodiment, and will not be described here. 〇 The data storage circuit (2) and the data operation circuit 622 constitute a signal, which is between the data transmission unit 61G and the light-emitting diode = unit 630. The data storage circuit 621 further includes a first "memory circuit 623 and a second data storage device. The first data storage device Δ^23 and the second data storage circuit 624 can be triggered by the double-edge according to the latch signals LAT1 and LAI, respectively. The shift register 6 ΐ 3, 614 reads = material ^ such as image data or command data). The first - f material storage circuit (2) travel M 12-bit data storage circuit to correspond to the storage of double-edge touch Save the data picked up by Is 6! 3. The second data storage circuit · 18 201041445 30689twf.doc / n Smart poor storage circuit to correspond to the storage of double edge trigger shift „ 6Η captured data. It is worth noting that the latch signal, LAT2, can be generated by the control unit, but is not limited to being generated by the control, but also by the outside (front-end circuit or system). The tributary operation circuit 622 includes a counter yang and a plurality of comparators, such as a digital comparator, and the comparator ~43z is used to compare ^ Ο

的輪出與第一資料儲存電路奶中所检鎖的資料, j據=致能發光二極體驅動單元630是否輸出Μ個驅動 =。貧料運算電路M2藉由計數器咖與複數個比較器 ^來細影像㈣的運算,其功能可視為—脈波寬 又調I:單元(pUlse width m〇dulati〇n肪⑴,用以調整發光二 3驅動單S63G所接收到的脈波寬度調整信號。同時也 二致能發光二極體驅動單元63〇是否輸出驅動信號的功 月b 0 驅動信號奴電路67〇包括數位類比轉換電路奶、 j電壓魅電路674叹钱職電路π6。參考 μ-生電路674耦接於電壓電流轉換電路676,數位類 、電路672耗接於資料错存電路a4與電壓電流轉換 雪676之間。數位類比轉換電路π2將儲存在資料儲存 5带,24、中的命令貢料轉換為類比信號(例如電壓)以輸出 電流轉換電路676 ’衫電流轉換電路676則根據 二料與餐考電驗生電路674的輸出調整發光二極體 驅動笔路632的驅動信號。 此外’值付注意的是’上述雙緣擷取資料傳遞單元 19 201041445 30689twf.doc/n 610、資料儲存電路621與資料運算電路幻^中的元件可依 照不^的使用需求設計為不同位元的電子元件,其傳輸路 徑與資料傳輸方式也依照所需的資料位元數進行調整,本 發明並不,限於上述實施例所述之位元數。此外,上述資 料輸入錢DIN的麵可以是—般賴錢或是差動信 號,本實施例並不受限。 電源管理系統680主要用來管理驅動電路6〇〇的電源 供給,其例如為調變式電源管理系統p〇wer ma皿ger)或線性電源管理系統(Unearpowermanager)。控 制單元660可依照所接收的資料輸入信號mN與時序信號 CKI的組合取得—卫作模式資料,並據此輸出—工作模式 信號MODE至债測保護單元65〇以進行工作模式的切換或 參數設定或電路狀態制。侧賴單元㈣可將所偵測 到的參數值贿到雙賴取資料傳遞單元⑽,、 資料輪出信號DO輸出。 請過 此外,值得注意的是,時脈輸出信號(:艮〇與The data of the lock detected in the milk of the first data storage circuit, j = whether the light-emitting diode driving unit 630 outputs one drive =. The poor material operation circuit M2 uses the counter coffee and a plurality of comparators to perform the operation of the fine image (4), and its function can be regarded as: pulse width and I: unit (pUlse width m〇dulati〇n fat (1), used to adjust the light The second 3 drives the pulse width adjustment signal received by the single S63G. At the same time, the dimming diode driving unit 63 输出 outputs the driving signal of the power month b 0 driving signal slave circuit 67 〇 including the digital analog conversion circuit milk, j voltage enchant circuit 674 sighs the money circuit π6. The reference μ-sheng circuit 674 is coupled to the voltage-current conversion circuit 676, the digital class, the circuit 672 is consumed between the data error circuit a4 and the voltage-current conversion snow 676. Digital analogy The conversion circuit π2 converts the command material stored in the data storage 5 band, 24, into an analog signal (for example, voltage) to output the current conversion circuit 676. The shirt current conversion circuit 676 is based on the second material and the meal test circuit 674. The output adjusts the driving signal of the LED driving pen path 632. In addition, the value of the above-mentioned double-edge data transmission unit 19 201041445 30689twf.doc/n 610, the data storage circuit 621 and The components in the material computing circuit can be designed as electronic components of different bits according to the requirements of use, and the transmission path and the data transmission mode are also adjusted according to the required number of data bits. The present invention is not limited to the above. The number of bits described in the embodiment. In addition, the face of the data input DIN can be a general money or a differential signal, and the embodiment is not limited. The power management system 680 is mainly used to manage the driving circuit 6〇. The power supply of the crucible is, for example, a modulated power management system or a linear power management system (Unearpowermanager). The control unit 660 can obtain the security mode data according to the combination of the received data input signal mN and the timing signal CKI, and output the working mode signal MODE to the debt testing protection unit 65〇 to perform the switching or parameter setting of the working mode. Or circuit state system. The side unit (4) can bribe the detected parameter value to the data transfer unit (10), and the data output signal DO output. Please, in addition, it is worth noting that the clock output signal (: 艮〇

依照參數設定為輸出同相的時序信號CKI ‘ 貝;斗輪入k號DIN或是輪出反相的時序信紅KI 二=外’若資料輸入信號_與資料輸出信‘ 而進仃編解碼,控制單元660中也可加設解碼 動電路600的輸出端可以加設編碼器以進行資料的編 圖^中所述的驅動電路的其餘電路操作細節則如 迷弟二實施例所述,在此不在累述。 接下來,請參照圖7、圖7為根據本發明第四實施例 20 201041445 30689twf.doc/nAccording to the parameter setting, the output phase in-phase timing signal CKI 'Bei; the bucket wheel enters the k-number DIN or the round-trip inversion timing letter KI 2 = outside 'if the data input signal _ and the data output letter' enters the codec, The output of the decoding circuit 600 can also be added to the control unit 660. The encoder can be added to encode the data. The remaining circuit operation details of the driving circuit are as described in the second embodiment. Not being told. Next, please refer to FIG. 7 and FIG. 7 as a fourth embodiment according to the present invention. 20 201041445 30689twf.doc/n

〇 之資料輸出信號波形圖。以12位元的影像資料與8個驅動 信號(發光二極體驅動電路630可輸出8個的驅動信號)為 例,當驅動電路600依序輸出雙緣擷取移位暫存電路613 中所擷取的資料時,資料輸出信號DO會比資料輸入信號 DIN延遲96個位元的時間。由於雙緣擷取移位暫存電路^ 613是以雙緣觸發的方式進行資料取樣,因此雙緣揭取移 位暫存電路613僅需48個週期的時序信號CKI即可完成 96個位元資料的取樣。 & 综上所述,本發明所提出的發光二極體驅動電路由於 具有雙緣觸發的擷取電路,因此可以較低頻率的時序信號 來進行資料存取,藉此可降低高頻信號對驅動電路的電磁 干擾以及增加驅動電路的穩定度。 雖然本發明已以實施例揭露如上,然其並非用以限定 本發明,任何所屬技術領域中具有通常知識者,在不脫離 本發明之精神和範#可作些許之更動與潤飾,故 ,明之保護翻當視後社巾請專職圍所 【圖式簡單說明】 可马旱 圖1為根據習知技術之資料取樣示意圖。 電路=為根據本發明第—實施㈣光二極體的驅動 圖2B為根據本發明第一實施例之資料取樣時序示意 圖3A為根據本發明第一 單元的内部電路圖。 實施例之雙緣擷取資料傳輸 201041445 30689twf.doc/n 圖3B為根據本實施例之脈衝信號波型圖。 圖4為根據本發明第二實施例的驅動電路。 圖5為根據本發明第三實施例之驅動電路圖。 圖6為根據本發明第四實施例之驅動電路圖。 圖7為根據本發明第四實施例之資料輸出信號波形 圖。 【主要元件符號說明】 200、400、500、600 :驅動電路 210、410、610 :雙緣擷取資料傳遞單元 220、420 :信號處理單元 230、430、530、630 :發光二極體驅動單元 440、640 :時序處理單元 310 :單緣觸發移位暫存器 320 :脈衝產生電路 413 :雙緣擷取移位暫存電路 415、615 :資料輸入信號處理電路 417、617 :多工器 421、 621 :資料儲存電路 422、 622 :資料運算電路 432、532、632 :發光二極體驅動電路 450、650 :偵測保護單元 460、660 :控制單元 470、570、670 :驅動信號設定電路 510 : 8位元雙緣擷取移位暫存器 22 201041445 30689twf.doc/n 521 : 8位元資料儲存電路 522 : 8位元資料運算電路 613、614 :雙緣觸發移位暫存器 623 :第一資料儲存電路 624 :第二資料儲存電路 672 :數位類比轉換電路 674 :參考電壓產生電路 676 :電壓電流轉換電路 680 :電源管理系統 CLK、CKI、CKL、CKI2 :時序信號 CKO :時序輸出信號 DIN :資料輸入信號 DO :資料輸出信號 EN :致能信號 LAT、LATi、LAT2 :栓鎖信號 MODE :工作模式信號 PUS :脈衝信號 PI、P2 :脈衝 S1〜S3 :取樣點 SEL :選擇信號 43b〜43z :比較器 43a :計數器 23资料 Data output signal waveform diagram. Taking 12-bit image data and 8 driving signals (the LED driving circuit 630 can output 8 driving signals) as an example, when the driving circuit 600 sequentially outputs the double-edge capture shift register circuit 613 When the data is retrieved, the data output signal DO is delayed by 96 bits from the data input signal DIN. Since the dual-edge capture shift register circuit 613 performs data sampling in the manner of double-edge triggering, the double-edge stripping shift register circuit 613 only needs 48 cycles of the timing signal CKI to complete 96 bits. Sampling of data. In summary, the LED driving circuit of the present invention has a dual-edge triggering circuit, so that data access can be performed with a lower frequency timing signal, thereby reducing the high frequency signal pair. Electromagnetic interference of the drive circuit and increase the stability of the drive circuit. The present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. Any person having ordinary knowledge in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. After looking at the social towel, please take a full-time office. [Simple description of the map] Figure 1 shows the sampling of the data according to the conventional technology. Circuit = is the driving of the photodiode according to the first embodiment of the present invention. Fig. 2B is a schematic diagram showing the sampling timing of the data according to the first embodiment of the present invention. Fig. 3A is an internal circuit diagram of the first unit according to the present invention. Double Edge Data Transfer of Embodiments 201041445 30689twf.doc/n FIG. 3B is a waveform diagram of a pulse signal according to the present embodiment. 4 is a driving circuit in accordance with a second embodiment of the present invention. Figure 5 is a diagram showing a driving circuit in accordance with a third embodiment of the present invention. Figure 6 is a diagram showing a driving circuit in accordance with a fourth embodiment of the present invention. Figure 7 is a waveform diagram of a data output signal in accordance with a fourth embodiment of the present invention. [Main component symbol description] 200, 400, 500, 600: drive circuit 210, 410, 610: double edge data transfer unit 220, 420: signal processing unit 230, 430, 530, 630: light emitting diode drive unit 440, 640: timing processing unit 310: single-edge trigger shift register 320: pulse generation circuit 413: double edge capture shift temporary storage circuit 415, 615: data input signal processing circuit 417, 617: multiplexer 421 621: data storage circuits 422, 622: data operation circuits 432, 532, 632: light-emitting diode drive circuits 450, 650: detection protection units 460, 660: control units 470, 570, 670: drive signal setting circuit 510 : 8-bit dual-edge capture shift register 22 201041445 30689twf.doc/n 521 : 8-bit data storage circuit 522: 8-bit data operation circuit 613, 614: double-edge trigger shift register 623: First data storage circuit 624: second data storage circuit 672: digital analog conversion circuit 674: reference voltage generation circuit 676: voltage current conversion circuit 680: power management system CLK, CKI, CKL, CKI2: timing signal CKO: timing output signal DIN: capital Material input signal DO: data output signal EN: enable signal LAT, LATi, LAT2: latch signal MODE: operation mode signal PUS: pulse signal PI, P2: pulse S1~S3: sampling point SEL: selection signal 43b~43z: Comparator 43a: counter 23

Claims (1)

201041445 30689twf.doc/n 七、申請專利範園: L —種發光二極體的驅動電路’包括: 一雙緣擷取資料傳遞單元,接收一時序信號與一資料 輸入信號’該雙緣擷取資料傳遞單元係由該時序信號的上 升緣與下降緣進行觸發以對該資料輸入信號進行資料取樣 並且依序儲存所操取之該貧料輸入信號, 一信號處理單元,耦接於該雙緣擷取資料傳遞單元, 用以儲存該雙緣擷取資料傳遞單元所擷取的該資料輸入信 號並根據所儲存之該資料輸入信號輸出一驅動致能信號; 以及 一發光二極體驅動單元,耦接於該信號處理單元,並 根據該驅動致能信號輸出至少一個驅動信號以驅動至少— 個發光二極體。 2.如申請專利範圍第1項所述之驅動電路,其中該雙 緣擷取資料傳遞單元包括: 一脈衝產生電路,根據該時序信號產生一脈衝信號, 其中該脈衝信號具有複數個第一脈衝與複數個第二脈衝, 該些第一脈衝的時序對應於該時序信號的上升緣,該些第 二脈衝的時序對應於該時序信號的下降緣;以及 一單緣觸發移位暫存器,根據該脈衝信號對該資料輸 入信號進行資料取樣並且依序儲存所擷取之該資料輸入信 號。 3.如申請專利範圍第1項所述之驅動電路,其中該雙 缘擷取資料傳遞單元包括: 24 201041445 30689twf,doc/n 一雙緣觸發移位暫存器,由該時序信號的上升緣與下 降緣進行觸發以對該資料輸入信號進行資料取樣並且依序 儲存所擷取之該資料輸入信號。 4.如申請專利範圍第1項所述之驅動電路,其中該雙 緣擷取資料傳遞單元包括: Ο201041445 30689twf.doc/n VII. Application for Patent Park: L—The driving circuit of a light-emitting diode' includes: a dual-edge data transfer unit that receives a timing signal and a data input signal. The data transfer unit is triggered by the rising edge and the falling edge of the timing signal to sample the data input signal and sequentially store the consumed input signal, and a signal processing unit coupled to the double edge The data transfer unit is configured to store the data input signal captured by the dual-edge data transfer unit and output a drive enable signal according to the stored data input signal; and a light-emitting diode driving unit, The signal processing unit is coupled to the signal processing unit and outputs at least one driving signal to drive at least one of the light emitting diodes according to the driving enable signal. 2. The driving circuit of claim 1, wherein the dual-edge data transfer unit comprises: a pulse generating circuit, generating a pulse signal according to the timing signal, wherein the pulse signal has a plurality of first pulses And a plurality of second pulses, the timings of the first pulses correspond to rising edges of the timing signals, the timings of the second pulses correspond to falling edges of the timing signals; and a single-edge trigger shift register, The data input signal is sampled according to the pulse signal, and the captured data input signal is sequentially stored. 3. The driving circuit according to claim 1, wherein the double edge data transfer unit comprises: 24 201041445 30689twf, doc/n a double edge trigger shift register, by the rising edge of the timing signal Triggering with the falling edge to sample the data input signal and sequentially store the captured data input signal. 4. The driving circuit of claim 1, wherein the double edge data transfer unit comprises: 一雙緣觸發移位暫存器,由該時序信號的上升緣與下 降緣進行觸發以對該資料輸入信號進行資料取樣並且依序 儲存所擷取之該資料輸入信號; —資料輸入信號處理電路,接收該資料輸入信號並輸 出同相或反相之該資料輸入信號;以及 —多工斋,該多工器的一第一輸入端耦接於該雙緣觸 ^矛夕位暫存器的輸出,該多工器的一第二輸入端耦接於該 資料輪入信號處理電路的輸出,該多工器的一輸出端耦接 於—資料輸出端。 5.如申凊專利乾圍第丨項所述之驅動電路,更包括: 日年序處理單元’接收該時序信號並用以輸出同相或 反相之該時序信號。 6.如申靖專利範圍第1項所述之驅 立 緣梅取資料傳遞單元包括: -第-雙緣觸發移位暫存器,用以儲存該資料輸入信 遽中之一影像資料; 號中發移位暫存器,用以儲存該資料輸入信 出人域處理電路,接收該資缝人信號並輸 出同相或反相之該資料輸入信號;以及 25 201041445 30689twf.doc/n ^ ^ ^ ππ踢夕工器的三個輪入端分別耦接於哕# 觸發移位暫存器、該第二雙緣觸發移d 貝枓輸出而太,亚根據一選擇信號決定該多工器的輪出。 7‘如申請專利範圍第丨項所述之驅動電路,星:二 號處理單元包括: 一貢料儲存電路,用以儲存該雙緣擷取資 所梅取的該資料輪人信號;以及 ㈣早凡 一資料運算電路,用以輸出該驅動致能信號。 8.如申請專利範圍第7項所述之驅動電路,其 料儲存電路包括: 、 一第一賁料儲存電路,根據一第一栓鎖信號儲 料輸入信號中之—影像資料;以及 X貝 、一第二資料儲存電路,根據/第二栓鎖信號儲存誃次 料輪入信號中之—命令資料。 貝 9.如申請專利範圍第7項所述之驅動電略,复 料運算電路包括: 、Τ遠一貝 一計數器;以及 複數個比較器,耦接於該計數器與該資料儲存電路, 用以比較所儲存之該資料輸入信號與該計數器的輪出以產 生該驅動致能信號至該發光二極艨驅動單元。 10.如申請專利範圍第7項所述之驅動電路,复 資料運算電路包括: 複數個及閘,該些及閘的輸入分別耦接於該資料儲存 。路與一致能信號,該些及閘的輸出則耦接於該發光二極 26 201041445 30689twf.doc/n 體驅動單元。 11. 如申請專利範圍第1項所述之驅動電路,更包括: 一偵測保護單元,用以偵測該發光二極體與該驅動電 路的狀態並輸出一偵測信號至該資料傳遞單元。 12. 如申請專利範圍第1項所述之驅動電路,其中該 發光二極體驅動單元更包括: 一發光二極體驅動電路,耦接於該信號處理單元,根 據該驅動致能信號輸出該些驅動信號以驅動該些發光二極 體;以及 一驅動信號設定電路,耦接於該發光二極體驅動電 路,用以調整該發光二極體驅動電路所輸出之該些驅動信 號。 13. 如申請專利範圍第12項所述之驅動電路,其中該 驅動信號設定電路包括: 一參考電壓產生電路; 一數位類比轉換電路,耦接於該信號處理單元以接收 該資料輸入信號中之一命令資料;以及 一電壓電流轉換電路,耦接該參考電壓產生電路與該 數位類比轉換電路,用以調整該發光二極體驅動單元所輸 出的該些驅動信號。 14. 如申請專利範圍第1項所述之驅動電路,更包括: 一控制單元,耦接於該雙緣擷取資料傳遞單元,用以 傳送該時序信號與該資料輸入信號至該雙緣擷取資料傳遞 單元,並透過時序信號與該資料輸入信號的組合以產生一 控制信號。 27a double edge trigger shift register is triggered by the rising edge and the falling edge of the timing signal to perform data sampling on the data input signal and sequentially store the captured data input signal; — data input signal processing circuit Receiving the data input signal and outputting the data input signal in the same phase or inversion; and - multi-working, a first input end of the multiplexer is coupled to the output of the double-edge touch device A second input end of the multiplexer is coupled to the output of the data wheel signal processing circuit, and an output end of the multiplexer is coupled to the data output end. 5. The driving circuit of claim 1, wherein the daily processing unit receives the timing signal and outputs the timing signal in phase or inversion. 6. The data transfer unit of the driving edge of the data according to item 1 of the Shenjing patent scope includes: - a first-double edge trigger shift register for storing one image data in the data input signal; a medium shift register for storing the data input and output human domain processing circuit, receiving the slot signal and outputting the data input signal in phase or inversion; and 25 201041445 30689twf.doc/n ^ ^ ^ The three wheel-in ends of the ππ kicking device are respectively coupled to the 哕# trigger shift register, and the second double-edge trigger shifts the b 枓 output, and the sub-decision determines the wheel of the multiplexer according to a selection signal. Out. 7' The driving circuit described in the scope of claim 2, the Star: No. 2 processing unit comprises: a tributary storage circuit for storing the data wheel signal obtained by the double edge collection; and (4) A data operation circuit is used to output the drive enable signal. 8. The driving circuit of claim 7, wherein the material storage circuit comprises: a first data storage circuit, the image data in the input signal according to a first latch signal, and the X-ray a second data storage circuit stores the command data in the secondary wheeling signal according to the /second latch signal. 9. The driving circuit as described in claim 7 of the patent application scope, the multiplexing operation circuit includes: a counter, a counter, and a plurality of comparators coupled to the counter and the data storage circuit for Comparing the stored data input signal with the rounding of the counter to generate the driving enable signal to the light emitting diode driving unit. 10. The driving circuit of claim 7, wherein the complex data operation circuit comprises: a plurality of gates, wherein the inputs of the gates are respectively coupled to the data storage. The circuit and the uniform signal, the outputs of the gates are coupled to the light-emitting diode 26 201041445 30689twf.doc/n body drive unit. 11. The driving circuit of claim 1, further comprising: a detecting and protecting unit for detecting a state of the light emitting diode and the driving circuit and outputting a detecting signal to the data transfer unit . 12. The driving circuit of claim 1, wherein the LED driving unit further comprises: a light emitting diode driving circuit coupled to the signal processing unit, and outputting the signal according to the driving enable signal The driving signals are used to drive the LEDs; and a driving signal setting circuit is coupled to the LED driving circuit for adjusting the driving signals output by the LED driving circuit. 13. The driving circuit of claim 12, wherein the driving signal setting circuit comprises: a reference voltage generating circuit; a digital analog conversion circuit coupled to the signal processing unit to receive the data input signal And a voltage-current conversion circuit coupled to the reference voltage generating circuit and the digital analog conversion circuit for adjusting the driving signals output by the LED driving unit. 14. The driving circuit of claim 1, further comprising: a control unit coupled to the dual edge data transfer unit for transmitting the timing signal and the data input signal to the double edge The data transfer unit is taken and a combination of the timing signal and the data input signal is used to generate a control signal. 27
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CN103813579A (en) * 2012-11-09 2014-05-21 明阳半导体股份有限公司 Light emitting diode driving circuit and driving system of light emitting diode
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US6596977B2 (en) * 2001-10-05 2003-07-22 Koninklijke Philips Electronics N.V. Average light sensing for PWM control of RGB LED based white light luminaries
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CN103687162A (en) * 2012-09-14 2014-03-26 明阳半导体股份有限公司 Light emitting diode driving circuit and driving system with same
TWI470609B (en) * 2012-09-14 2015-01-21 My Semi Inc Led driver circuit and driver system having the same
CN103687162B (en) * 2012-09-14 2016-05-18 明阳半导体股份有限公司 Light emitting diode driving circuit and driving system with same
CN103813579A (en) * 2012-11-09 2014-05-21 明阳半导体股份有限公司 Light emitting diode driving circuit and driving system of light emitting diode
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CN103813579B (en) * 2012-11-09 2016-04-06 明阳半导体股份有限公司 Light emitting diode driving circuit and driving system of light emitting diode
WO2020019872A1 (en) * 2018-07-26 2020-01-30 深圳市爱协生科技有限公司 Display device
CN110768879A (en) * 2018-07-26 2020-02-07 深圳市爱协生科技有限公司 Communication control link
CN110782828A (en) * 2018-07-26 2020-02-11 深圳市爱协生科技有限公司 Display device
CN110768879B (en) * 2018-07-26 2021-11-19 深圳市爱协生科技有限公司 Communication control link

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