CN111817703B - Detection circuit for specific coded signal - Google Patents
Detection circuit for specific coded signal Download PDFInfo
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- CN111817703B CN111817703B CN202010492407.6A CN202010492407A CN111817703B CN 111817703 B CN111817703 B CN 111817703B CN 202010492407 A CN202010492407 A CN 202010492407A CN 111817703 B CN111817703 B CN 111817703B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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Abstract
The application provides a detection circuit of a specific code signal, which processes the specific code signal to be detected and outputs a rising or falling edge effective signal through a processing module based on a preset clock signal and a preset width setting signal. The timing module counts the number of cycles of the preset clock signals correspondingly received by the adjacent rising or falling edge effective signals in the forming signals, and the timing module is matched with the timing holding module to output a timing holding value to the judging module so as to determine whether the frequency judging signals are effective or not. And determining whether the output frequency detection result is effective or not through a counting processing module according to the frequency judgment signal and a preset synchronous head period value. And when the frequency detection result is valid, determining whether to output a valid sampling time signal to the encoding processing module or not through the sampling time generation module based on the real-time timing value and a preset fixed value. And determining whether the output code detection result is valid or not through a code processing module based on the preset clock signal, the sampling moment valid signal and the preset code value signal.
Description
Technical Field
The present application relates to the field of signal detection technology, and in particular, to a detection circuit for a specific encoded signal.
Background
One frame of the specific coded signal comprises a synchronous head and a coded value, wherein the synchronous head is fixed in a mode that a bit 0 and a bit 1 are alternately transmitted, and the length is not fixed. The encoded value is a binary arbitrary value. The sync header is sent first in a frame. The specific coded signal comprises one or more high-level pulses in a bit period, the high-level duration of each pulse is not fixed, but the high-level duration of at least one pulse is larger than Ts; the specific coded signal must be at a high level at the beginning of the bit period and at a low level at the end of the bit period.
One period of the specific coded signal is shown in fig. 1, where a-c indicates the length of 1 bit period and a-d indicates the length of one period (referred to as Tp). The length between a-b is called Th, which represents the maximum length that a high level pulse may have. I.e. there may be high pulses between a-b in the high representation method and there must not be high pulses between b-c.
The low level in this particular encoded signal is represented as no high level pulse for 1 bit period. The detection of the specific coded signal is an urgent problem to be solved at present.
Disclosure of Invention
In view of this, it is necessary to provide a detection circuit capable of detecting the above-mentioned specific code signal.
A detection circuit for a particular encoded signal, comprising:
the processing module is used for inputting a specific coding signal to be detected, processing the specific coding signal to be detected based on a preset clock signal and a preset width setting signal and outputting a forming signal, and detecting a rising edge or a falling edge of the forming signal based on the preset clock signal and outputting a rising edge or a falling edge effective signal;
the timing module is electrically connected with the processing module and used for counting the number of cycles of the preset clock signal correspondingly received by the adjacent effective signal of the rising edge or the falling edge in the forming signal and outputting a real-time timing value;
the timing maintaining module is respectively electrically connected with the timing module and the processing module, and is used for receiving and storing the real-time timing value when the rising edge effective signal or the falling edge effective signal is effective based on the preset clock signal, and outputting the stored timing maintaining value;
the judging module is electrically connected with the timing holding module and is used for determining whether the output frequency judging signal is valid or not according to the timing holding value and a set threshold value;
the counting processing module is respectively electrically connected with the judging module and the processing module and is used for delaying one preset clock signal period based on the effective signal of the preset clock signal on the rising edge or the falling edge to receive the frequency judging signal and determining whether the output frequency detection result is effective or not according to the frequency judging signal and a preset synchronous head period value;
the sampling time generation module is respectively electrically connected with the counting processing module and the timing module and is used for determining whether to output a sampling time effective signal or not based on the real-time timing value and a preset fixed value when the frequency detection result is effective; and
and the coding processing module is respectively electrically connected with the sampling time generation module and the processing module and is used for determining whether the output coding detection result is valid or not based on the preset clock signal, the sampling time valid signal and the preset coding value signal.
In one embodiment, the encoding processing module includes:
the decoding cache module is respectively electrically connected with the sampling time generation module and the processing module and is used for determining whether the sampling time effective signal is effective or not based on the preset clock signal, and if the sampling time effective signal is effective, the forming signal is shifted and cached and a cached receiving signal is output; and
and the coding judgment module is electrically connected with the decoding cache module and is used for determining whether the output coding detection result is valid according to the cache receiving signal and the preset coding value signal.
In one embodiment, if the encoding determination module determines that the buffered received signal is the same as the predetermined encoded value signal, the output encoded detection result is valid;
and if the coding judgment module determines that the cache receiving signal is different from the preset coding value signal, the output coding detection result is invalid.
In one embodiment, when the frequency detection result is valid, the sampling time generation module is configured to determine whether the real-time timing value is equal to the preset fixed value;
if the real-time timing value is determined to be equal to the preset fixed value, the sampling moment generation module outputs the sampling moment effective signal;
and if the real-time timing value is determined to be not equal to the preset fixed value, the sampling moment generation module does not output the effective sampling moment signal.
In one embodiment, the count processing module comprises
The delay module is electrically connected with the processing module and used for delaying the effective rising or falling edge signal for one preset clock signal period based on the preset clock signal and outputting the effective rising or falling edge delay signal; and
and the counting module is respectively electrically connected with the judging module and the delay module and is used for receiving the frequency judging signal when the effective delay signal of the rising edge or the falling edge is effective based on the preset clock signal and determining whether the output frequency detection result is effective according to whether the frequency judging signal is effective and the preset synchronous head period value.
In one embodiment, if the frequency decision signal received by the counting module is a valid signal, the count value of the counting module is added up;
and if the frequency judgment signal received by the counting module is an invalid signal, clearing the count value of the counting module.
In one embodiment, when the count value of the counting module reaches the preset synchronization header period value, the frequency detection result output by the counting module is valid.
In one embodiment, the counting module is electrically connected with the timing module;
and when the output frequency detection result is valid, the timing module clears the real-time timing value based on a preset cycle length and counts in the preset cycle length again.
In one embodiment, the counting module is electrically connected with the timing module;
the timing module is further configured to determine whether the real-time timing value exceeds a maximum countable range thereof, and if the real-time timing value exceeds the maximum countable range, the timing module outputs a timing value invalid signal to the timing keeping module and the counting module.
In one embodiment, when the timing holding module receives the timing value invalid signal, the timing holding module clears the timing holding value;
and when the counting module receives the timing value invalid signal, the counting module clears the counting value.
In one embodiment, when the timing keeping module receives the real-time timing value or the timing module outputs the timing value invalid signal, the timing module clears the real-time timing value and counts again.
In one embodiment, the judging module receives the timing holding value and determines whether the timing holding value is within the set threshold range;
if the timing holding value is determined to be within the set threshold range, the frequency judgment signal output by the judgment module is valid;
if the timing holding value is determined not to be within the set threshold range, the frequency judgment signal output by the judgment module is invalid;
and the set threshold is set according to the cycle length setting signal and the cycle fault tolerance setting signal of the specific coding signal to be detected.
In one embodiment, the processing module comprises:
the buffer module comprises N cascaded D triggers, and is used for shifting and buffering the specific coding signal to be detected through each level of D triggers according to the rising edge or the falling edge of the preset clock signal and outputting a tap signal delayed by each level of D triggers;
a first input end of the high-level widening module is electrically connected with an output end of the cache module, and a second input end of the high-level widening module is used for inputting the preset width setting signal and outputting the forming signal according to the tap signals of each level and the preset width setting signal; and
the detection module is respectively electrically connected with the high-level broadening module, the timing module and the timing keeping module, and is used for detecting the rising or falling edge of the forming signal according to the preset clock signal and outputting a rising or falling edge effective signal;
and N is an integer greater than N, and is greater than the ratio of the period of the specific encoding signal to be detected to the period of the preset clock signal.
Compared with the prior art, the detection circuit of the specific coding signal processes the specific coding signal to be detected and outputs a forming signal through the processing module based on the preset clock signal and the preset width setting signal, and simultaneously detects the rising edge or the falling edge of the forming signal and outputs a rising edge or falling edge effective signal; counting the number of cycles of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the molding signal through a timing module, and outputting a timing holding value to a judging module by matching with the timing holding module, thereby determining whether the frequency judging signal is effective; and determining whether the output frequency detection result is valid or not through a counting processing module according to the frequency judgment signal and a preset synchronous head period value. When the frequency detection result is valid, determining whether to output a sampling time valid signal to the encoding processing module or not through the sampling time generation module based on the real-time timing value and a preset fixed value; and finally, determining whether the output code detection result is valid or not through a code processing module based on the preset clock signal, the sampling moment valid signal and the preset code value signal, thereby realizing the low-power consumption detection function of the specific code signal.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a specific encoded signal provided in an embodiment of the present application;
FIG. 2 is a block circuit diagram of a specific encoded signal detection circuit according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of a cache module according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a high-level stretching module according to an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a detection module according to an embodiment of the present application;
fig. 6 is a circuit diagram of a delay module according to an embodiment of the present application.
Description of reference numerals:
10 detection circuit for specific coded signal
100 processing module
110 cache module
111D trigger
120 high level widening module
121 OR gate circuit
122 selection circuit
130 detection module
131 trigger
132 NOT gate
133 and gate
200 timing module
300 timing keeping module
400 judging module
500 count processing module
510 delay module
520 counting module
600 sampling moment generation module
700 coding processing module
710 decoding buffer module
720 coding judgment module
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and fig. 2, an embodiment of the present application provides a specific coded signal detection circuit 10, including: the device comprises a processing module 100, a timing module 200, a timing holding module 300, a judging module 400, a counting processing module 500, a sampling time generating module 600 and an encoding processing module 700. The input end of the processing module 100 is used for inputting a specific coded signal to be detected. The processing module 100 is configured to process the specific encoding signal to be detected based on a preset clock signal and a preset width setting signal and output a forming signal. The processing module 100 is further configured to detect a rising edge or a falling edge of the forming signal based on the preset clock signal and output a rising edge or a falling edge valid signal. The timing module 200 is electrically connected to the processing module 100. The timing module 200 is configured to count the number of periods of the preset clock signal correspondingly received by the adjacent rising or falling edge valid signal in the molding signal, and output a real-time timing value.
The timing maintaining module 300 is electrically connected to the timing module 200 and the processing module 100, respectively. The timing keeping module 300 is configured to receive and save the real-time timing value when the rising or falling edge valid signal is valid based on the preset clock signal, and output a saved timing keeping value. The judging module 400 is electrically connected to the timing keeping module 300. The judging module 400 is configured to determine whether the output frequency decision signal is valid according to the timing hold value and a set threshold. The counting process module 500 is electrically connected to the determination module 400 and the process module 100, respectively. The counting processing module 500 is configured to delay the receiving of the frequency decision signal by one preset clock signal period based on the valid signal of the preset clock signal on the rising or falling edge, and determine whether the output frequency detection result is valid according to the frequency decision signal and a preset synchronization header period value.
The sampling time generation module 600 is electrically connected to the counting module 500 and the timing module 200, respectively. When the frequency detection result is valid, the sampling time generation module 600 determines whether to output a sampling time valid signal based on the real-time timing value and a preset fixed value. The encoding processing module 700 is electrically connected to the sampling time generation module 600 and the processing module 100, respectively. The encoding processing module 700 is configured to determine whether an output encoding detection result is valid based on the preset clock signal, the sampling time valid signal, and a preset encoding value signal. In one embodiment, one cycle of the specific coded signal to be detected is shown in FIG. 1.
It is understood that the specific structure of the processing module 100 is not limited as long as it has the function of processing the specific encoding signal to be detected and outputting a shaped signal based on the preset clock signal and the preset width setting signal. In one embodiment, the processing module 100 may include a buffer module 110, a high-level stretching module 120, and a detection module 130. Specifically, as shown in fig. 3, the cache module 110 may include N cascaded D flip-flops 111. And N is an integer greater than 1 and is greater than the ratio of the period of the specific encoding signal to be detected to the period of the preset clock signal.
In one embodiment, the buffer module 110 may be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. When the preset clock signal is input to the buffer module 110, that is, when the D flip-flops 111 at each stage all receive the edge trigger signal of the preset clock signal, the D flip-flops 111 at each stage shift and buffer the specific code signal to be detected, and the D flip-flops 111 at each stage output delayed tap signals corresponding to the specific code signal. Specifically, as shown in fig. 3, each stage of the D flip-flop 111 outputs a tap signal corresponding thereto. For example, D flip-flop 1 outputs tap signal 1,D and flip-flop 2 outputs tap signal 2 … … D flip-flop N outputs tap signal N.
In one embodiment, a first input terminal of the high-level stretching module 120 is electrically connected to an output terminal of the buffer module 110. A second input end of the high-level widening module 120 is configured to input the preset width setting signal. The high-level widening module 120 is configured to output the forming signal according to the tap signal at each level and the preset width setting signal. In one embodiment, as shown in fig. 4, the high-level stretching module 120 may include a plurality of or gates 121 and a selection circuit 122. In one embodiment, the or gate circuit 121 may be a logic or gate.
Specifically, two input terminals of any one of the or gates 121 of the plurality of or gates 121 receive the tap signal 1 and the tap signal 2, respectively. Each of the other or gate circuits 121 has one input terminal connected to the output terminal of the adjacent or gate circuit 121, the other input terminal receiving a tap signal, and the tap signal received by each or gate circuit 121 is different. The outputs of the plurality of or gates 121 are electrically connected to a selection circuit 122, and the selection circuit 122 may also directly receive the tap signal 1. For example, one input terminal of OR gate 1 receives tap signal 1, the other input terminal thereof receives tap signal 2, and the output terminal thereof is electrically connected to input terminal 2 of selection circuit 122, one input terminal of OR gate 2 receives tap signal 3, and the other input terminal thereof is electrically connected to the output terminal of OR gate 1, or the output terminal of OR gate 2 is electrically connected to input terminal 3 of selection circuit 122 … …, or one input terminal of OR gate N-1 receives tap signal N, and the other input terminal thereof is electrically connected to the output terminal of OR gate N-2, or the output terminal of OR gate N-1 is electrically connected to input terminal N of selection circuit 122. Input 1 of selection circuit 122 receives tap signal 1 directly.
In one embodiment, the selection circuit 122 is further configured to receive the preset width setting signal, and determine which of the tap signals in each stage the output shaping signal is according to the preset width setting signal. For example, if the preset width setting signal received by the selection circuit 122 is 3, the molding signal output by the output terminal of the selection circuit 122 is the signal received by the input terminal 3 of the selection circuit 122. If the preset width setting signal received by the selection circuit 122 is N, the forming signal output by the output end of the selection circuit 122 is the signal received by the input end N of the selection circuit 122. In an embodiment, a value corresponding to the preset width setting signal should be greater than a difference between a maximum length of a high-level pulse in the specific encoding signal to be detected and a period of the preset clock signal. In one embodiment, the selection circuit 122 is a one-out-of-many selector.
In one embodiment, the detection module 130 is electrically connected to the high-level stretching module 120, the timing module 200, and the timing keeping module 300, respectively. The detecting module 130 is configured to detect a rising edge or a falling edge of the forming signal according to the preset clock signal and output a rising edge or a falling edge valid signal. It is understood that the specific structure of the detection module 130 is not limited as long as it has the function of detecting the rising or falling edge of the molding signal and outputting a rising or falling edge valid signal. In one embodiment, as shown in fig. 5, the detection module 130 may be composed of a flip-flop 131, a not gate 132, and an and gate 133. Specifically, a first input end of the flip-flop 131 is electrically connected to an output end of the high-level stretching module 120. A second input terminal of the flip-flop 131 is configured to input the preset clock signal. An input terminal of the not gate 132 is electrically connected to an output terminal of the flip-flop 131. A first input terminal of the and gate 133 is electrically connected to the output terminal of the high-level stretching module 120. A second input of the and gate 133 is electrically connected to an output of the not gate 132. The output terminal of the and gate 133 is configured to output the rising or falling edge valid signal to the timing module 200.
In one embodiment, the flip-flop 131 may be a D flip-flop. In one embodiment, the flip-flop 131 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. In this embodiment, through the cooperation of the flip-flop 131, the not gate 132 and the and gate 133, the rising edge or the falling edge of the forming signal can be detected, and finally the rising edge or the falling edge valid signal is output to the timing module 200.
In one embodiment, the timing module 200 may be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. When the detecting module 130 outputs the rising or falling edge valid signal to the timing module 200, the timing module 200 may count the number of cycles of the predetermined clock signal correspondingly received by the adjacent rising or falling edge valid signal in the molding signal. That is, the timing module 200 may count the number of cycles of the preset clock signal received by the timing module 200 in a time period corresponding to the adjacent effective rising or falling edge signal. Specifically, in a time period corresponding to an effective signal of the rising edge or the falling edge in the molding signal, the timing module 200 may count the rising edge or the falling edge of the received preset clock signal and output a real-time timing value.
In one embodiment, the timing and holding module 300 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. When the rising or falling edge valid signal received by the timing holding module 300 is valid, the timing holding module 300 may sample and store the real-time timing value output by the timing module 200, and at this time, the timing module 200 automatically resets the real-time timing value and counts again. Meanwhile, the timing keeping module 300 outputs the saved timing keeping value to the determining module 400.
In one embodiment, the determining module 400 receives the timing hold value output by the timing hold module 300, and determines whether the output frequency decision signal is valid according to the timing hold value and the set threshold. Specifically, the determining module 400 may determine whether the timing keeping value is within the set threshold range. If it is determined that the timing hold value is within the set threshold range, the frequency decision signal output by the determining module 400 is valid. If it is determined that the timing hold value is not within the set threshold range, the frequency decision signal output by the determining module 400 is invalid. In one embodiment, the setting threshold may be set according to a period length setting signal and a period fault tolerance setting signal of the specific encoding signal to be detected. Specifically, the range of the set threshold may be from a difference between the period length setting signal and the period fault-tolerant setting signal to a sum of the period length setting signal and the period fault-tolerant setting signal. In one embodiment, the period length setting signal and the period fault tolerance setting signal may be set in advance in the determination module 400 according to actual requirements.
In one embodiment, the count processing module 500 may be composed of a delay and a counter. In one embodiment, the count processing module 500 may be triggered by an edge (i.e., a rising edge or a falling edge) of the preset clock signal. Specifically, after the counting module 500 is triggered, the counting module 500 may receive the frequency decision signal after the rising or falling valid signal is delayed by one period of the predetermined clock signal. If the frequency decision signal received by the counting processing module 500 is a valid signal, the count value in the counting processing module 500 is added by 1. If the frequency decision signal received by the count processing module 500 is an invalid signal, the count value in the count processing module 500 is cleared.
In one embodiment, the preset sync header period value may be stored in the count processing module 500 in advance. When the count value in the counting module 500 reaches the preset synchronization head cycle number, that is, the count value is equal to the preset synchronization head cycle number, it indicates that a valid synchronization head signal is detected, and at this time, the frequency detection result output by the counting module 500 is valid. Otherwise, when the count value is smaller than the preset synchronization header period value, it indicates that no valid synchronization header signal is detected, and at this time, the frequency detection result output by the count processing module 500 is invalid.
In one embodiment, when the frequency detection result output by the count processing module 500 is valid, the sampling time generation module 600 may determine whether the received real-time timing value is equal to the preset fixed value. If the sampling time generation module 600 determines that the real-time timing value is equal to the preset fixed value, the sampling time generation module 600 outputs the sampling time valid signal. If the sampling time generation module 600 determines that the real-time timing value is not equal to the preset fixed value, the sampling time generation module 600 does not output the sampling time valid signal. Wherein, the preset fixed value is a positive integer, and is generally 1 or a high level width setting value of-1.
In an embodiment, when the frequency detection result output by the count processing module 500 is invalid, the sampling time generation module 600 does not determine whether the received real-time timing value is equal to the preset fixed value. That is, only when the frequency detection result is valid, the sampling time generation module 600 may determine whether the received real-time timing value is equal to the preset fixed value.
In one embodiment, the encoding processing module 700 may include: a decoding buffer module 710 and an encoding decision module 720. Specifically, the decoding buffer module 710 is electrically connected to the sampling time generation module 600 and the processing module 100, respectively. The decoding buffer module 710 is configured to determine whether the sampling time valid signal is valid based on the preset clock signal, and if the sampling time valid signal is valid, shift and buffer the molding signal and output a buffered received signal. The encoding judgment module 720 is electrically connected to the decoding buffer module 710. The encoding judgment module 720 is configured to determine whether an output encoding detection result is valid according to the buffered received signal and the preset encoding value signal.
In one embodiment, the decode buffer module 710 may be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. When the sampling time generation module 600 outputs the sampling time valid signal, the decoding buffer module 710 may determine whether the received sampling time valid signal is valid. If the sampling time valid signal is valid, the forming signal is shifted and buffered, and a buffered received signal is output to the encoding determination module 720. On the contrary, if the sampling time valid signal is invalid (that is, the decoding cache module 710 does not receive the sampling time valid signal), the decoding cache module 710 does not perform shift cache on the molding signal. In one embodiment, the decode buffer module 710 may include N D flip-flops; and N is greater than or equal to the bit number of the preset coding value signal.
In an embodiment, after receiving the buffered received signal sent by the decoding buffering module 710, the encoding determining module 720 may compare the buffered received signal with the predetermined encoding value signal. If the buffered received signal is the same as the preset code value signal, indicating that the detection circuit 10 of the specific code signal detects an effective specific code signal, the code detection result output by the code determination module 720 is effective. On the contrary, if the buffered received signal is different from the preset code value signal, which indicates that the detection circuit 10 of the specific code signal does not detect a valid specific code signal, the code detection result output by the code determination module 720 is invalid.
The detection circuit can realize low-power consumption detection of the specific coded signal. The wireless wake-up circuit can be used as a demodulation and decoding circuit to be applied to circuits which need wireless low-power wake-up functions, such as the field of wireless sensor end design in the Internet of things and the Internet of vehicles.
In this embodiment, the processing module 100 processes the specific encoding signal to be detected and outputs a forming signal based on the preset clock signal and the preset width setting signal, and detects a rising edge or a falling edge of the forming signal and outputs a rising edge or a falling edge valid signal; counting the number of cycles of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the forming signal through the timing module 200, and outputting a timing hold value to the judging module 400 in cooperation with the timing hold module 300, thereby determining whether the frequency judging signal is effective; and determining whether the output frequency detection result is valid or not through the counting processing module 500 according to the frequency judgment signal and a preset synchronization header period value. When the frequency detection result is valid, determining whether to output a sampling time valid signal to the encoding processing module through the sampling time generation module 600 based on the real-time timing value and a preset fixed value; and finally, determining whether the output code detection result is valid or not through the code processing module 700 based on the preset clock signal, the sampling time valid signal and the preset code value signal, thereby realizing the low-power consumption detection function of the specific code signal.
In one embodiment, the count processing module 500 includes a delay module 510 and a count module 520. The delay module 510 is electrically connected to the processing module 100. The delay module 510 is configured to delay the effective rising or falling edge signal by one period of the preset clock signal based on the preset clock signal, and output the effective rising or falling edge delayed signal. The counting module 520 is electrically connected to the determining module 400 and the delaying module 510, respectively. The counting module 520 is configured to receive the frequency decision signal when the rising or falling edge effective delay signal is effective based on the preset clock signal, and determine whether the output frequency detection result is effective according to whether the frequency decision signal is effective and the preset synchronization header period value.
In one embodiment, the delay module 510 and the counting module 520 may both be triggered by an edge (i.e., a rising edge or a falling edge) of the predetermined clock signal. In one embodiment, after the delay module 510 is triggered by the predetermined clock signal, the delay module 510 may delay the effective rising or falling edge signal output by the detection module 130 in the processing module 100 by one period of the predetermined clock signal and output the effective rising or falling edge delay signal to the counting module 520. As shown in fig. 6, the delay module 510 may be formed by a D flip-flop.
When the counting module 520 is triggered by the preset clock signal, the counting module 520 may receive the frequency decision signal when the rising or falling edge valid delay signal is valid, and add 1 to the count value in the counting module 520 if the frequency decision signal received by the counting module 520 is a valid signal. If the frequency decision signal received by the counting module 520 is an invalid signal, the count value in the counting module 520 is cleared.
When the count value in the counting module 520 reaches the preset sync period number, that is, the count value is equal to the preset sync period number, it indicates that the detection circuit 10 of the specific encoded signal detects an effective sync signal, and at this time, the frequency detection result output by the counting module 520 is effective. On the contrary, when the count value is smaller than the preset detection period value, it indicates that the detection circuit 10 of the specific encoded signal does not detect a valid sync header signal, and the frequency detection result output by the counting module 520 is invalid at this time.
Since the buffer module 110, the detection module 130, the timing module 200, the timing keeping module 300, the delay module 510, the counting module 520, and the decoding buffer module 710 are all awakened by the preset clock signal, the power consumption of the detection circuit 10 for the specific code signal can be reduced when detecting the specific code signal, so that the low power consumption detection function for the specific code signal can be realized.
In one embodiment, the counting module 520 is electrically connected to the timing module 200. The timing module 200 is also configured to determine whether the real-time timing value exceeds its maximum countable range. If the real-time timing value exceeds the maximum countable range, the timing module 200 outputs a timing value invalid signal to the timing keeping module 300 and the counting module 520, and the timing module 200 clears the real-time timing value. When the timing holding module 300 receives the timing value invalid signal, the timing holding module 300 clears the saved timing holding value. Meanwhile, when the counting module 520 receives the timing value invalid signal, the counting module 520 also clears the count value. That is, as long as the timing module 200 determines that the real-time timing value exceeds the maximum countable range, the timing module 200, the timing keeping module 300, and the counting module 520 all clear their respective counts.
In one embodiment, when the frequency detection result output by the counting module 520 is valid, the timing module 200 clears the real-time timing value based on a preset period length and counts again within the preset period length. Specifically, when the frequency detection result is valid, the timing module 200 may count the number of cycles of the received preset clock signal in the preset cycle length in real time, and output a real-time timing value. When the preset period length is reached, the timing module 200 clears the real-time timing value, and counts the number of periods of the received preset clock signal within the preset period length again.
In summary, the processing module 100 processes the specific to-be-detected encoded signal based on the preset clock signal and the preset width setting signal and outputs a forming signal, and detects a rising edge or a falling edge of the forming signal and outputs a rising edge or a falling edge effective signal; counting the number of cycles of the preset clock signal correspondingly received by the adjacent rising or falling edge effective signal in the forming signal through the timing module 200, and outputting a timing hold value to the judging module 400 in cooperation with the timing hold module 300, thereby determining whether the frequency judging signal is effective; and determining whether the output frequency detection result is valid or not through the counting processing module 500 according to the frequency decision signal and a preset synchronization header period value. When the frequency detection result is valid, determining whether to output a sampling time valid signal to the encoding processing module through the sampling time generation module 600 based on the real-time timing value and a preset fixed value; and finally, determining whether the output code detection result is valid or not through the code processing module 700 based on the preset clock signal, the sampling time valid signal and the preset code value signal, thereby realizing the low-power consumption detection function of the specific code signal.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A circuit for detecting a particular encoded signal, comprising:
the processing module (100), an input end of the processing module (100) is used for inputting a specific coded signal to be detected, processing the specific coded signal to be detected based on a preset clock signal and a preset width setting signal and outputting a forming signal, and is also used for detecting a rising edge or a falling edge of the forming signal based on the preset clock signal and outputting a rising edge or a falling edge effective signal;
the timing module (200) is electrically connected with the processing module (100) and is used for counting the number of periods of the preset clock signal correspondingly received by the adjacent effective rising or falling edge signal in the forming signal and outputting a real-time timing value;
the timing keeping module (300) is respectively electrically connected with the timing module (200) and the processing module (100), and is used for receiving and saving the real-time timing value based on the preset clock signal when the effective signal of the rising or falling edge is effective, and outputting the saved timing keeping value;
the judging module (400) is electrically connected with the timing holding module (300) and is used for determining whether the output frequency judging signal is valid or not according to the timing holding value and a set threshold value;
the counting processing module (500) comprises a delay module (510) and a counting module (520), the delay module (510) is electrically connected with the processing module (100), the counting module (520) is electrically connected with the judging module (400) and the delay module (510) respectively, and the counting processing module (500) is used for delaying one preset clock signal period to receive the frequency judgment signal based on the effective signal of the preset clock signal on the rising edge or the falling edge, and determining whether the output frequency detection result is effective according to the frequency judgment signal and a preset synchronous head period value;
the sampling moment generating module (600) is respectively electrically connected with the counting processing module (500) and the timing module (200) and is used for determining whether to output a sampling moment effective signal or not based on the real-time timing value and a preset fixed value when the frequency detection result is effective; and
and the coding processing module (700) is respectively electrically connected with the sampling time generation module (600) and the processing module (100) and is used for determining whether the output coding detection result is valid or not based on the preset clock signal, the sampling time valid signal and the preset coding value signal.
2. The detection circuit of a particular coded signal according to claim 1, characterized in that said coding processing module (700) comprises:
a decoding buffer module (710) electrically connected to the sampling time generation module (600) and the processing module (100), respectively, and configured to determine whether the sampling time valid signal is valid based on the preset clock signal, and if the sampling time valid signal is valid, shift and buffer the molding signal and output a buffered received signal; and
and the coding judgment module (720) is electrically connected with the decoding cache module (710) and is used for determining whether the output coding detection result is valid according to the cache receiving signal and the preset coding value signal, if the cache receiving signal is determined to be the same as the preset coding value signal, the output coding detection result is valid, and if the cache receiving signal is determined to be different from the preset coding value signal, the output coding detection result is invalid.
3. A detection circuit for a specific coded signal according to claim 1, characterized in that when said frequency detection result is valid, said sampling instant generation module (600) is adapted to determine whether said real time timing value is equal to said preset fixed value;
if the real-time timing value is determined to be equal to the preset fixed value, the sampling time generation module (600) outputs the effective sampling time signal;
and if the real-time timing value is determined not to be equal to the preset fixed value, the sampling moment generation module (600) does not output the effective sampling moment signal.
4. The detection circuit of a specific encoded signal according to claim 1, wherein said delay module (510) is configured to delay said rising or falling edge valid signal by one period of said predetermined clock signal based on said predetermined clock signal and to output a rising or falling edge valid delayed signal; and
the counting module (520) is configured to receive the frequency decision signal when the rising or falling edge effective delay signal is effective based on the preset clock signal, and determine whether the output frequency detection result is effective according to whether the frequency decision signal is effective and the preset synchronization header period value.
5. The detection circuit for a specific coded signal according to claim 4, wherein if the frequency decision signal received by the counting module (520) is a valid signal, the count value of the counting module (520) is cumulatively increased by 1;
if the frequency decision signal received by the counting module (520) is an invalid signal, the count value of the counting module (520) is cleared.
6. The detection circuit of a specific coded signal according to claim 5, characterized in that said counting module (520) is electrically connected to said timing module (200);
when the accumulated count value of the counting module (520) reaches the preset synchronization head period value, the frequency detection result output by the counting module (520) is valid, and at the moment, the timing module (200) clears the real-time timing value based on the preset period length and counts again in the preset period length.
7. The detection circuit of a specific coded signal according to claim 4, characterized in that said counting module (520) is electrically connected to said timing module (200);
the timing module (200) is further configured to determine whether the real-time timing value exceeds a maximum countable range thereof, and if the real-time timing value exceeds the maximum countable range, the timing module (200) outputs a timing value invalidation signal to the timing maintenance module (300) and the counting module (520);
when the timing holding module (300) receives the timing value invalid signal, the timing holding module (300) clears the timing holding value;
when the counting module (520) receives the timing value invalid signal, the counting module (520) clears the counting value.
8. The detection circuit of a specific coded signal according to claim 7, wherein when the timing maintenance module (300) receives the real-time timer value or the timing module (200) outputs the timer value disable signal, the timing module (200) clears and recounts the real-time timer value.
9. The detection circuit of a particular coded signal according to claim 1, wherein said decision module (400) receives said timing hold value and determines whether said timing hold value is within a set threshold range;
if the timing holding value is determined to be within the set threshold range, the frequency judgment signal output by the judgment module (400) is valid;
if the timing holding value is determined not to be within the set threshold range, the frequency judgment signal output by the judgment module (400) is invalid;
and the set threshold is set according to the cycle length setting signal and the cycle fault tolerance setting signal of the specific coding signal to be detected.
10. The detection circuit of a particular coded signal according to claim 1, characterized in that said processing module (100) comprises:
the buffer module (110) comprises N cascaded D flip-flops (111), and the buffer module (110) is used for shifting and buffering the specific coding signal to be detected through each stage of the D flip-flops (111) according to the rising edge or the falling edge of the preset clock signal and outputting a tap signal delayed by each stage of the D flip-flops (111);
a high-level widening module (120), a first input end of the high-level widening module (120) being electrically connected to an output end of the cache module (110), and a second input end of the high-level widening module (120) being configured to input the preset width setting signal, and being configured to output the molding signal according to the tap signal of each stage and the preset width setting signal; and
the detection module (130) is electrically connected with the high-level stretching module (120), the timing module (200) and the timing and holding module (300) respectively, and is used for detecting a rising edge or a falling edge of the molding signal according to the preset clock signal and outputting a rising edge or falling edge effective signal;
and N is an integer greater than 1 and is greater than the ratio of the period of the specific encoding signal to be detected to the period of the preset clock signal.
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