CN110703582B - Thermometer code to binary code circuit for time-to-digital converter - Google Patents

Abstract

The invention discloses a thermometer code to binary code circuit for a time-to-digital converter, which comprises: the temperature meter code is used as an input signal and is accessed to the LUT screening circuit, an LUT unit in the screening circuit inverts the high 5 bits of the input signal, the inversion result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal and is accessed to a read enable end of the RAM storage circuit; when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized. The invention solves the problem of bubbling in the decoding process of the FPGA-based time-to-digital converter, and improves the overall performance of the FPGA-based time-to-digital converter.

Description

Thermometer code to binary code circuit for time-to-digital converter

Technical Field

The invention relates to the field of integrated circuit measurement, in particular to a decoding circuit which is applied to a time-to-digital converter based on an FPGA and used for converting thermometer codes into binary codes.

Background

The time interval measurement technology has great significance to national economy and national defense industrial construction, and is an accurate time interval measurement technology, in particular to a picosecond (1ps is 10 ═ 10)¹²s) order of magnitude is more important. The method has very important application in the theoretical research fields of molecular biology, nuclear physical detection, astronomical observation and the like, and the engineering practice fields of laser ranging, high-precision positioning, food and drug safety monitoring and the like.

Currently, the most widely used high-precision time interval measurement technology is the time To Digital Converter (TDC) technology, and the most important technical index is the measurement precision. Most industrial-scale time-to-digital converters are implemented primarily using Application Specific Integrated Circuits (ASICs). Compared with an ASIC type TDC, the TDC based on the FPGA has the advantages of low development cost, short period and the like. Meanwhile, with the progress of the manufacturing technology of the integrated circuit, the manufacturing process of the FPGA is greatly improved, and the delay of the internal connecting line and the logic unit of the FPGA is smaller and smaller, so that the TDC can also achieve high measurement precision.

In the FPGA-based time-to-digital converter, a tap signal output by a delay chain is a thermometer code, and a decoding circuit is required to convert the thermometer code into a binary code for subsequent numerical calculation. The accuracy and speed of the decoding circuit greatly affect the measurement accuracy and speed of the time-to-digital converter. However, the thermometer code of the tap output may exhibit irregularities, so-called "bubbling", for various reasons, such as: the FPGA chip has process deviation in the manufacturing process, so that the delay time of carry units in a carry chain is inconsistent, taking Xilinx Artix 7 series FPGA as an example, a large delay with the carry time of 91ps appears in every 4 adjacent carry units, and as the carry time of the carry unit is large, the set-up time of a trigger may not be met, so that a tap value cannot be normally latched. The carry time of the next stage carry unit is shorter, and the tap signal can be correctly latched by a trigger, so that the tail end of the valid bit of the thermometer code generates a bubbling phenomenon; for another example: clock signals in the FPGA clock network cannot reach each trigger at the same time, but certain clock skew exists, and if the clock skew of two adjacent triggers used for latching carry signals in a carry chain is large, the trigger at the next stage latches the carry signals in advance of the trigger at the previous stage, and the bubbling phenomenon can also be caused.

The serious bubbling phenomenon can greatly reduce the precision of converting thermometer code into binary code (decoding), thereby influencing the precision of a time-to-digital converter and bringing great difficulty to the design of a thermometer code into binary code circuit. Document [1] proposes a method and a device for decoding and converting thermometer codes into binary codes based on an FPGA chip. The principle is that the thermometer code is divided into a plurality of window values through a sliding window, and the one-hot codes corresponding to the thermometer code are obtained by sequencing true values corresponding to the window values, so that bubble error correction is realized. Meanwhile, the one-hot code is converted into a binary code by using a pipeline structured coding algorithm. The thermometer code to binary code circuit disclosed by the document can well realize the filtering of a thermometer code 'bubble' code segment, but the decoding algorithm is complex, the utilization rate of FPGA resources is not high, and the decoding time is long. Meanwhile, the decoder disclosed in the document has poor time sequence characteristics, and a pipeline structure is used for eliminating the time sequence problem caused by too large logic path delay, so that more trigger resources are occupied.

Reference documents:

[1]Wang Y,Kuang J,Liu C,et al.A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA[J].IEEE Transactions on Nuclear Science,2017,64(10):2713-2718.

disclosure of Invention

In order to solve the problem of bubbling in the decoding process of the FPGA-based time-to-digital converter, the invention designs a thermometer code-to-binary code circuit with strong fault tolerance, high decoding speed and good time sequence characteristic from the specific hardware circuit level, thereby improving the overall performance of the FPGA-based time-to-digital converter, and the details are described in the following:

a thermometer code to binary code circuit for a time-to-digital converter, the circuit comprising: an LUT screening circuit and a RAM memory circuit,

the thermometer code is used as an input signal and is accessed into an LUT screening circuit, an LUT unit in the screening circuit inverts the high 5 bits of the input signal, the inversion result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal and is accessed into a read enable end of an RAM storage circuit;

when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized.

Wherein the circuit further comprises: and storing the binary codes corresponding to the thermometer codes into a RAM storage circuit.

Further, the LUT screening circuit filters out bubble code segments through logic operation and outputs a read enable signal.

The LUT screening circuit specifically filters out the bubble code segment through logic operation as follows:

sequentially inputting every adjacent 6 bits into a corresponding LUT from the 0 th bit to the highest bit;

the LUT screening circuit only outputs logic 1 on the LUT with 000001 code segment as input, and the other LUTs output logic 0, thereby enabling the corresponding RAM to read out binary numbers.

The technical scheme provided by the invention has the beneficial effects that:

1. the invention uses the RAM unit to realize the conversion from thermometer code to binary code, does not use complex combinational logic, and can keep good time sequence characteristic even if a pipeline structure is not inserted;

2. the invention carries out logical negation and logical AND operation on every adjacent 6 bits in the thermometer code by using an LUT (lookup table) screening circuit, accurately identifies the 000001 code segment, filters the bubbling code segment, and can carry out fault-tolerant decoding on the thermometer code with 4 bubbling bits at most;

3. the invention stores the binary codes corresponding to each thermometer code into the corresponding RAM in advance by initializing the memory, and can read the binary codes by only one clock cycle in a RAM reading mode, thereby realizing the conversion from the thermometer codes to the binary codes and effectively improving the decoding speed.

In conclusion, the thermometer code to binary code circuit designed by the invention can effectively improve the decoding precision and speed, and is beneficial to improving the overall performance of the FPGA type time-to-digital converter.

Drawings

FIG. 1 is a schematic diagram of a thermometer code to binary code circuit;

FIG. 2 is a block diagram of a thermometer code to binary code circuit;

FIG. 3 is a logic diagram of an internal implementation of a LUT;

FIG. 4 is a schematic view of a thermometer code;

fig. 5 is a structural diagram of a RAM cell.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.

Example 1

1. The invention relates to a thermometer code-to-binary code circuit, which comprises two parts: LUT screening circuit and RAM memory circuit.

The LUT screening circuit is used for identifying the position of the most significant bit 01 alternating position and filtering a thermometer code bubbling code section; the RAM storage circuit is used for pre-storing binary numbers, and the conversion from thermometer codes to binary codes is realized by reading the pre-stored binary numbers in the RAM.

2. In the invention, a thermometer code is used as an input signal and is accessed into an LUT screening circuit. The LUT unit in the screening circuit firstly inverts the high 5 bits of the input signal, then the inverted result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal to be accessed to a read enable end of the RAM storage circuit.

3. Before the decoder executes decoding action, the RAM storage circuit is initialized, binary codes corresponding to all thermometer codes are stored in the RAM storage circuit, and when the read enable from the LUT screening circuit is pulled high, the binary codes in the corresponding RAM storage circuit are read out at the next clock rising edge, so that conversion from the thermometer codes to the binary codes is realized.

Example 2

FIG. 1 is a schematic diagram of a thermometer code to binary code circuit. The circuit mainly comprises two parts: LUT screening circuit and RAM memory circuit. The former functions to filter the bubble code segments in the thermometer code, and the latter functions to convert the thermometer code into binary code.

The specific process is as follows: first, the thermometer code is input to the LUT screening circuit, the bubble code segment is "filtered" by logical operation, and the read enable signal is output. Then, the read enable signal is input to the RAM storage circuit to control reading of the binary code, and the decoding process is completed.

FIG. 2 is a circuit diagram of thermometer code to binary code conversion. The LUT screening circuit is composed of LUT resources in the FPGA. The LUT is essentially a static random access memory with 6 bit address lines, 64 depths and 1bit width, which can realize the combinational logic operation with no more than 6 bit input, and the principle of realizing the logic function is as follows: and storing all possible results of the logic function into the LUT, wherein the input of the logic function is used as an address line to control the LUT to output a corresponding logic value.

In the present invention, the thermometer code is logically processed using the LUT to filter out "bubble" code segments. The specific implementation process comprises the following steps:

in the n-bit thermometer code tap [ n-1:0], each adjacent 6 bits are sequentially input into the corresponding LUT from the 0 th bit to the highest bit. For example, tap [0], tap [1], tap [2], tap [3], tap [4] and tap [5] are connected to the inputs of LUT0, tap [1], tap [2], tap [3], tap [4], tap [5] and tap [6] are connected to the inputs of LUT1, and so on, up to tap [ n-1 ].

The implementation logic inside the LUT is shown in fig. 3. The high 5 bits of the input signal are inverted respectively, and then the inverted result is anded with the lowest bit. For example, in LUT0, tap [1], tap [2], tap [3], tap [4] and tap [5] are inverted, respectively, and then the inverted result and tap [0] are logically ANDed; in LUT1, tap [2], tap [3], tap [4], tap [5] and tap [6] are inverted, and the inverted result and tap [1] are logically ANDed, and so on.

FIG. 4 is a schematic view of a thermometer code. The time information measured by the time-to-digital converter is contained in the most significant bit 01 alternation position of the thermometer code, and the code segment at the most significant bit 01 alternation position is characterized in that: the lowest order is 1 and the high orders are 0. Through the logic, the LUT screening circuit can uniquely identify the 000001 code segment, only outputs logic 1 on the LUT taking the 000001 code segment as input, and other LUTs output logic 0, so that the corresponding RAM can read binary numbers, and the influence of 'bubbling' code segments on the decoding process is avoided.

For example, when a thermometer code has a 1-bit "bubble", as in … 0000001011111, the LUT screening circuit enables the RAM6 to read out binary number 7 by detecting a 000001 code segment, causing LUT6 to output a logic 1 and the other LUTs to output a logic 0. Similarly, when 2-bit, 3-bit and 4-bit bubbles appear in the thermometer code, compared with … 0000001001111, … 0000001000111 and … 0000001000011, the LUT screening circuit filters out 2-bit, 3-bit and 4-bit bubble bits in the thermometer code by detecting 000001 code segments, so that LUT6 outputs logic 1, and other LUTs output logic 0, so that the RAM6 reads out binary number 7. If the thermometer code has 5 bubble bits, for example … 0000001000001, LUT0 and LUT1 will output logic 1 at the same time, thus enabling RAM0 and RAM1 to read binary data at the same time, resulting in contention on the bus and resulting in decoding error. Therefore, the invention can realize correct decoding of thermometer codes with 4 bubble bits at most.

Fig. 5 shows a specific structure of the RAM cell. The RAM unit in the invention has read-only property and is realized by using a distributed RAM in FPGA. The RAM units are not interfered with each other and cannot be in a read state at the same time so as to avoid competing bus resources. Through parameterization configuration, each RAM is configured to have the depth of 1 and the width of 8, and decimal numbers of 0-255 can be stored. By initializing the memory, the binary code corresponding to the thermometer code is stored in the RAM, wherein the RAM0 stores 1, the RAM1 stores 2, the RAM2 stores 3, and so on. The output signals en _ rd _0, en _ rd _1, en _ rd _2 and the like of each LUT are used as enabling signals to be accessed to the read enabling end of the corresponding RAM. For example, en _ rd _0 accesses the read enable of RAM0, en _ rd _1 accesses the read enable of RAM1, en _ rd _2 accesses the read enable of RAM2, and so on. If the read enable signal of a certain RAM is logic 1, when the rising edge of the clock comes, the stored binary number is read out to realize the conversion from the thermometer code to the binary code, otherwise, the output is forbidden, and the bus idle state is kept.

In conclusion, the thermometer code to binary code circuit designed by the invention fully utilizes abundant configurable logic resources in the FPGA, can realize correct decoding of the thermometer code with 4 bubbling bits at most by detecting the 000001 code segment, and has strong fault-tolerant capability. The thermometer code is converted into the binary code by reading the RAM, the whole decoding process can be completed by only one clock period, the decoding speed is increased, and the integral measuring speed of the clock digital converter is increased.

In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.

Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (2)

1. A thermometer code to binary code circuit for a time to digital converter, the circuit comprising: an LUT screening circuit and a RAM memory circuit,

the thermometer code is used as an input signal and is accessed into an LUT screening circuit, and each adjacent 6 bits are sequentially input into a corresponding LUT from the 0 th bit to the highest bit of an LUT unit in the screening circuit; the LUT screening circuit only outputs logic 1 on the LUT taking 000001 code segment as input, and the other LUTs output logic 0, thereby enabling the corresponding RAM to read binary number; and the output signal is used as a control signal to be accessed to a read enabling end of the RAM storage circuit;

when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized.

2. The thermometer code to binary code circuit for a time-to-digital converter of claim 1, further comprising: and storing the binary codes corresponding to the thermometer codes into a RAM storage circuit.

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