CN114884510A - SAR ADC circuit of low bit error rate - Google Patents
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Abstract
The invention discloses a SAR ADC circuit with low bit error rate, comprising: the SAR control circuit comprises a capacitor DAC array, a comparator and an SAR logic circuit which are connected in sequence, wherein the SAR logic circuit generates an enabling signal of the comparator and a control signal of the capacitor DAC array; the SAR logic circuit comprises M bit processing units and M corresponding DFF units, wherein M is more than or equal to 3 and is a positive integer; each bit processing unit is respectively connected with the comparator, the capacitor DAC array and the sampling clock CKS; the DFF unit connects each of the bit processing units and a sampling clock CKS. The invention can avoid the error rate problem caused by the metastable state of the comparator being mistakenly identified by subsequent logic, and reduce the error probability, thereby meeting the ADC application requirement of a low-error-rate system.
Description
Technical Field
The invention relates to a SAR ADC circuit.
Background
Compared with an analog-to-digital converter (ADC) with other structures, the successive approximation type (SAR) ADC has the advantages of small area, low power consumption, simple structure, low delay and the like, and is widely applied to the current communication system, MCU (microprocessor) and sensors. Due to the characteristic of successive approximation, the N-bit SAR ADC needs to perform at least N comparisons, and each comparison may cause a logic error due to the metastable state of the comparator, so that the ADC outputs a large error, which is unacceptable in a system with a high requirement on the error rate.
In an asynchronously clocked SAR ADC, the comparator clock is generated by the clock generation module of the ADC. The clock generating module generates the clock of the comparator module through logic delay according to the output result of the comparator, so once the comparator has a definite output result, because the logic delay is fixed, each bit of the SAR ADC can be ensured to obtain the same DAC (digital to analog converter) establishing time, and the DAC is already established to the required precision before the comparator of the next bit enables. In contrast, the period of each bit of the synchronization timing sequence is fixed, once the input signal is very small, the comparison time of the comparator is prolonged, which results in occupying DAC setup time, and even logic disorder, which results in a large error of the ADC output. Asynchronous timing is therefore more structurally suited to low bit error rate applications. However, under the condition of high requirement on the error rate, when the input of the comparator is extremely low, the comparator inevitably generates a metastable state, so that the positive/negative output ends of the comparator are at the output common mode level of the comparator, and the subsequent SAR logic is triggered by mistake, so that the ADC outputs a large error code. Optimizing the comparator itself can alleviate this problem to some extent, but at the cost of a severely reduced comparator speed.
Disclosure of Invention
The invention aims to provide an SAR ADC circuit with a low error rate, which can avoid the error rate problem caused by the fact that the metastable state of a comparator is mistakenly identified by subsequent logic and reduce the error probability.
The technical scheme for realizing the purpose is as follows:
a low bit error rate SAR ADC circuit, comprising: the device comprises a capacitor DAC array, a comparator and an SAR logic circuit which are connected in sequence, wherein,
the SAR logic circuit generates an enabling signal of the comparator and a control signal of the capacitor DAC array;
the SAR logic circuit comprises M bit processing units and M corresponding DFF units, wherein M is more than or equal to 3 and is a positive integer;
each bit processing unit is respectively connected with the comparator, the capacitor DAC array and the sampling clock CKS;
the DFF (D flip-flop) unit connects each of the bit processing units and a sampling clock CKS.
Preferably, the SAR logic circuit further comprises an asynchronous clock generation circuit,
the asynchronous clock generating circuit is connected with the comparator and the sampling clock CKS;
respective MO ends of the M bit processing units are sequentially connected to an MI end of a next bit processing unit, and respective RO ends of the M bit processing units are sequentially connected to an RI end of the next bit processing unit; the MI end of the first bit processing unit is connected to the '0' potential, and the RI end of the first bit processing unit is connected to the sampling clock CKS; the MO end of the last bit processing unit is connected with one input end of a third NAND gate through a second NOT gate; the RO end of the last bit processing unit is connected with the other input end of the third NAND gate; the output end of the third NAND gate is connected with the asynchronous clock generating circuit through the third NOT gate.
Preferably, the asynchronous clock generation circuit comprises a first not gate, a first nand gate, a second nand gate and a delay unit;
the input end of the first NOT gate is connected with a sampling clock CKS;
two input ends of the first NAND gate are connected with the comparator;
the output end of the first NOT gate, the output end of the first NAND gate and the output end of the third NOT gate are respectively connected with three input ends of the second NAND gate;
the output end of the second NAND gate is connected with the input end of the delay unit;
and the output end of the delay unit is connected with the comparator.
Preferably, the bit processing unit includes: a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a tenth not gate, a fourth not gate, a fifth not gate, an exclusive nor gate, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, a sixth nor gate, a seventh nor gate, a first latch, a second latch, and a delay, wherein,
the MI end of the bit processing unit is connected with the first input ends of the fourth NOR gate and the sixth NOR gate respectively; the Q end of the bit processing unit is connected with the D end of the first latch; the CKS end of the bit processing unit is connected with the respective SET ends of the first latch and the second latch, and simultaneously connected with the first input end of the third NOR gate and the second input end of the seventh NOR gate; the QB end of the bit processing unit is connected with the D end of the second latch; the RI end of the bit processing unit is connected with the first input end of the seventh NOR gate; the MO end of the bit processing unit is connected with the output end of the fourth NOT gate; the D end of the bit processing unit is connected with the output end of the sixth NOR gate; the RO end of the bit processing unit is connected with the output end of the time delay unit;
two input ends of the exclusive-OR gate are respectively connected with respective Q ends of the first latch and the second latch, and an output end of the exclusive-OR gate is connected with a first input end of the first NOR gate;
the second input end of the first NOR gate is connected with the output end of the time delay unit, and the output end of the first NOR gate is connected with the second input end of the second NOR gate;
the first input end of the second NOR gate is connected with the output end of the third NOR gate;
a second input end of the third NOR gate is connected with an output end of the second NOR gate;
the output end of the fourth NOR gate is connected with the input end of the fourth NOR gate, the second input end of the fourth NOR gate is connected with the output end of the third NOR gate,
a first input end of the fifth nor gate is connected with an output end of the third nor gate, a second input end of the fifth nor gate is connected with a Q end of the first latch, and an output end of the fifth nor gate is connected with a second input end of the sixth nor gate;
two input ends of the fourth NAND gate are respectively connected with the respective Q ends of the first latch and the second latch, and the output end of the fourth NAND gate is connected with the input end of the fifth NOT gate;
the output end of the fifth NOT gate is connected with the input end of the time delay unit;
a first input end of the fifth nand gate is connected with an output end of the fifth not gate, a second input end of the fifth nand gate is connected with an output end of the seventh nor gate, and an output end of the fifth nand gate is connected with an input end of the tenth not gate;
the output end of the tenth NOT gate is connected with the respective EN ends of the first latch and the second latch;
and the Q end and the Q reverse end of each of the first latch and the second latch are respectively connected with the capacitor DAC array through the sixth NOT gate, the seventh NOT gate, the eighth NOT gate and the ninth NOT gate.
The invention has the beneficial effects that: the invention adds the metastable state detection and error correction logic on the logic path, which can not reduce the conversion speed of the ADC, and once the metastable state of the comparator is identified, the output code of the comparator can be identified and corrected in the current conversion period, and the metastable state of the metastable state detection circuit is not required to be alleviated by additionally beating one beat, thus no extra time delay is generated on the output of the ADC. Thereby alleviating the ADC error rate problem caused by the metastable state of the comparator.
Drawings
FIG. 1 is a circuit diagram of a low bit error rate SAR ADC circuit of the present invention;
FIG. 2 is a block diagram of a SAR ADC;
FIG. 3 is a circuit diagram of a bit processing unit of the present invention;
fig. 4 is a schematic diagram of the normal operation timing of the SAR ADC of the present invention.
Detailed Description
The invention will be further explained with reference to the drawings.
As shown in fig. 2, the SAR ADC block diagram is mainly composed of a capacitor DAC array, a comparator, and a SAR logic circuit. Taking a 4-bit SAR ADC as an example, in the sampling stage of the ADC, the capacitor DAC array samples input signals Vin + and Vin-into the capacitor DAC array, the SAR logic circuit generates an enabling signal of the comparator, the comparator starts the judgment of bit3, the output result is output into the SAR logic circuit, the SAR logic circuit changes a DAC array switch corresponding to bit3 according to the output result of the comparator, and the DAC is reestablished. Then the period of bit2 begins: the SAR logic circuit generates an enabling signal of the comparator, the comparator compares the enabling signal, the SAR logic circuit changes the DAC array switch corresponding to bit2 according to the output of the comparator, and the DAC is reestablished. After bit1 and bit0 also complete conversion, the SAR logic circuit outputs the stored 4-bit comparator results after the sampling clock is synchronized.
Referring to fig. 1, the low-bit-error-rate SAR ADC circuit of the present invention includes: the device comprises a capacitor DAC array (DAC array), a comparator and a SAR logic circuit (SAR logic) which are connected in sequence.
The SAR logic circuit generates an enable signal of the comparator and a control signal of the capacitor DAC array.
The SAR logic circuit comprises M bit processing units and corresponding M DFF units L7, wherein M ≧ 3 and is a positive integer. Each bit processing unit is respectively connected with the comparator, the capacitor DAC array and the sampling clock CKS. The DFF unit L7 connects each bit processing unit and the sampling clock CKS. In the figure, a 5-bit SAR ADC is taken as an example for illustration, the number of bits of the ADC can be increased without an upper limit, the number of bits can be reduced to 3 bits, and then the SAR ADC is reduced to be no longer dominant, and other structures are generally adopted. The logic cores in the figure are bit processing units L2-L6. Wherein the circuitry of the bit processing unit is shown in fig. 3.
The SAR logic circuit comprises a K1 module and a K2 module, wherein the K1 module is an asynchronous clock generation circuit. The asynchronous clock generation circuit is connected to the comparator and the sampling clock CKS.
In the K2 module, the MO end of each of M bit processing units L2-L6 is connected to the MI end of the next bit processing unit in sequence, and the RO end of each of M bit processing units L2-L6 is connected to the RI end of the next bit processing unit in sequence; the MO terminal of the last bit processing unit L6 is connected to an input terminal of a third nand gate N2 through a second not gate N1; the RO end of the last bit processing unit L6 is connected with the other input end of the third NAND gate N2; the output of the third nand gate N2 is connected to the asynchronous clock generating circuit through a third not gate N3.
The asynchronous clock generation circuit comprises a first NOT gate I1, a first NAND gate I4, a second NAND gate I2 and a delay unit I3. The input end of the first NOT gate I1 is connected with the sampling clock CKS; two input ends of the first NAND gate I4 are connected with the Q end and the QB end of the comparator L0; the output end of the first not gate I1, the output end of the first NAND gate I4 and the output end of the third not gate N3 are respectively connected with three input ends of a second NAND gate I2; the output end of the second NAND gate I2 is connected with the input end of the delay unit I3; the output terminal of the delay unit I3 is connected to the comparator L0, and outputs an enable signal CMP _ EN.
The bit processing unit includes: a fourth not gate I19, a fifth not gate I22, a sixth not gate I26, a seventh not gate I27, an eighth not gate I28, a ninth not gate I29, a tenth not gate I30, a fourth nand gate I21, a fifth nand gate I24, an exclusive or gate I13, a first nor gate I14, a second nor gate I15, a third nor gate I16, a fourth nor gate I17, a fifth nor gate I18, a sixth nor gate I20, a seventh nor gate I25, a first latch I11, a second latch I12, and a delay I23.
The MI end of the bit processing unit is connected with the first input ends of a fourth NOR gate I17 and a sixth NOR gate I20; the Q end of the bit processing unit is connected with the D end of the first latch I11; the CKS terminal of the bit processing unit is connected with the SET terminals of the first latch I11 and the second latch I12 respectively, and is simultaneously connected with the first input terminal of the third NOR gate I16 and the second input terminal of the seventh NOR gate I25; the QB end of the bit processing unit is connected with the D end of the second latch I12; the RI end of the bit processing unit is connected with the first input end of a seventh NOR gate I25; the MO end of the bit processing unit is connected with the output end of the fourth NOT gate I19; the D end of the bit processing unit is connected with the output end of the sixth NOR gate I20; the RO end of the bit processing unit is connected with the output end of the time delay I23;
two input ends of an exclusive-nor gate I13 are respectively connected with the Q ends of a first latch I11 and a second latch I12, and the output end of the exclusive-nor gate I14 is connected with a first input end; a second input end of the first NOR gate I14 is connected with the output end of the time delay I23, and an output end of the first NOR gate I15 is connected with a second input end of the second NOR gate I15; a first input end of the second NOR gate I15 is connected with an output end of the third NOR gate I16; a second input end of the third NOR gate I16 is connected with the output end of the second NOR gate I15; an output end of a fourth NOR gate I17 is connected with an input end of the fourth NOR gate I19, a second input end of the fourth NOR gate I3878 is connected with an output end of the third NOR gate I16, a first input end of a fifth NOR gate I18 is connected with an output end of a third NOR gate I16, a second input end of the fifth NOR gate I18 is connected with a Q end of a first latch I11, and an output end of the fifth NOR gate I18 is connected with a second input end of a sixth NOR gate I20; two input ends of a fourth nand gate I21 are respectively connected to the Q ends of the first latch I11 and the second latch I12, and the output end is connected to the input end of the fifth not gate I22; the output end of the fifth NOT gate I22 is connected with the input end of the time delay I23; a first input end of a fifth NAND gate I24 is connected with the output end of the fifth NOT gate I22, a second input end of the fifth NAND gate I24 is connected with the output end of a seventh NOR gate I25, and the output end of the fifth NAND gate I3878 is connected with the input end of the tenth NOT gate I30;
the output end of the tenth NOT gate I30 is connected to the respective EN ends of the first latch I11 and the second latch I12; the Q terminal and the Q inverted terminal of each of the first latch I11 and the second latch I12 are connected to the capacitor DAC array through the sixth not gate I26, the seventh not gate I27, the eighth not gate I28 and the ninth not gate I29, respectively.
The following description of the operation will be made by combining the circuit diagrams of fig. 1 and 3 and the timing chart of fig. 4.
In the sampling phase of the ADC, the sampling clock CKS =1, the enable signal CMP _ EN =0 of the comparator, and the comparator output is reset to Q = QB = 1. After sampling is completed, the clock CKS =0, the clock generation circuit generates a high level of CMP _ EN after delaying, the comparator starts to compare to obtain Q and QB, and the 2 output signals change from the reset state Q = QB =1 to Q =1, QB =0 or Q =0, QB = 1. For bit-processing unit L2, MI =0, RI = CKS =0, bit5 corresponding to the bit-processing unit is enabled, in fig. 3, WEN =1, and the first latch I11 and the second latch I12 respectively latch Q, QB, obtaining the output Q +, Q-of the latch. At least one of Q + and Q-is 0, so WEN =0, and after the delay of I23, let RO =0, i.e. R <4> =0 in fig. 1, as can be seen from the logic in fig. 3, R <4> =0, which triggers the bit processing unit of bit4 to enable; after the values of Q + and Q-are determined, the values of SWBP <4>, SWP <4>, SWN <4> and SWBN <4> are changed through NOT gates I26-I29, so that the corresponding switches of the DAC are changed, after the DAC is built, the SAR logic completes the conversion of bit4, and the conversion of bit3 is started. The conversion process of Bit3 is the same as Bit4, the comparator receives the enable signal and then compares the enable signal to obtain Q, QB, the Bit processing unit L3 latches the output result of the comparator and outputs M <3>, R <3>, SWBP <3>, SWP <3>, SWN <3> and SWBN <3 >. Similarly, bit 2-bit 0. Then DFF unit L7<4:0> synchronizes the output result of the latch with CKS clock and then takes it as the output signal DOUT <4:0> of ADC.
When the comparator metastability occurs, assuming it occurs at bit4, the comparator cannot output a clean output signal late under the enable signal of CMP _ EN, Q, QB is near its common mode level VDD/2, so that both latches of L2 are misidentified as 0, i.e., Q + = Q- =0, and R <4> =0 is output. It can be seen that at this time, an abnormality has occurred in the signal path, and actually the comparator is still in the process of comparison, and the logic circuit mistakenly believes that the comparator has obtained a result, and has started to go down to reset the comparator. Note that when the comparator has the above metastable state, the xor output NXOR of the exclusive nor gate I13 of the bit processing unit L2 changes from 0 to 1 under normal conditions, and is latched by the SR latch formed by the second nor gate I15 and the third nor gate I16 and then output to the fifth nor gate I18, one input end of the fifth nor gate I18 is 1, the output is 0, and then the D <4> is forced to 1 through the sixth nor gate I20 whose 2 inputs are 0; while M <4> = 1. For the bit-processing unit L3 of the next bit, one of the inputs M <4> =1 of the sixth nor gate I20 such that D <3> = 0. The same reason can be found that D <2> = D <1> = D <0> = 0. Since the input signal is already very close to the quantization value corresponding to D <4:0> =10000 when the comparator processes the metastability, the processing error for D <4:0> is much less than 1lsb (least Significant bit). Therefore, the logic circuit corrects the logic error caused by the metastable state of the comparator, avoids the error code generated by the error and effectively improves the error rate of the SAR ADC. Note that M <4> =1 will be passed from I17, I19 all the way to M <0> to generate the end-of-transition signal LATCH _ STOP, which is typically less than the delay of I3, so the SAR logic STOPs bit4 and the transition down immediately after bit5 becomes metastable, waiting for the next ADC sample.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.
Claims (4)
1. A low bit error rate SAR ADC circuit, comprising: the device comprises a capacitor DAC array, a comparator and an SAR logic circuit which are connected in sequence, wherein,
the SAR logic circuit generates an enabling signal of the comparator and a control signal of the capacitor DAC array;
the SAR logic circuit comprises M bit processing units and M corresponding DFF units, wherein M is more than or equal to 3 and is a positive integer;
each bit processing unit is respectively connected with the comparator, the capacitor DAC array and the sampling clock CKS;
the DFF unit connects each of the bit processing units and a sampling clock CKS.
2. The low bit error rate SAR ADC circuit of claim 1, wherein the SAR logic circuit further comprises an asynchronous clock generation circuit,
the asynchronous clock generating circuit is connected with the comparator and the sampling clock CKS;
respective MO ends of the M bit processing units are sequentially connected to an MI end of a next bit processing unit, and respective RO ends of the M bit processing units are sequentially connected to an RI end of the next bit processing unit; the MI end of the first bit processing unit is connected to the 0 potential; the RI end of the first bit processing unit is connected to a sampling clock CKS; the MO end of the last bit processing unit is connected with one input end of a third NAND gate through a second NOT gate; the RO end of the last bit processing unit is connected with the other input end of the third NAND gate; the output end of the third NAND gate is connected with the asynchronous clock generating circuit through the third NOT gate.
3. The low bit error rate SAR ADC circuit of claim 2, wherein the asynchronous clock generation circuit comprises a first not gate, a first nand gate, a second nand gate, and a delay unit;
the input end of the first NOT gate is connected with a sampling clock CKS;
two input ends of the first NAND gate are connected with the comparator;
the output end of the first NOT gate, the output end of the first NAND gate and the output end of the third NOT gate are respectively connected with three input ends of the second NAND gate;
the output end of the second NAND gate is connected with the input end of the delay unit;
and the output end of the delay unit is connected with the comparator.
4. The low bit error rate SAR ADC circuit of claim 1, wherein the bit processing unit comprises: a fourth not gate (I19), a fifth not gate (I22), a sixth not gate (I26), a seventh not gate (I27), an eighth not gate (I28), a ninth not gate (I29), a tenth not gate (I30), a fourth not gate (I21), a fifth not gate (I24), an exclusive-or gate (I13), a first NOR gate (I14), a second NOR gate (I15), a third NOR gate (I16), a fourth NOR gate (I17), a fifth NOR gate (I18), a sixth NOR gate (I20), a seventh NOR gate (I25), a first latch (I11), a second latch (I12) and a time delay (I23), wherein,
the MI end of the bit processing unit is connected with the first input ends of the fourth NOR gate (I17) and the sixth NOR gate (I20); the Q end of the bit processing unit is connected with the D end of the first latch (I11); the CKS terminal of the bit processing unit is connected with the SET terminals of the first latch (I11) and the second latch (I12), and is simultaneously connected with the first input terminal of the third NOR gate (I16) and the second input terminal of the seventh NOR gate (I25); the QB end of the bit processing unit is connected with the D end of the second latch (I12); the RI end of the bit processing unit is connected with the first input end of a seventh NOR gate (I25); the MO end of the bit processing unit is connected with the output end of the fourth NOT gate (I19); the D end of the bit processing unit is connected with the output end of the sixth NOR gate (I20); the RO end of the bit processing unit is connected with the output end of the time delay unit (I23);
two input ends of the exclusive-nor gate (I13) are respectively connected with the Q ends of a first latch (I11) and a second latch (I12), and an output end of the exclusive-nor gate is connected with a first input end of the first NOR gate (I14);
a second input end of the first NOR gate (I14) is connected with the output end of the time delay unit (I23), and an output end of the first NOR gate is connected with a second input end of the second NOR gate (I15);
a first input terminal of the second NOR gate (I15) is connected with an output terminal of the third NOR gate (I16);
a second input terminal of the third NOR gate (I16) is connected with an output terminal of the second NOR gate (I15);
an output of the fourth NOR gate (I17) is connected to an input of the fourth NOR gate (I19), a second input is connected to an output of the third NOR gate (I16),
the first input end of the fifth NOR gate (I18) is connected with the output end of the third NOR gate (I16), the second input end of the fifth NOR gate is connected with the Q end of the first latch (I11), and the output end of the fifth NOR gate is connected with the second input end of the sixth NOR gate (I20);
two input ends of the fourth NAND gate (I21) are respectively connected with the Q ends of the first latch (I11) and the second latch (I12), and the output end of the fourth NAND gate is connected with the input end of the fifth NOT gate (I22);
the output end of the fifth NOT gate (I22) is connected with the input end of the time delay unit (I23);
the first input end of the fifth NAND gate (I24) is connected with the output end of the fifth NOT gate (I22), the second input end of the fifth NAND gate is connected with the output end of the seventh NOR gate (I25), and the output end of the fifth NAND gate is connected with the input end of the tenth NOT gate (I30);
an output terminal of the tenth not-gate (I30) is connected to EN terminals of the first latch (I11) and the second latch (I12), respectively;
the Q end and the Q reverse end of each of the first latch (I11) and the second latch (I12) are respectively connected with the capacitor DAC array through the sixth NOT gate (I26), the seventh NOT gate (I27), the eighth NOT gate (I28) and the ninth NOT gate (I29).
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