CN114374391B - High-speed SAR ADC circuit - Google Patents
High-speed SAR ADC circuit Download PDFInfo
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- CN114374391B CN114374391B CN202210044030.7A CN202210044030A CN114374391B CN 114374391 B CN114374391 B CN 114374391B CN 202210044030 A CN202210044030 A CN 202210044030A CN 114374391 B CN114374391 B CN 114374391B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The invention discloses a high-speed SAR ADC circuit, which comprises: the device comprises a capacitor DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit, wherein the REF circuit is connected with the capacitor DAC array; the capacitor DAC array is connected with two input ends of the comparator; the comparator is connected with the clock logic circuit and the data logic circuit; the clock logic circuit outputs a comparator clock to the comparator; the data logic circuit outputs DAC control signals to the capacitor DAC array; the data logic circuit is additionally provided with M-bit DFF units on the basis of N-bit DFF units, and is additionally provided with M-bit data processing units on the basis of N-bit data processing units, wherein N, M are positive integers. According to the invention, the speed and the performance of the asynchronous SAR ADC can be kept stable under PVT by automatically adjusting the circuit delay and the current of the reference voltage circuit, and the power consumption is reduced.
Description
Technical Field
The present invention relates to a Successive Approximation (SAR) analog-to-digital converter (ADC).
Background
Successive approximation type analog-to-digital converters are widely used due to the low power consumption and low delay of the successive approximation type analog-to-digital converters, but due to the characteristic of successive approximation, the SAR ADC with the resolution of N bits needs at least N conversion periods, so that the speed is low. Although the speed of the asynchronous sequential SAR ADC is improved, in actual design, the total time of N conversion periods varies greatly with PVT (Process, voltage, temperature) Corner, and the speeds are easily doubled at the fastest and slowest PVT corners, and in conventional design, the driving capability of the delay unit and the reference level driving circuit is set at the slowest Corner, so that the reference level driving circuit of the Typical (standard Process Corner) and the faster Corner is over-designed, resulting in larger power consumption of the SAR ADC.
Disclosure of Invention
The invention aims to provide a high-speed SAR ADC circuit, which can keep the speed and the performance of an asynchronous SAR ADC stable under PVT and reduce the power consumption by automatically adjusting the circuit delay and the current of a reference voltage circuit.
The technical scheme for achieving the purpose is as follows:
a high speed SAR ADC circuit comprising: a capacitor DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit,
The REF circuit is connected with the capacitor DAC array;
the capacitor DAC array is connected with two input ends of the comparator;
The comparator is connected with the clock logic circuit and the data logic circuit;
the clock logic circuit outputs a comparator clock to the comparator;
The data logic circuit outputs DAC control signals to the capacitor DAC array;
The data logic circuit is provided with an additional M-bit DFF unit based on the N-bit DFF unit, and an additional M-bit data processing unit based on the N-bit data processing unit, wherein N, M are positive integers.
Preferably, each DFF unit is connected to a corresponding data processing unit;
the data logic circuit comprises a delay control module for receiving a sampling clock CKS;
The M-bit output of the M-bit DFF unit is connected with the input end of the delay control module;
Each bit of the data processing unit is connected with the comparator;
the capacitor DAC control output CTL end of the N-bit data processing unit is connected with the capacitor DAC array;
the delay control module is respectively connected with the REF circuit and the clock logic circuit.
Preferably, the clock logic circuit comprises an NOT gate, a first NOT gate, a second NOT gate and a delay unit;
The input end of the NOT gate is connected with a sampling clock CKS;
Two input ends of the first NAND gate are connected with the comparator;
The output end of the first NAND gate is connected with an N+M bit DFF unit;
The common connection end of the output end of the NOT gate, the output end of the first NOT gate and the M-bit DFF unit is connected with the three input ends of the second NOT gate;
The output end of the second NAND gate is connected with the input end of the delay unit;
the output end of the delay unit is connected with the comparator;
the delay unit is connected with the delay control module.
Preferably, the sampling clock CKS is connected to the n+m-bit DFF unit through two connected not gates on the one hand, and to one input terminal of the and gate subordinate to the first-bit DFF unit through one not gate on the other hand, and to the other input terminal of the and gate subordinate to the first-bit DFF unit; the output end of the AND gate belonging to the first bit DFF unit is connected with a corresponding data processing unit;
the two input ends of the AND gates of the other DFF units except the first bit are respectively connected with the subordinate DFF unit and the former DFF unit, and the output ends are connected with the corresponding data processing units.
Preferably, the method further comprises: a data calculation unit and an output DFF unit;
the data calculation unit is respectively connected with the delay control module, the sampling clock CKS and the N+M bit data processing unit;
The DFF unit is connected to the data computing unit and to the sampling clock CKS through a not gate.
Preferably, the REF circuit includes: current DAC and REF buffer,
The Current DAC is connected with the delay control module and the REF buffer;
the REF buffer is connected with the capacitor DAC array.
The beneficial effects of the invention are as follows: the invention automatically adjusts the delay and the current of the reference level driving circuit according to different Corner where the chip is located. The state of the current SAR ADC is detected by inserting additional conversion bits, the number of the additional conversion bits can be used as a conversion time allowance, and the requirements of different systems on the SAR ADC error rate and the robustness can be met by only adjusting the number of the conversion bits. Compared with the traditional method that the Current of the delay unit and the Current of the reference level driving circuit are set to the slowest counter, the default gear is set under the PVT type nominal counter, the delay of the delay unit is reduced under the slowest counter to speed up, the bias Current of the reference level driving circuit is increased through the Current DAC, and the capacitor DAC establishment time in the SAR ADC is shortened; the purpose of saving power consumption is achieved by increasing the delay of the delay unit and reducing the bias Current of the reference level driving circuit by the Current DAC under a slow counter. The slowest PVT Corner has small statistical duty ratio, and the method for automatically adjusting the delay and the current can effectively achieve the purpose of saving power consumption on the premise of meeting the high-speed application. Finally, the invention counts the data output of the extra conversion bit, can play a role in improving SAR ADC noise, relieves the problem of compromise of the comparator on high-speed application speed and noise performance, and effectively improves the speed of the whole SAR ADC.
Drawings
FIG. 1 is a circuit diagram of a high-speed SAR ADC circuit of the present subject matter;
FIG. 2 is a block diagram of a SAR ADC of the present invention;
FIG. 3 is a timing block diagram of a 5-bit asynchronous SAR ADC according to the present invention
Fig. 4 is a high-speed SAR ADC operation flow diagram in accordance with the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Fig. 2 is a block diagram of a SAR ADC, which is mainly composed of a capacitor DAC (Digital to Analog converter, digital-to-analog converter) array, a comparator, a REF circuit (reference level driving circuit), a clock logic circuit, and a data logic circuit. The REF circuit is connected with the capacitor DAC array; the capacitor DAC array is connected with two input ends of the comparator; the comparator is connected with the clock logic circuit and the data logic circuit; the clock logic circuit outputs a comparator clock cmp_en to the comparator; the data logic circuit outputs a DAC control signal DAC_CTL to the capacitor DAC array.
Fig. 3 is a timing block diagram for an example of a 5-bit asynchronous SAR ADC. In the sampling phase of the ADC, the sampling clock CKS is high level, and the capacitor DAC array samples the input signal Vin+ and Vin-into the capacitor DAC array. During the transition phase, CKS low, the clock logic generates the comparator clock cmp_en one by one. In the 5 bit asynchronous SAR ADC of fig. 3, cmp_en generates 5 high levels, wherein the high level time of cmp_en is different due to the difference in comparison time of each comparator. Bit <4>, bit <3> clock loops and data loops are illustrated in FIG. 3. Wherein clock loop refers to the loop from the comparator to the clock logic in fig. 2, which is fed back to the comparator via the comparator clock cmp_en; the DAC loop refers to the loop from the capacitive DAC array to the comparator to the data logic in fig. 2, which is finally fed back to the capacitive DAC array by the DAC control signal dac_ctl. The clock loop of bit <4> in FIG. 3 starts from the rising edge of bit <4> of cmp_en, the comparator starts to compare, and the comparison result generates the falling edge of cmp_en through the logic delay of the clock logic module; the comparator starts to reset at the falling edge of cmp_en, after the reset is completed, clock logic is passed through, the delay is 'logic delay 2' of fig. 3, the rising edge of cmp_en is triggered, and the period of bit <3> is started. On the DAC loop, when the bit <4> rising edge of cmp_en means that the DAC has been established, changing the control signal of the DAC through a data logic circuit (the delay of which is the data delay in FIG. 3) after the comparator result is obtained, starting the DAC to establish the bit-3 DAC in FIG. 3; to achieve better SAR ADC performance, it is required that Bit-3 DAC be established before the Bit <3> high rising edge of cmp_en. The conversion speed of an asynchronous SAR ADC is directly dependent on the speed of the clock loop, i.e. cmp_en is to complete the complete 5 cycles. Its components include the "bit-n comparator setup" of fig. 3, the "logic delay 1", the "comparator reset", the "logic delay 2". The delay of these 4 parts is different at different burners.
As shown in fig. 1, the high-speed SAR ADC circuit of the present invention comprises: a capacitive DAC array, a comparator, a REF circuit, a clock logic circuit, and a data logic circuit. In the figure, the K1 block corresponds to a clock logic circuit. The K2 plus K3 module corresponds to a data logic circuit. The K4 module corresponds to the REF circuit.
The data logic circuit adds an additional M-bit DFF (D flip-flop) unit (corresponding to 3-bit DFF of I11-I13 in FIG. 1) on the basis of the N-bit DFF units (I6-I10), and simultaneously adds an additional M-bit data processing unit (corresponding to L7-L9 in FIG. 1) on the basis of the N-bit data processing units (L2-L6), wherein N, M are all positive integers.
Each bit of DFF unit is connected with a corresponding data processing unit. The data logic circuit includes a delay control module (delay control) L10 that receives the sampling clock CKS. The common connection end of the M-bit DFF units I11-I13 is connected with the input end of the delay control module L10. Each data processing unit is connected with the Q end and the QB end of the comparator Lx. The DAC control terminals (CTL terminals) of the N-bit data processing units L2-L6 are connected with corresponding capacitors in the capacitor DAC array. Delay control module L10 is connected to the REF circuit and the clock logic circuit, respectively.
The clock logic circuit includes an not gate I1, a first nand gate I4, a second nand gate I2, and a delay cell (delay dac) L0. The input of the NOT gate I1 is connected with a sampling clock CKS. Two input ends of the first NAND gate I4 are connected with the Q end and the QB end of the comparator Lx. The output end of the first NAND gate I4 is connected with the CK end of the N+M bit DFF unit. The common interface (Q-terminal) of the output of the not gate I1, the output of the first nand gate I4 and the M-bit DFF units I11-I13 is connected to the three inputs of the second nand gate I2. The output end of the second NAND gate I2 is connected with the input end of the delay unit L0. The output end of the delay unit L0 is connected with the comparator Lx. The delay unit L0 is connected to the delay control module L10 and receives the control signal d_dac_ctl.
The sampling clock CKS is connected with the rst ends of the N+M bit DFF units through two connected NOT gates, and is connected with one input end of an AND gate subordinate to the first bit DFF unit I6 through a NOT gate, and is connected with the Q opposite end of the first bit DFF unit I6 through the other input end of the AND gate subordinate to the first bit DFF unit I6; the output of the and gate belonging to the first bit DFF unit I6 is connected to the EN terminal of the corresponding data processing unit L2. The two input ends of the other DFF units I7-I13 except the first bit are respectively connected with the Q opposite ends of the subordinate DFF units I7-I13 and the Q ends of the former DFF units I6-I12, and the output ends are connected with the corresponding data processing units L3-L9.
The invention also includes: and a data calculation unit and an output DFF unit. The data calculation unit is respectively connected with the delay control module L10, the sampling clock CKS and the D ends of the N+M bit data processing units L2-L9.
The output DFF unit is connected to the data computing unit and to the sampling clock CKS via a not gate I5.
The REF circuit comprises: current DAC (Current digital-to-analog converter) and REF buffer (reference voltage drive circuit),
The Current DAC L11 is connected to the delay control module L10, and receives the control signal i_dac_ctl to adjust the bias Current Ibias of the REF buffer L12. REF buffer L12 is connected to the capacitor DAC array, providing VREF+ and VREF-.
As shown in fig. 4, a high-speed SAR ADC flow chart is provided, and the present invention will be described with reference to fig. 1 and 4.
When the circuit is powered up or reset, the delay control module L10 is in a default configuration, leaving DELAY DAC L0 and the Current DAC L11 in a default gear. In this gear, the SAR ADC is just capable of N normal conversions (5 in fig. 1) and M-1 additional conversions (2 in fig. 1) under a typical Corner (PVT is intermediate gear). For a SAR ADC circuit at some unknown Corner, the circuit tries to make 5 normal conversions and 3 additional conversions in this default mode. The process is as follows: after the sampling is finished, the rising edge of cmp_en triggers the comparator Lx to start comparison, and when the comparison is finished, the valid signal (the comparator comparison finishing signal from the output end of the first NAND gate I4) in the K1 module obtains a rising edge and triggers the corresponding DFF (I6-I13) to output Q=1; before q=1, LEN < n > or LREN < m > of the corresponding bit is high, the corresponding logic cell (L2-L9 in the K2 block) is put in an enabled state, the comparison result of the bit is stored, and the corresponding DAC switch is changed. The logic unit comprises 2 latches for latching Q and QB signals, when the EN signal is 1, the 2 latches are respectively connected to Q, QB signals for latching, and the D end is the positive signal output of the corresponding latch of Q; when the EN signal is 0, the latches are disconnected from Q, QB, 2 latches remain in state, and the output D also remains in the original state; the rst signal is a reset signal, and when the rst signal is in a high level, the latch is reset; the L2-L6 also comprises DAC control signals, and DAC control signals DAC_CTL are output through internal logic according to the result of the latch.
After n+m transitions are attempted, on the rising edge of the next CKS, the delay control module L10 of fig. 1 counts the completion status of the additional M transitions, i.e. the delay control module L10 counts whether the Q-terminal outputs of the DFF units I10, I11, I12 are 1. When q=1 of I10, I11 and q=0 of Q12, neither the Current DAC nor the delay DAC is adjusted, and the values are converged to the appropriate values; when q=1 of I10, I11, Q12, indicating that the delay is too small, then the Current of the Current DAC is reduced and the delay DAC delay is increased; when q=0 of I11, indicating that the delay is too large, the Current of the Current DAC is increased and the delay DAC delay is reduced. The Current DAC and the delay DAC can be synchronously adjusted, so that the DAC establishment speed can be adjusted while proper delay is obtained, and the effect of saving the power consumption of the reference level driving circuit is achieved.
After the Current DAC and the delay DAC are adjusted, data output is obtained according to the condition that conversion is completed. The last 1bit (LSB) of the normal transition, DO <0> and RDO <2:0> of FIG. 1, is counted. At the time of the CKS rising edge, L6-L9 outputs DO <0> and RDO <2:0> corresponding to Q=1 of the DFF (I10-I13) are effective values, the number of 1 in the effective values is counted, when the number of 1 occupies the majority of the effective values, DO1<0> =1, otherwise DO1<0> =0. For example, BEN <0> =bren <1> =1, BREN <2> =0, the effective value is 3; when DO <0> =1, RDO <0> =rdo <1> =0, then data 1 is not greater than 3++2=1.5, so DO1<0> =1, DO1<4:1> =do <4:1>. After DO1<4:0> passes through the output DFF unit, the ADC outputs DOUT <4:0>, and the SAR ADC completes the conversion. According to the logic, the last 1bit can be averaged, and the noise performance of the ADC is improved.
In summary, the present invention detects the current state of the SAR ADC by inserting additional conversion bits, and in fig. 1, an additional 3-bit additional conversion bit is inserted as an example, and in fact, the number of conversion bits can be adjusted according to the requirements of the system on the SAR ADC, so as to achieve the purpose of designing the conversion time margin. When the error rate requirement of the system is higher, more than 2 extra conversion bits can be inserted to obtain larger time allowance; the extra conversion bits can be reduced to 2 bits when the system bit error rate requirements are low to achieve higher SAR ADC speeds.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (3)
1. A high-speed SAR ADC circuit, comprising: a capacitor DAC array, a comparator, a REF circuit, a clock logic circuit and a data logic circuit,
The REF circuit is connected with the capacitor DAC array;
the capacitor DAC array is connected with two input ends of the comparator;
The comparator is connected with the clock logic circuit and the data logic circuit;
the clock logic circuit outputs a comparator clock to the comparator;
The data logic circuit outputs DAC control signals to the capacitor DAC array;
the data logic circuit is provided with an additional M-bit DFF unit based on the N-bit DFF unit, and an additional M-bit data processing unit based on the N-bit data processing unit, wherein N, M are positive integers;
each bit of the DFF unit is connected with the corresponding data processing unit;
the data logic circuit comprises a delay control module for receiving a sampling clock CKS;
The M-bit output of the M-bit DFF unit is connected with the input end of the delay control module;
Each bit of the data processing unit is connected with the comparator;
the capacitor DAC control output CTL end of the N-bit data processing unit is connected with the capacitor DAC array;
The delay control module is respectively connected with the REF circuit and the clock logic circuit;
The clock logic circuit comprises an NOT gate, a first NOT gate, a second NOT gate and a delay unit;
The input end of the NOT gate is connected with a sampling clock CKS;
Two input ends of the first NAND gate are connected with the comparator;
The output end of the first NAND gate is connected with an N+M bit DFF unit;
The common connection end of the output end of the NOT gate, the output end of the first NOT gate and the M-bit DFF unit is connected with the three input ends of the second NOT gate;
The output end of the second NAND gate is connected with the input end of the delay unit;
the output end of the delay unit is connected with the comparator;
The delay unit is connected with the delay control module;
The REF circuit comprises: current DAC and REF buffer,
The Current DAC is connected with the delay control module and the REF buffer;
The REF buffer is connected with the capacitor DAC array;
the REF circuit is a reference level driving circuit, the Current DAC is a Current type digital-to-analog converter, and the REF buffer is a reference voltage driving circuit.
2. The high-speed SAR ADC circuit according to claim 1, wherein the sampling clock CKS connects the n+m bit DFF unit via two not gates connected on the one hand, and connects one input terminal of an and gate subordinate to the first bit DFF unit via one not gate, and connects the first bit DFF unit via the other input terminal of the and gate subordinate to the first bit DFF unit; the output end of the AND gate belonging to the first bit DFF unit is connected with a corresponding data processing unit;
the two input ends of the AND gates of the other DFF units except the first bit are respectively connected with the subordinate DFF unit and the former DFF unit, and the output ends are connected with the corresponding data processing units.
3. The high-speed SAR ADC circuit of claim 1, further comprising: a data calculation unit and an output DFF unit;
the data calculation unit is respectively connected with the delay control module, the sampling clock CKS and the N+M bit data processing unit;
The DFF unit is connected to the data computing unit and to the sampling clock CKS through a not gate.
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| TWI847433B (en) * | 2022-12-16 | 2024-07-01 | 瑞昱半導體股份有限公司 | Successive approximation register analog to digital converter and signal conversion method |
| CN117614453B (en) * | 2023-12-06 | 2024-09-03 | 灿芯半导体(上海)股份有限公司 | Logic circuit applied to high-speed SAR ADC |
| CN118646417B (en) * | 2024-08-14 | 2024-10-29 | 成都旋极星源信息技术有限公司 | SAR ADC asynchronous time sequence control logic circuit |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101655521A (en) * | 2008-08-19 | 2010-02-24 | 恩益禧电子股份有限公司 | Pulse phase difference detecting circuit and a/d converter using the same |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN106972859A (en) * | 2017-02-24 | 2017-07-21 | 浙江大学 | A kind of low-power consumption gradual approaching A/D converter |
| CN107947792A (en) * | 2017-12-20 | 2018-04-20 | 中南大学 | A kind of low-power consumption SAR ADC control logic circuits |
| US10044364B1 (en) * | 2017-11-22 | 2018-08-07 | Infinera Corporation | Metastability error correction methods and circuits for asynchronous successive approximation analog to digital converter (SAR ADC) |
| CN109412598A (en) * | 2018-10-29 | 2019-03-01 | 合肥松豪电子科技有限公司 | A kind of successive approximation analog-digital commutator |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
| JP2020036255A (en) * | 2018-08-31 | 2020-03-05 | サンケン電気株式会社 | A/d conversion circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2296280B1 (en) * | 2009-09-10 | 2012-12-19 | Stichting IMEC Nederland | Asynchronous SAR ADC |
| US8754800B2 (en) * | 2012-09-29 | 2014-06-17 | Intel Corporation | Methods and arrangements for high-speed analog-to-digital conversion |
-
2022
- 2022-01-14 CN CN202210044030.7A patent/CN114374391B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101655521A (en) * | 2008-08-19 | 2010-02-24 | 恩益禧电子股份有限公司 | Pulse phase difference detecting circuit and a/d converter using the same |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN106972859A (en) * | 2017-02-24 | 2017-07-21 | 浙江大学 | A kind of low-power consumption gradual approaching A/D converter |
| US10044364B1 (en) * | 2017-11-22 | 2018-08-07 | Infinera Corporation | Metastability error correction methods and circuits for asynchronous successive approximation analog to digital converter (SAR ADC) |
| CN107947792A (en) * | 2017-12-20 | 2018-04-20 | 中南大学 | A kind of low-power consumption SAR ADC control logic circuits |
| JP2020036255A (en) * | 2018-08-31 | 2020-03-05 | サンケン電気株式会社 | A/d conversion circuit |
| CN109412598A (en) * | 2018-10-29 | 2019-03-01 | 合肥松豪电子科技有限公司 | A kind of successive approximation analog-digital commutator |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN110768674A (en) * | 2019-10-29 | 2020-02-07 | 湖南国科微电子股份有限公司 | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method |
Non-Patent Citations (2)
| Title |
|---|
| 12位高精度低功耗SAR ADC设计;李晓兴;《电子世界》;20161231;15-16 * |
| An ultra high-resolution low propagation delay time and low power with 1.25GS/s CMOS dynamic latched comparator for high-speed SAR ADCs in 180nm technology;Sina Mahdavi;《2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI)》;20181231;1-4 * |
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