CN115276656A

CN115276656A - Logic acceleration circuit and logic acceleration method of high-speed capacitive SAR type ADC

Info

Publication number: CN115276656A
Application number: CN202210252801.1A
Authority: CN
Inventors: 韩啸; 韩雁; 程志渊; 谭磊; 陈昌彦
Original assignee: Zhejiang University ZJU; SG Micro Beijing Co Ltd
Current assignee: Zhejiang University ZJU; SG Micro Beijing Co Ltd
Priority date: 2022-03-11
Filing date: 2022-03-15
Publication date: 2022-11-01

Abstract

The invention discloses a logic acceleration circuit and a logic acceleration method of a high-speed capacitive SAR type ADC. The logic acceleration circuit comprises a 2-path selector, a latch, a comparator and an adaptive asynchronous clock generator; a 2-way selector for selecting the output latch result and the comparator result and connecting to a switch controlling the capacitor array analog-to-digital converter CDAC; a latch for latching the comparator result and connected to the 2-way selector; the comparator is used for comparing the output value of the CDAC with a reference voltage V_refAnd outputs the comparison result, the comparison result is output to the 2-way selector, and a comparison finished mark signal is generated after the comparison is finished and is output to the self-adaptive asynchronous clock generator; the self-adaptive asynchronous clock generator comprises a DELAY module DELAY and a plurality of NAND gates and NOT gates, and is used for controlling the successive approximation step. The invention accelerates the logical operation, and each bit operation can be accelerated.

Description

Logic acceleration circuit and logic acceleration method of high-speed capacitive SAR type ADC

Technical Field

The invention relates to a logic acceleration circuit and a logic acceleration method of a high-speed capacitive SAR type ADC (analog-to-digital converter), which are used for improving the conversion speed of the ADC so that the ADC can normally work at a higher sampling rate.

Technical Field

The SAR ADC is widely used for detection of physiological signals, quantization of biological signals, low power consumption wireless communication systems, compensation after error quantization of circuit systems, and the like. For example, when the power management module is applied, if a circuit system needs to output a voltage value with higher precision, the voltage value can be corrected through an ADC, and in general, the circuit system needs more than one ADC because the SAR ADC can realize single-ended, differential, and multi-channel input, so that one high-speed SAR ADC can realize the requirement of the power management on the ADC.

The current resolution of successive approximation analog-to-digital converters is generally below 16 bits, wherein an analog circuit is simple, a large part of circuits are digital circuits, high-performance operational amplifiers are not needed, and the compatibility of the process is good.

Because the integrated circuit has the advantages of strong process compatibility, low power consumption in unit area and the like, for a complex integrated circuit system design, a successive approximation type analog-to-digital converter is usually selected when the performance index is proper. The successive approximation type analog-to-digital converter has close relation between the conversion rate and the process, and under the condition of the same architecture, the more advanced the general process is, the faster the conversion rate is and the lower the power consumption is.

The SAR ADC mainly includes a resistive, capacitive and resistor-capacitor hybrid architecture. The resistor framework can realize higher speed, but the resistor matching performance is inferior to that of the capacitor, the influence of temperature is larger, the precision is lower, and the resistor type has static power consumption and larger power consumption. The capacitor has no static power consumption and good matching performance, and in the SAR ADC with high resolution, the area can be saved by using the bridging capacitor, the total capacitance value is reduced, but the bridging capacitor brings great errors if the bridging capacitor is mismatched.

In a general SAR ADC, the operation time of digital logic includes a waiting comparator comparison time and a latch time, and a logic circuit for controlling the level of a capacitor array is operated according to a comparison result held by a latch. The conventional acceleration method generates an asynchronous clock of logic operation according to the comparison completion signal of the comparator, so that the internal timing sequence is more compact. Digital logic accounts for about 50% of the total conversion time, excluding the time for the digital and analog portions to work together, and a method for further increasing the conversion rate by speeding up the operation time of the digital logic is needed.

Disclosure of Invention

Aiming at the problem that the conversion rate of the SAR type ADC in the prior art is determined by sampling time and conversion time, in order to enable the SAR type ADC to have higher conversion rate, the invention aims to provide a logic acceleration circuit and a logic acceleration method of the high-speed capacitive SAR type ADC.

A logic acceleration circuit of high-speed capacitive SAR type ADC comprises a 2-way selector MUX, a LATCH LATCH, a Comparator, and an adaptive asynchronous clock generator;

a 2-way selector for selecting the output latch result and the comparator result and connecting to a switch for controlling the capacitor array analog-to-digital converter CDAC (Capacitive data to analog converter);

a latch for latching the comparator result and connected to the 2-way selector;

the comparator is used for comparing the output value of the CDAC with a reference voltage V_refAnd outputs the comparison result, the comparison result is output to the 2-way selector, and a comparison finished mark signal is generated after the comparison is finished and is output to the self-adaptive asynchronous clock generator;

the self-adaptive asynchronous clock generator comprises a DELAY module DELAY, a plurality of NAND gates, NOT gates and a buffer for driving the next stage of output, and is used for controlling the successive approximation step.

The 2-way selector comprises two transmission gates.

The latch comprises two transmission gates and two inverters.

The output control of the 2-path selector adopts a 2-path selector control switch, and the 2-path selector control switch is controlled by a state register signal in a logic circuit of a non-accelerating circuit (a state register signal is generated in the logic circuit every asynchronous clock period) matched with a delay module and a NAND gate.

The self-adaptive asynchronous clock generator comprises 4 NAND gates, 1 delay module, 1 inverter and 1 buffer. A method for carrying out logic acceleration by adopting the logic acceleration circuit of the high-speed capacitive SAR type ADC comprises the following steps:

1) After the ADC is controlled by an externally input sampling clock to finish sampling, the comparator starts to work; after the comparator finishes each comparison, the 2-path selector selects the comparison result of the comparator, the latch latches the comparison result, and the latched result is kept until the next quantization;

2) According to the mark signal which is output by the comparator and is compared, the self-adaptive asynchronous clock generator generates an asynchronous clock with a period time long enough for subsequent operation;

3) The 2-way selector outputs the ith bit comparison result output by the comparator firstly, and meanwhile, the latch latches the ith bit comparison result; controlling the switch of the 2-way selector according to the asynchronous clock and the extra delay module, outputting the result converted from the comparison result to the latch result after the latch is latched, and keeping the result until the next quantization;

4) The DATA signal of the ith bit ADC output value is output by a D trigger, and the CDAC is operated according to the output result of the ith bit 2-way selector;

5) After the latch is latched, the latch resets the comparator, and the asynchronous clock controls the comparator to carry out next comparison;

6) And repeating the steps 1) to 5) until the successive approximation finishes quantizing the analog signal.

Step 3), when the asynchronous clock is changed into 1, the ith working state register in the logic circuit of the non-acceleration circuit is changed into 1, at the moment, the 2-way selector selects the comparator result to output, the latch starts to latch the input result continuously, and meanwhile, the comparator also starts to work; the output signal of the ith bit state register passes through a delay module, and after certain delay, the 2-way selector is controlled to select the latch result and enable the latch to keep the latched data; and after the operation is finished, the next step is carried out.

And 5) after the comparator is reset, the CDAC can start comparison only when a stable output is required, when the self-adaptive asynchronous clock generator outputs the ith bit of the state register, the output result of the state register generates a temporary 0 signal through a DELAY module and an NAND gate, and the signal is used as an ACC signal to accelerate the asynchronous clock or a DELAY signal to decelerate the asynchronous clock.

The method controls the self-adaptive asynchronous circuit generator to decelerate the clock by the high-order input signals and accelerate the clock by the low-order input signals.

The invention has the beneficial effects that:

in practical application, in a 0.18um process, each process corner is simulated after layout, and compared with the conventional method which adds the logic accelerating circuit structure provided by the invention, the speed is 100ps to 200ps, and for an ADC with N-bit resolution, the conversion time of 100 × Nps to 200 × Nps can be saved in each sampling quantization period. For a high-speed SAR ADC, the level conversion to the logic control capacitor array can be accelerated by 20-30% compared and completed in asynchronous logic added with an acceleration circuit. In addition, the overall conversion speed can be further improved by about 10% by matching with the self-adaptive asynchronous clock generator.

Drawings

FIG. 1 is a schematic diagram of a logic acceleration circuit of a high-speed capacitive SAR ADC;

in FIG. 1: v_inFor input signal, V_refIs a reference voltage, STEPFor the ADC ith bit work enable signal, COMPARATOR _ DATA is the COMPARATOR result, COMPARATOR _ DONE is the COMPARATOR comparison completion signal, SThe signal selects the input of the ith 2-way selector, LATCH _ DATAThe ith bit comparison result, DATA, latched by the latchAs the result of the ith comparison, ACCFor speeding up the clock cycle of the ith bit, DELAYThe ith bit clock cycle DELAY signal, SAR _ EN is SAR logic clock enable signal, SAR _ CLK is SAR logic clock, MUX is 2-way selector, LATCH is LATCH, comparator is Comparator, and DELAY is DELAY module.

Fig. 2 is a schematic diagram of the acceleration structure of the successive approximation logic circuit in the SAR ADC according to the present invention.

Fig. 3 is a 2-way selector.

In fig. 3, E and E _ I are selection signals of the 2-way selector, D is an input, and Q is an output.

FIG. 4 is a latch structure in a standard logic cell;

e and E _ I in FIG. 4 are the enable signals for the latch, D is the input and Q is the output.

FIG. 5 is a waveform diagram of key signals in a successive approximation logic circuit;

the SWITCH signal in fig. 5 is the ith SWITCH on the capacitor array, and the other signals are the same as in fig. 1.

Fig. 6 is a waveform diagram of a logical operation embodying a SAR-type ADC.

Fig. 7 is a capacitor array switching scheme suitable for high-speed capacitive SAR ADC.

Fig. 8 is a circuit configuration for generating an asynchronous clock in a high-speed SAR-type ADC.

Detailed Description

The invention is illustrated and explained below with reference to the figures and examples, which are not intended to limit the invention.

In the high-speed SAR ADC, under the same Process and the same architecture, the conversion rate is greatly influenced by Process, voltage, and Temperature (PVT). In order to enable the high-speed SAR type ADC to achieve a high conversion rate under the condition that PVT is not ideal, the invention designs a logic acceleration circuit of the high-speed capacitive SAR type ADC.

As shown in FIG. 1, a logic acceleration circuit for a high-speed capacitive SAR type ADC includes a 2-way selector MUX, a LATCH LATCH, a Comparator Comparator, and an adaptive asynchronous clock generator. The connection mode of the acceleration circuit is as shown in fig. 2, the 2-way selector selects the comparator result or the latch result to output, and the result is output before the latch when the comparator result is selected to output, so as to achieve the purpose of acceleration.

The 2-way selector has a structure shown in fig. 3, and is composed of 2 transmitters. The specific structure of the 2-way selector can be selected as shown in fig. 3, and the specific structure includes two transmission gates. The 2-way selector control switch is controlled by a state register signal in a logic circuit of the non-acceleration circuit (a bit of state register signal is generated in the logic circuit every asynchronous clock cycle) in cooperation with a delay module and a NAND gate.

The latch is used for latching the comparator result and is connected to the 2-way selector, and the structure of the latch of the embodiment is shown in FIG. 4 and comprises two transmission gates and two inverters. It can be seen visually from the combination of the timing diagram shown in fig. 5 and the input/output signals in fig. 1 that the output of the 2-way selector is significantly earlier than the latch, and the SWITCH signal is significantly earlier than the signal shown in dashed lines without the speedup circuit.

As can be seen from the waveform diagram in fig. 6, the comparator clock determines the upper sampling rate limit of the ADC during one complete cycle of the ADC operation. The comparator is used for comparing the output value of the CDAC with a reference voltage V_refAnd outputting a comparison result, outputting the comparison result to the 2-path selector, generating a comparison-completed mark signal after the comparison is completed, and outputting the comparison-completed mark signal to the self-adaptive asynchronous clock generator. The CDAC specifically operates by the capacitor array DAC of FIG. 1 obtaining V through the sampling switch_in，V_inComparing with reference voltage to obtain quantized value of the highest bit, and comparing with the reference voltage to obtain quantized value of the capacitor arrayThe switching pattern being as shown in FIG. 7, e.g. the upper panel sampling into the input signal V_inFor quantization without a sign bit, the capacitor is connected to the reference voltage across the lower plate of the column. If the ith comparison result is 1, the ith capacitor upper stage plate is driven by V_refReceiving the GND potential; if the ith bit comparison result is 0, the (i-1) th bit capacitor is connected from GND to V_refPotential, i-th capacitor from V_refTo the GND potential.

The adaptive asynchronous clock generator includes a DELAY module DELAY and several nand gates and not gates for controlling the successive approximation step, and the structure of this embodiment is shown in fig. 8. The structure comprises 4 NAND gates, 1 delay module, 1 NOT gate and 1 buffer. Wherein the two nand gates can speed up and DELAY the clock in coordination with the ACC and DELAY signals, respectively. The status register output results in a temporary 0 signal through a DELAY block and a NAND gate, which serves as the ACC signal to speed up the asynchronous clock or the DELAY signal to slow down the asynchronous clock. The DELAY signal is used for high-order logic operation to ensure that high-order large capacitors can complete level conversion, and the ACC signal is used for low-order operation to reduce the clock period.

The invention accelerates the logic operation of each bit of ADC needing conversion through a plurality of 2-path selectors, so that a clock for performing successive approximation in the high-speed SAR type ADC can work under higher frequency, and the design steps comprise:

1) Determining the capacitance size and the resistance value of a capacitance switch and controlling the level conversion time of a capacitance array according to the precision and the sampling rate of the high-speed SAR type ADC to be designed so as to meet the requirements of the precision and the conversion rate of the ADC;

2) The added logic is designed. A logic accelerating circuit for controlling the level conversion of the capacitor array is added in the logic circuit;

3) And designing a successive approximation clock inside the ADC to ensure that the conversion of the ADC can be completed in each period.

The specific operation of the step 2) is as follows:

first, the ith bit flip-flop switches, and the ADC enters the logic operation of the ith bit.

The comparator outputs a flag signal indicating that the comparison is completed after the ith comparison is completed.

After the ith bit comparison is completed, the ith bit 2-way selector selects the output result of the comparator, and meanwhile, the latch stores the ith bit comparison result.

The output result of the 2-way selector enables the level of the whole capacitor column to start to switch after a series of logic operations according to the switching mode of the capacitor array.

After the latch stores the comparison result, the 2-way selector selects to output the latch result, and the latch stops working. And after the latch stops latching, the comparator starts to reset, and after the reset is completed and the level conversion of the capacitor array is completed, the next comparison is carried out. Since the capacitor array is operated earlier by the speedup circuit, the level transition will complete the transition earlier, and step 1) can determine that the time of the level transition is less than the cycle size of the asynchronous clock.

A method for carrying out logic acceleration by adopting the logic acceleration circuit of the high-speed capacitive SAR type ADC comprises the following steps:

1) After the ADC is controlled by an externally input sampling clock to finish sampling, the comparator starts to work; after the comparator finishes each comparison, the 2-way selector selects the comparison result of the comparator, the latch latches the comparison result, the latched result is kept until the next quantization, the signal for controlling the CDAC can be changed when the state register is started, the signal of the state register is reset after each conversion is finished, the latch does not need to be reset, and the advantage of doing so is that the dynamic power consumption caused by the reset of the latch can be reduced.

2) According to the mark signal which is output by the comparator and is compared, the self-adaptive asynchronous clock generator generates an asynchronous clock with a period time long enough for subsequent operation; the asynchronous clock is generated by the circuit structure shown in fig. 8, the comparator generates a high level 1 after comparison is completed, the signal does not pass through any delay module, the asynchronous clock is changed into 0 only through 6-stage logic operation, and the comparator is reset by the 0 type. The comparator outputs the comparison completion flag signal to 0 after the completion of the reset. The 0 signal is affected by a delay blockEnsure that the output of CDAC is stable result and is compared with V next time by the comparator_refA comparison is made. ACC (adaptive cruise control)And DELAYThe signal accelerates or delays the time when the model of SAR _ CLK becomes 1 according to the different stable time of the CDAC output signal when the high bit and the low bit are converted.

3) The 2-way selector outputs the ith bit comparison result output by the comparator firstly, and meanwhile, the latch latches the ith bit comparison result; the switch of the 2-way selector is controlled according to the asynchronous clock and the extra delay module, after the latch is latched, the output is converted from the comparison result to the latch result and is kept until the next quantization, and the 2-way selector selects the structure shown in the figure 3. The latch employs the structure shown in fig. 4, which is also a fast structure. In practice, the structure of fig. 4 is also slow and can be accelerated by the 2-way selector shown in fig. 3, so that the output of the CDAC can be changed more quickly and its settling time can be made earlier. The comparator is a dynamic comparator, wherein a preamplifier is used for amplifying signals and isolating kickback noise, and the comparator has bandwidth with the amplifier, namely, a certain time is needed from the time when the CDAC output is stable to the time when the CDAC output is compared, so that the CDAC output signals are stabilized in advance, the preamplifier has not so much bandwidth pressure, and the clock speed is increased under the condition that the bandwidth allows, so that the conversion rate of the ADC can be improved.

4) The ith bit ADC outputs a DATA value signal which is output by a D trigger, and the CDAC is operated according to the output result of the ith bit 2-way selector; and D flip-flops for outputting results output quantized data latched by the latches in the FIG. 1 after conversion is completed. The output signal of the 2-way selector can control the CDAC to change the output voltage when the output of the bit status register is 1.

5) After the latch is latched, the latch resets the comparator, and the asynchronous clock controls the comparator to carry out next comparison; resetting of the comparator note that it takes a slower time than the 2-way selector selection latch output, which is done to prevent the 2-way selector output from resetting the comparator output. And also slower than the time the latch enters the hold phase, in order to prevent latching to the reset comparator output.

6) And repeating the steps 1) to 5) until the successive approximation finishes the quantization of the analog signal. An N-bit ADC requires repeating the above operation N times. That is, the speed-up circuit can function N times.

Step 3), when the asynchronous clock is changed into 1, the ith working state register in the logic circuit of the non-acceleration circuit is changed into 1, at the moment, the 2-way selector selects the comparator result to output, the latch starts to latch the input result continuously, and meanwhile, the comparator also starts to work; the output signal of the ith bit state register passes through a delay module, and after certain delay, the 2-way selector is controlled to select the latch to latch the result, and the latch is enabled to keep the latched data. And after the operation is finished, the next step is carried out.

And 5), after the comparator is reset, the CDAC needs to have a stable output to start comparison, when the self-adaptive asynchronous clock generator outputs the ith bit of the status register, the output result of the status register generates a temporary 0 signal through a DELAY module and a NAND gate, and the temporary 0 signal is used as an ACC signal to accelerate the asynchronous clock or a DELAY signal to decelerate the asynchronous clock. The method adopts a few high-order input signals to decelerate the clock and adopts a few low-order input signals to accelerate the clock. Without the adaptive asynchronous clock generation architecture, it is necessary to obey the time required for the CDAC output voltage to stabilize at the time of the most significant bit change. However, when the low bit changes, because the CDAC output voltage is stable and fast due to the low bit changes, and the difference between the two voltage values compared when the low bit changes is small, the bandwidth pressure of the preamplifier is also small, which results in that the low bit has much time to be left.

The logic operation circuit for controlling the capacitor array switch must have a register or latch to hold the comparison result of the comparator. Fig. 4 is a latch structure, fig. 3 is a 2-way selector structure, and the 2-way selector is significantly faster than the latch in terms of the number of logical operation stages and structure.

Determining the conversion time and the reset time of the comparator, and ensuring that the clock of the step 5) can enable the comparator to complete the comparison of the level and complete the reset. After the comparator is reset, the CDAC needs to have a stable output to start comparison, and since the output of the CDAC has a longer stable time in the high-order operation and a shorter stable time in the low-order operation, it is necessary to adjust the DELAY module in fig. 8 to control the internal logic operation clock period and to assist with ACC and DELAY signals. The status register output results in a temporary 0 signal through a DELAY block and a NAND gate, which serves as the ACC signal to speed up the asynchronous clock or the DELAY signal to slow down the asynchronous clock. The DELAY signal is used for high-order logic operation to ensure that high-order large capacitors can complete level conversion, and the ACC signal is used for low-order operation to reduce the clock period. As can be seen from the waveform diagram in fig. 6, the comparator clock determines the upper sampling rate limit of the ADC during one complete cycle of the ADC operation.

The successive approximation logic operation needs a plurality of registers to record working states, the latch records the comparison result of each bit, and the capacitor array is operated according to the comparison result of each bit. The ADC internally generates a comparator clock asynchronous to the sampling clock (which is also the clock generated by the adaptive asynchronous logic clock generator to control the operation of the internal logic) and this clock is used to control the operation of the internal successive approximation logic and the operation state of the comparator. After sampling is finished, the register is influenced by the comparator clock, STEP <0> enters a working state and is set to be 1, logic operation is started, after the comparator result is output, the comparator result is latched, the latched comparator clock enters a reset state, meanwhile, the logic circuit controls level conversion of the capacitor array, and after the conversion is finished, the next comparator cycle is started. And (4) successively comparing and approaching, and finally outputting the result latched each time, wherein the result is the quantized value of the ADC. The quantized values of the ADC are output from a dedicated register.

After the logic operation circuit is added, the capacitor array can enter level conversion operation more quickly after comparison is finished, and logic acceleration is realized.

The principle of logic acceleration in the step 3) is that the 2-way selector is far faster than the latch conversion output, and the 2-way selector outputs the comparison result of the comparator first and is matched with the self-adaptive asynchronous clock to accelerate. The 2-path selector outputs the comparator result and latches the comparison result of the comparator at the same time, the output result of the 2-path selector is faster than that of the latch, and the output result of the 2-path selector controls the capacitor array to carry out level conversion so as to enable the capacitor array to complete level conversion in advance, and thus, the clock period of each comparator can be reduced after operation. The comparator cannot directly compare after level conversion is completed, and if the bandwidth of the preamplifier of the comparator is not enough, the comparison error can be caused, and the accelerating structure reduces the pressure on the bandwidth of the amplifier. The acceleration structure has obvious improvement on the conversion rate of the high-speed SAR type ADC when the acceleration structure works at the SS process corner and high temperature. The performance of the SAR type ADC is not affected because the operation is performed aiming at the logic operation.

In the 0.18um process, the simulation after each process corner layout in practical application shows that the structure of fig. 4 is only slower by 100ps to 200ps than the structure of fig. 2 accelerated by a latch and a 2-way selector, and for an ADC with N-bit resolution, the conversion time of 100 × nps to 200 × nps can be saved in each sampling quantization period. The level conversion to the logic control capacitor array can be accelerated by 20-30% by comparison in the asynchronous logic added with the acceleration circuit. The overall conversion speed can be further improved by about 10% by matching the self-adaptive asynchronous clock generator.

The embodiments in the above description can be further combined or replaced, and the embodiments are only described as preferred examples of the present invention, and do not limit the concept and scope of the present invention, and various changes and modifications made to the technical solution of the present invention by those skilled in the art without departing from the design concept of the present invention belong to the protection scope of the present invention. The scope of the invention is given by the appended claims and any equivalents thereof.

Claims

1. A logic acceleration circuit of high-speed capacitive SAR ADC is characterized in that the logic acceleration circuit comprises a 2-way selector MUX, a LATCH LATCH, a Comparator multiplexer and an adaptive asynchronous clock generator;

a 2-way selector for selecting the output latch result and the comparator result and connecting to a switch controlling the capacitor array analog-to-digital converter CDAC (Capacitive data to analog converter);

a latch for latching the comparator result and connected to the 2-way selector;

the self-adaptive asynchronous clock generator comprises a DELAY module DELAY and a plurality of NAND gates and NOT gates, and is used for controlling the successive approximation step.

2. The logic acceleration circuit of a high-speed capacitive SAR-type ADC according to claim 1, wherein said 2-way selector comprises two transmission gates.

3. The logic acceleration circuit of a high-speed capacitive SAR-type ADC according to claim 1, wherein said latch comprises two transmission gates and two inverters.

4. The logic accelerating circuit of a high-speed capacitive SAR ADC according to claim 1, wherein said 2-way selector control switch is adapted to output control of said 2-way selector, and said 2-way selector control switch is controlled by a state register signal (one bit of state register signal is generated in said logic circuit every asynchronous clock cycle) in said logic circuit of said non-accelerating circuit in cooperation with a delay module and said nand gate.

5. The logic accelerator circuit of a high-speed capacitive SAR ADC according to claim 1, wherein said adaptive asynchronous clock generator comprises 4 nand gates, 1 delay block, 1 inverter, and 1 buffer.

6. A method for performing logic acceleration using the logic acceleration circuit of a high-speed capacitive SAR-type ADC according to claim 1, characterized by the steps of:

1) After the ADC is controlled by an externally input sampling clock to finish sampling, the comparator starts to work; after the comparator finishes each comparison, the 2-path selector selects the comparison result of the comparator, the latch latches the comparison result, and the latched result is kept until next quantization;

3) The 2-path selector outputs the ith bit comparison result output by the comparator firstly, and meanwhile, the latch latches the ith bit comparison result; controlling the switch of the 2-way selector according to the asynchronous clock and the extra delay module, outputting the result converted from the comparison result to the latch result after the latch is latched, and keeping the result until the next quantization;

4) The ith bit ADC outputs a DATA value signal which is output by a D trigger, and the CDAC is operated according to the output result of the ith bit 2-way selector;

7. The method according to claim 6, wherein in step 3), when the asynchronous clock becomes 1, the i-th bit operation status register in the logic circuit of the non-acceleration circuit becomes 1, and at this time, the 2-way selector selects the output of the comparator result, the latch starts to latch the input result continuously, and at the same time, the comparator also starts to operate; the output signal of the ith bit state register passes through a delay module, and after certain delay, the 2-way selector is controlled to select the latch result and enable the latch to keep the latched data; and after the operation is finished, the next step is carried out.

8. The method of claim 6, wherein in step 5), after the comparator is reset, the CDAC is required to have a stable output to start comparison, and when the adaptive asynchronous clock generator outputs the i-th bit of the status register, the output result of the status register generates a temporary 0 signal through a DELAY module and a nand gate, and the temporary 0 signal is used as the ACC signal to speed up the asynchronous clock or the DELAY signal to slow down the asynchronous clock.

9. The method of claim 8, wherein the clock is slowed down using the high order input signal and the clock is speeded up using the low order input signal.