KR101725833B1 - Ten bit successive approximation register analog to digital converter - Google Patents

Abstract

The present invention proposes a 10-bit sequence comparison type analog-to-digital converter.
A 10-bit sequential comparison type analog-to-digital converter according to the present invention includes an input unit for receiving an analog signal and generating a reset signal in a POR circuit; And
And an output unit including a capacitor digital-to-analog converter in which the most significant bit stage is divided into four, and receiving the reset signal and outputting the digital signal as a digital signal.
Thus, by using four times as many switches as the uppermost capacitor stage to which the analog input signal is charged, it is possible to obtain a value almost equal to the analog input signal applied for the first time.
It also makes it easier to restore the desired signal and has the effect of increasing the resolution.

Description

[0001] DESCRIPTION [0002] TEN BIT SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER [

More particularly, the present invention relates to a digital converter which divides the capacitor bit of the most significant bit into quadrants to improve the linearity of the analog input and increase the resolution.

The analog-to-digital converters have been proposed and practically applied to various types of technologies in accordance with various standards of various application fields. Particularly, the analog-to-digital converters used in wireless communication devices have problems such as low power consumption .

Also, as interest in broadband communication increases, there is a demand for an analog-to-digital converter that operates at a higher speed in addition to lower power consumption.

Among various analog-to-digital converters, the Successive Approximation Analog / Digital Converter is a circuit for converting an analog signal to a digital signal by using a high-speed dynamic latch comparator to charge the charge of the capacitor digital-analog converter, The structure of the circuit is simple and low-power design is possible as compared with analog / digital converters of other structures.

 Member.

1A is an example of a C-DAC (Capacitor-Digital to Analog Converter) of a conventional 4-bit SAR ADC (SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER), and FIG. 1B is an example of DAC output of a conventional single- .

신호가 샘플링된다. (이때

값은

와 같은 값을 갖는다.) First, when the reset signal and the first clock signal come in simultaneously, the C-DAC array

The signal is sampled. (At this time

The value is

And has the same value.)

값이 입력되고, C-DAC Array에

값이 저장된다. Then, before the second clock signal is input,

Value is entered, and the C-DAC

The value is stored.

When the second clock is activated, the comparison and conversion starts from this point.

값이

값보다 작은 값을 갖기 때문에 비교기 출력이 ‘1’을 갖는다.1A and 1B,

The value is

Value, the comparator output has a value of " 1 ".

값만큼 저장하게 되고, 다시 비교를 진행하게 된다. 역시

값이

값보다 작기 때문에 비교기 출력에 ‘1’을 갖게 된다. In a C-DAC array

Value, and the comparison is resumed. Also

The value is

Value, it will have a '1' in the comparator output.

값을 저장하게 된다. 세 번째 클럭 신호가 동작하게 되면

값과

을 비교하게 되는데, 이 값은

보다 큰 값을 가지므로

값을 갖게 된다. Therefore, the C-DAC array

Value. When the third clock signal is activated

Value and

The value of which is

Since it has a larger value

Value.

값과

값을 비교하고 역시 더 큰 값을 가지므로 ‘0’의 출력을 갖고

값을 취한다. When the fourth clock signal is operating

Value and

Compares values and also has a larger value, so it has an output of '0'

Value.

값과

값과 비교를 하게 되고, ‘1’값을 갖게 되어 최종 디지털 출력이 다음의 ‘11001’값을 나타내게 된다. When the fifth clock signal is operating,

Value and

Value, and has a value of '1', so that the final digital output shows the next value '11001'.

값에 단위 커패시턴스

값을 곱한 값이 된다. Finally, the final output voltage value

Unit capacitance to value

Multiplied by the value.

In this case, the linearity of the capacitor digital-to-analog converter plays an important role in increasing the resolution.

However, the analog-to-digital converter of the time-series comparator may suffer from a lower resolution when the clock speed is faster than 10 MHz.

In this case, if the conversion is performed before the analog input signal is sufficiently charged in the first sampling interval, the desired signal can not be restored.

Korean Patent Publication No. 10-2011-0048231

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a technique of securing linearity by dividing the most significant bit of a capacitor digital converter into four parts in order to secure linearity of an analog input signal to be charged in a capacitor digital- .

A 10-bit sequence comparison type analog-to-digital converter according to the present invention comprises:

An input unit for receiving an analog signal and generating a reset signal; And

And an output unit for receiving the reset signal and outputting the digital signal as a digital signal.

Preferably, the input unit may include a POR module that implements the analog signal as a Reset signal using a D-flip-flop structure.

Advantageously, the output may include a DAC module with a capacitor digital-to-analog converter using a split capacitor that divides the capacitor stage into two parts: an MSB array and an LSB array.

Advantageously, the output may further comprise a comparison module with an S-R dynamic latch comparator.

Advantageously, the S-R dynamic latch comparator may be a NAND gate structure.

Advantageously, the output unit further comprises a SAR module having an SAR logic circuit for performing a feedback process for storing the output value of the S-R dynamic latch comparator and for passing the output value to the capacitor digital-to-analog converter.

The output unit may further include an output register module having a D-flip-flop structure, receiving an output signal of the SAR module as a clock, storing a value, and outputting a digital output signal.

According to the present invention, it is possible to obtain a value almost equal to the analog input signal applied for the first time by dividing the uppermost capacitor stage charged with the analog input signal by four and using four times as many switches.

It also makes it easier to restore the desired signal and has the effect of increasing the resolution.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate preferred embodiments of the invention and, together with the description of the invention given below, serve to further understand the technical idea of the invention. And should not be construed as limiting.
1A is an example of a C-DAC of a conventional 4-bit SAR ADC.
Figure 1B shows the DAC output of a conventional single input SAR ADC.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a 10-
3 is a block diagram of a POR module in accordance with one embodiment of the present invention.
4 is a block diagram of a digital buffer circuit according to one embodiment of the present invention. 5A is a block diagram of a general C-DAC array;
5B is a block diagram of a C-DAC array using split capacitors according to an embodiment of the present invention.
6A is a block diagram of a dynamic latch comparator in accordance with one embodiment of the present invention.
6B is a block diagram of an SR latch using a NAND gate structure in accordance with an embodiment of the present invention.
7A is a block diagram of a 10 bit SAR logic circuit in accordance with an embodiment of the invention.

7B is an example of a 10 bit SAR logical algorithm according to an embodiment of the present invention.
8 is a block diagram of an output register according to an embodiment of the present invention;
9 is an example of a C-DAC control logic circuit algorithm according to an embodiment of the present invention.
10A is a C-DAC control logic circuit according to an embodiment of the present invention.
10B is a C-DAC control logic circuit switch in accordance with an embodiment of the present invention.
11 is a circuit diagram of a 10-bit sequential comparison type analog-to-digital converter according to an embodiment of the present invention.
12A is a block diagram of a conventional capacitor digital-to-analog converter.
12B is a block diagram of a capacitor digital-to-analog converter in accordance with an embodiment of the present invention.
13 is a signal timing diagram of a 10-bit sequential comparison type analog-to-digital converter according to an embodiment of the present invention.
14 is a flowchart illustrating an operation of a 10-bit sequence comparison type analog-to-digital converter according to an embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

The specific structure or functional description presented in the embodiment of the present invention is merely illustrative for the purpose of illustrating an embodiment according to the concept of the present invention, and embodiments according to the concept of the present invention can be implemented in various forms.

And should not be construed as limited to the embodiments set forth herein, but should be understood to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

의 같은 크기를 갖는

와

값만큼 샘플링이 된다. The SAR ADC of the differential mode used in the circuit proposed by the 10-bit sequential comparison type analog-to-digital converter 100 according to the embodiment of the present invention is also used in a C-DAC array

Of the same size

Wow

Sampling is performed.

에서 n의 수를 늘려가면서 전압 값을 더하거나 빼주게 되는데 각각 (+)단자와 ()단자의 값을 비교하여 마찬가지로 변환을 해나가게 된다. Like each single mode

The voltage value is added or subtracted while increasing the number of n, and the values of the (+) terminal and the () terminal are compared with each other.

Using differential mode rather than single mode has the advantage of reducing the noise that can occur in the C-DAC array, which can further improve the resolution.

2 is a configuration diagram of a 10-bit sequence comparison type analog-to-digital converter 100 according to an embodiment of the present invention.

The 10-bit sequence comparison type analog-to-digital converter 100 according to the present invention includes an input unit 10 and an output unit 20.

The input unit 10 may include a power on reset (POR) module 11.

The POR module 11 can generate a reset signal using an analog signal (a clock signal, a VDD signal, and the like).

This reset signal is generated for every 13 clock signals, and every time this signal is generated, the 10-bit SAR ADC completes all the conversion.

That is, it is an important signal that not only becomes a reference for conversion but also enables the operation of all circuits.

3 is a block diagram of a POR module according to an embodiment of the present invention.

As shown in FIG. 3, a reset signal can be generated by dividing a clock signal using a D-flip-flop structure.

The clock signal (CLK) and the reset signal (Reset) at the input of the SAR ADC are the signals used in several detail blocks.

Therefore, it may take a lot of load or affect the clock and reset signal due to noise.

4 is a block diagram of a digital buffer circuit according to an embodiment of the present invention.

A buffer circuit may be constructed as shown in FIG. 4 and provided behind a clock and a reset signal to reduce the above-described points.

In addition, this buffer circuit can be added to the digital output part to reduce the noise that may be generated by the parasitic elements inside the chip and the PCB later.

At this time, considering the size of the load, the size of the buffer may be increased by 3 times to increase the size of the final stage by 81 times.

The output unit 20 may include a digital to analog converter (DAC) module 21, a comparison module 22, an SAR module 23, and an output register module 24.

The DAC module 21 may include a capacitor digital-to-analog converter (C-DAC).

In a SAR-ADC (SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER), a C-DAC array has a large effect on power and area, and also a large part in resolution.

5A is a diagram illustrating a general C-DAC array block diagram,

5B is a block diagram of a C-DAC array using split capacitors according to an embodiment of the present invention.

As can be seen from FIG. 5A, the arrangement of the C-DAC increases by an exponent of 2 as the number of bits of resolution increases.

If the resolution is increased by 8 bits or more, the size of the capacitors of the MSB may increase exponentially to increase the total area of the circuit, thereby increasing the power consumption.

)를 사용하여 C-DAC Array의 크기를 줄일 수가 있다. Therefore, as shown in FIG. 5B, a split capacitor (capacitor)

) Can be used to reduce the size of the C-DAC array.

5A and 5B show a 10-bit C-DAC array. However, the split capacitor is divided into two parts, an MSB array and an LSB array, and is represented by two 5-bit C-DAC arrays.

Split capacitors are connected in series with the LSB array and calculated using the following equation.

Since the combination of the LSB array and the split capacitor must be equal to the LSB of the MSB array, the following expression can be shown.

의 단위 커패시터(

)의 개수가 필요하지만, 이 회로를 사용하면

개의 단위 커패시터와 Split 커패시터만을 사용해서 동일한 성능의 DAC를 만들어 낼 수 있다. In the case of the above-mentioned C-DAC,

Unit capacitor (

), But if you use this circuit

It is possible to create a DAC having the same performance by using only the unit capacitors and the split capacitors.

In the proposed circuit according to the present invention, not only the unit capacitors are arranged around the entire capacitor array in consideration of the matching characteristics, but also the dummy capacitors having the same size as the split capacitors are used at the connection portion between the MSB array and the LSB array.

This layout allows us to see DAC behaviors similar to Schematic.

) 값이 샘플링되고, 근사화가 진행되는 경우가 있다. In case of general SAR ADC, when '1' is input to the reset signal,

) Values are sampled and the approximation may proceed.

를 샘플링하고 다음 CLK 신호가 인가되기 전에

값을 샘플링하게 된다. The other is that when '1' is applied to the reset signal as in the operation principle used in the circuit proposed according to the present invention

And before the next CLK signal is applied

Values are sampled.

값은 MSB 단에만 입력되어 샘플링되기 때문에 MSB 단의 정확도가 해상도에 큰 영향을 끼치게 된다. At this time

Since the value is sampled only at the MSB stage, the accuracy of the MSB stage greatly affects the resolution.

If the initial data is not accurate, it is hard to get accurate data.

The technique used to improve this accuracy is to divide the MSB stage into four equal-sized capacitors.

The comparison module 22 may comprise an S-R dynamic latch comparator.

6A is a block diagram of a dynamic latch comparator comparator.

In particular, the dynamic latched comparator used in the circuit proposed by the 10-bit sequential comparison type analog-to-digital converter according to the embodiment of the present invention does not use a preamplifier, thereby maximizing the power efficiency.

Dynamic latch comparator The comparator can be composed of two regenerative latches and a differential input stage.

If the clock is '0', all output terminals are reset to '0'. If the clock signal is given '1', it operates in regeneration mode to compare the difference between two input terminals and output '0' or '1' Digital output value can be displayed.

An S-R latch may be connected to the output of the comparator to remove unwanted portions from the output of the previous comparator as well as to reduce undesirable transient noise.

In this case, the structure of the S-R latch can be a NOR gate structure and a NAND gate structure.

DAC_P and DAC_N are differential input terminals, and OutP and OutN are connected to the input terminal of the S-R latch.

6B is an S-R latch structure using a NAND gate structure.

The SAR module 23 may comprise a 10-bit SAR Logic (SAR logic circuit).

The OutputRegister module 24 outputs the final digital output signal.

FIG. 7A is a block diagram of a 10-bit SAR logic circuit according to an embodiment of the present invention, and FIG. 7B is an example of a 10-bit SAR logic algorithm according to an embodiment of the present invention.

The SAR logic circuit can be configured based on a D-flip-flop, as can be seen in FIG. 7A.

The SAR logic circuit stores the output value of the comparator, passes it to the C-DAC, and performs a logic process to allow the approximation process to proceed through the feedback process.

The D-flip-flop can be composed of a shift register and an output stage as a basic block.

The shift register literally stores the output value and transfers the stored output value to the next block whenever the clock signal is applied.

When '1' is applied to Reset, '1' can be stored in Q of the first D flip-flop.

Similarly, when the next clock is applied, '1' is stored in the Q of the next block, and the value of Qb can operate the D-flip flop of the output stage and derive the data from the comparator as an output value.

The Q value of the second D flip-flop in the output stage is applied to the clock of the first D flip-flop to determine the final Q value, which can be the MSB value of the digital output.

That is, the Q value of the first stage shift register becomes '10000 00000' at the first clock and '1000 00000' at the second clock.

This value allows the output stage to operate, and the output stage data can receive the output data from the comparator and store the value.

If this process is repeated, the final digital output can be determined from MSB to LSB after 12 clocks.

Additionally, the output from the last block of the shift register can store the SAR_EOC signal '1' value.

This value can be applied to an output register to store the final digital output and to output the output.

This value can be stored in the c output register while the next conversion process takes place, and the SAR_EOC signal can be received to store the new output value again.

The SAR logic algorithm is shown in Figure 7b.

In this case, the output register is composed of a D-flip-flop, and the SAR_EOC signal can be clocked to store the value and output the output data.

A block diagram of the output register is shown in Fig.

It can receive data from SAR Logic and export it to the final digital output.

This value can be passed through the digital buffer described in the previous section, resulting in a final result.

In order to store the charge quantity in the C-DAC Array and to input the voltage value to the comparator, it may be necessary to control it.

신호에 의해서 C-DAC Array 회로를 동작시킬 수 있다.A reset signal which is an output value generated by the POR module 11 and an output value produced by the SAR logic circuit

The C-DAC array circuit can be operated by a signal.

It can be operated according to the timing of the clock signal, the reset signal, and the comparator output.

가 저장되고, Bottom Plate에는

신호가 인가될 수 있다.If '1' is input to Reset,

And the bottom plate

A signal can be applied.

)단자에는

신호가 인가된다.) 다음 클럭이 동작하기 전인 Reset 신호와

신호가 모두 ‘0’일 때, 아날로그 신호인

(

)이 Bottom Plate에 인가될 수 있다.(In differential)

) Terminal

Signal is applied.) Before the next clock operation, the reset signal

When the signals are all '0', the analog signal

(

) Can be applied to the bottom plate.

의 동작여부에 따라서 컨트롤 회로가 동작할 수 있다.The reset signal is fixed to '0' until the end of the conversion cycle from the second clock signal to the output of the SAR logic circuit

The control circuit can operate according to whether or not the control circuit is operated.

이 ‘1’이면 High, ‘0’이면 Low 값을 갖고, 동작할 수 있다.When the reset signal is fixed at '0'

Is '1', and has a Low value if it is '0', and can operate.

FIG. 9 shows an example of a C-DAC control logic circuit algorithm according to an embodiment of the present invention, and FIG. 9 shows such an operation algorithm.

10A is a diagram illustrating a C-DAC control logic circuit according to an embodiment of the present invention, and FIG. 10B is a diagram illustrating a C-DAC control logic circuit switch according to an embodiment of the present invention.

In Fig. 10A, a circuit for operating with such an algorithm is configured.

The last two stages improved the driving ability by using a size three times the size of the basic inverter to operate the switch.

The logic circuit shown in Fig. 10A can be used to operate the switch of Fig. 10B to drive the C-DAC array circuit.

크기의 더미 스위치를 배치하여 Charge Injection과 Clock Feedthrough 현상을 최소화할 수 있다.At this time, the switch width can be set to four times the minimum size,

Sized dummy switches can be placed to minimize charge injection and clock feedthrough.

11 is a block diagram showing the overall configuration of a sequential comparison type analog-to-digital converter (ADC) 100 (an analog to digital converter (ADC)) designed by dividing the most significant bit end of a capacitor digital- Block diagram.

The overall procedure of the digital-to-analog converter 100 proposed by the present invention is such that a reset signal is generated by a power on reset (POR) module 11 to initialize the conversion, and a capacitor digital-to- The amount of charge stored in the DAC module 21 is changed, and the final output signal is outputted through the OutputRegister module 24_, and a SAR_EOC (End of Conversion) signal is generated, thereby completing the conversion process.

12A is a block diagram of a conventional capacitor digital-to-analog converter, and FIG. 12B is a block diagram of a capacitor digital-to-analog converter proposed in the present invention.

배 만큼 곱한 값이 사용되었는데, 도 12b에 나타난 본 발명에 따른 커패시터 디지털 아날로그 변환기는 이 값을 4분할하여 단위 커패시턴스를 4배한 값을 최상위 비트 단으로 사용할 수 있다.As shown in Fig. 12A, the configuration of the most significant bit of the existing circuit is the same as that of the unit capacitance value

The capacitor digital-to-analog converter according to the present invention shown in FIG. 12B can use a value obtained by dividing the value by four and multiplying the unit capacitance by four as the most significant bit.

13 is a diagram illustrating signal timing diagrams of a 10-bit sequential comparison type analog-to-digital converter according to an embodiment of the present invention.

As shown in FIG. 13, the analog input signal is applied before the reset signal is input and the next clock signal is applied, where the stage where the analog input signal is charged is the most significant bit stage.

Therefore, if the analog value is not properly input at this time, it becomes difficult to restore a proper value.

FIG. 14 is an operational flowchart of a 10-bit sequence comparison type analog-to-digital converter according to an embodiment of the present invention.

(Analog input signal) according to the above-mentioned description, and receives the clock signal (analog input signal) through the POR module 11 through the input unit 10 at step s10 and the capacitor digital-analog conversion at the output unit 20 through the DAC module 21 After the operation (s20), a digital signal is output via the SR dynamic latch comparator (s30) through the comparison module 22, finally through the SAR logic circuit of the SAR module (s40), and finally through the OutputRegister (s40) (s50),

According to the present invention, the most significant bit stage of the present invention can be configured by using three more switches of the same size used in the most significant bit stage of the present invention.

By using three more switches, it is possible to reduce the error of the analog input signal which occurs when the clock speed is faster than a certain speed by speeding up the charging at the most significant bits.

If only one switch is used, the speed of receiving analog input is slower than that of 4, so it goes to the next clock before getting the desired value, and the desired value is not obtained.

The value indicated by the solid line is more similar to the analog input value which is actually received at the beginning than the portion indicated by the dotted line, so that the error can be reduced and the effect of increasing the number of effective bits of the entire converter can be obtained.

12A is a diagram of a general C-DAC array circuit not applying the idea, and FIG. 12B is a block diagram of a C-DAC array to which the MSB stage proposed according to the present invention is applied.

의 커패시터 양을 갖는 MSB단을

의 같은 크기로 나누어 스위치를 4배 더 증가시켰다. Through simulation

RTI ID = 0.0 > MSB < / RTI >

And the switch was increased four times.

의 값이 charging 되는 속도보다

의 크기로 동시에 4개의 노드에서 한번에 charging 되기 때문에 변환 속도에 비교적 영향을 덜 받는 결과를 얻어낼 수가 있다.

The value of

Of the total number of nodes simultaneously charged at four nodes, so that the conversion rate is relatively less influenced.

의 아날로그 정현파를 입력주파수,

의 샘플링 주파수에서

은

의 모의 실험 결과를 나타내었고, 일반적인 SAR ADC는

의 결과를 보여서 효과적인 결과를 얻어내는 것을 확인할 수 있었다.In fact, in the simulation of the SAR ADC using the present invention

The analog sinusoidal wave of the input frequency,

At the sampling frequency of

silver

, And a typical SAR ADC is shown in Fig.

The results are shown in Fig.

This process can be repeated to restore the analog signal to a digital signal.

In this case, the most significant bit of the capacitor digital-to-analog converter can be modified into quadrants to shorten the time for storing the analog input, thereby securing the linearity.

This makes it easier to restore the desired signal and increase the resolution.

The present invention has been described in detail with reference to preferred embodiments. It will be apparent to those skilled in the art that the present invention is not limited to the embodiments described above and that various modifications and changes may be made by one of ordinary skill in the art without departing from the scope of the present invention, It is to be understood that the technical idea of the present invention extends to the extent possible.

Claims (7)

An input unit for receiving an analog signal and generating a reset signal; And
And an output unit for receiving the reset signal and outputting the digital signal as a digital signal, wherein the 10-bit sequence comparison type analog-to-digital converter includes a capacitor digital-to-analog converter in which a most significant bit is divided into four parts.
The method according to claim 1,
Wherein the input unit includes a POR module for implementing the analog signal as a Reset signal using a D-flip-flop structure.
The method according to claim 1 or 2,
Wherein the output section includes a DAC module having a capacitor digital-to-analog converter using a split capacitor dividing the capacitor stage into two parts, an MSB array and an LSB array.
The method of claim 3,
Wherein the output further comprises a comparison module having an SR dynamic latch comparator.
5. The method of claim 4,
Wherein the SR dynamic latch comparator is a NAND gate structure.
5. The method of claim 4,
Wherein the output unit further comprises a SAR module having an SAR logic circuit for performing a feedback process for storing an output value of the SR dynamic latch comparator and for passing the output value to the capacitor digital- Type analog-to-digital converter.
The method according to claim 6,
Wherein the output unit further comprises an output register module having a D-flip-flop structure and receiving an output signal of the SAR module as a clock and storing a value and outputting a digital output signal.

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