JP2020036255A - A/d conversion circuit - Google Patents

Abstract

To obtain an A/D conversion circuit in which an ADC performs sampling and holding at an arbitrary timing.SOLUTION: An A/D conversion circuit comprises a DAC 24 performing comparison potential generation operation generating a prediction potential for a sampling potential on the basis of a digital value, a comparator 23 for converting the sampling potential into a digital value by performing potential comparison operation for comparing the sampling potential with the prediction potential, and A/D converters 2a, 2b (hereinafter, ADC) including a sequential comparison data generator 25 for storing the converted digital value and outputting the digital value to the DAC. Hold operation in multiple ADCs is executed at a timing synchronous to the system clock, in a period when at least the comparison potential generation operation is not executed, and in each of the multiple ADCs, the comparison potential generation operation and the potential comparison operation are executed multiple times during one period of system clock.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an A / D conversion circuit including a converter for converting an analog value to a digital value.

  2. Description of the Related Art There is known an A / D conversion circuit that includes a plurality of successive approximation type digital-to-analog converters (hereinafter, ADCs) having an input potential sampling mechanism and supplies power to a plurality of ADCs with a common power supply. . In this A / D conversion circuit, the conversion operation of the ADC may generate noise in the power supply. When the ADC finishes sampling and holds the input potential at a time when noise is superimposed on the power supply by another ADC operation, the sampling and holding result is determined to be an erroneous value. For this reason, a correct conversion result cannot be obtained. Therefore, holding the sampling potential during the conversion operation of another ADC must be avoided.

  In Patent Document 1, as a method for avoiding this, at the time when the sampling potential is held, the operations of all ADCs during the other conversion operations are temporarily stopped.

Japanese Patent No. 5035997

  However, in Patent Literature 1, when a plurality of ADCs are operating in parallel, when a certain ADC is performing a conversion operation, and when a plurality of ADCs issue requests to hold one after another, the conversion operation is performed. One ADC must stop its operation until the hold of all other ADCs is completed.

  That is, the conversion operation end time of the ADC is affected by the operation of the other ADC, and the conversion end time cannot be scheduled and the operation cannot be completed on the expected schedule. This can be a fatal problem in applications where processing must be performed on a fixed schedule.

  It is an object of the present invention to provide an A / D conversion circuit in which each ADC can sample and hold at an arbitrary timing.

  An A / D conversion circuit according to an embodiment of the present invention includes a sampling and holding circuit (hereinafter, referred to as an SH circuit) for sampling and holding an analog potential, and digitally converting an analog predicted potential predicted with respect to the sampling potential of the SH circuit. A comparison potential creation circuit that performs a comparison potential creation operation that is created based on a value, a comparator that performs a potential comparison operation that compares the sampling potential with the predicted potential, and converts the sampling potential into a digital value, A plurality of ADCs each including a successive comparison data generator that stores the digital value and outputs the stored digital value to the comparison potential generation circuit; and a comparison potential generation operation and the potential comparison operation are performed by a system clock. Is controlled by another ADC control clock (hereinafter, ADC clock), The cycle of the ADC clock is faster than the cycle of the system clock, comprising: an ADC clock generator configured to generate the ADC clock from the system clock; At the same timing, the operation is performed at least during a period in which the comparison potential generation operation is not performed. In each of the plurality of ADCs, the comparison potential generation operation and the potential comparison operation are performed during one cycle of the system clock. It is executed once.

  An A / D conversion circuit according to another embodiment of the present invention includes a clock generator that has a frequency higher than a system clock and generates an ADC control clock (hereinafter, ADC clock) synchronized with the system clock. A sampling and holding circuit (hereinafter, referred to as an SH circuit) for sampling and holding an analog potential and holding the analog potential at a timing synchronized with the system clock, and a sampling potential of the SH circuit at a timing synchronized with the ADC clock. A comparison potential generation circuit that performs a comparison potential generation operation for generating an analog predicted potential based on a digital value, and a potential comparison that compares the sampling potential with the prediction potential at a timing synchronized with the ADC clock. Operate the sampling potential to the digital And a serial comparison data generator that stores the digital value converted by the comparator and outputs the stored digital value to the comparison potential generation circuit, wherein the ADC clock Is characterized in that the magnitude of the current flowing through the comparison potential generation circuit when the comparison potential generation operation is performed is proportional to the comparison potential generation speed.

  According to the A / D conversion circuit of the present invention, it is possible to provide an A / D conversion circuit capable of sampling and holding each ADC at an arbitrary timing.

1 is a configuration block diagram of an A / D conversion circuit according to a first embodiment of the present invention. 3A is a diagram illustrating a comparison potential generation operation and a potential comparison operation of an ADC of the A / D conversion circuit according to the first embodiment, and FIG. FIG. 7A illustrates a state where the power is held at an erroneous potential due to power supply noise due to a comparison potential generation operation of the ADC of the A / D conversion circuit according to the first embodiment, and FIG. FIG. FIG. 4 is a diagram illustrating a state where a plurality of ADCs of the A / D conversion circuit according to the first embodiment operate synchronously and at the same timing. FIG. 5 is a diagram illustrating a plurality of ADC clocks that control the time of the comparison potential generation operation and the time of the potential comparison operation in the ADC clock generator of the A / D conversion circuit according to the first embodiment. FIG. 5 is a diagram illustrating a clock that satisfies the relationship of “comparison time of comparison potential generation operation + time of potential comparison operation <delay time of delay circuit” in the ADC clock generator of the A / D conversion circuit according to the first embodiment. FIG. 5 is a diagram illustrating a state in which a 3-bit conversion operation is performed during one cycle of a system clock in the A / D conversion circuit according to the first embodiment. FIG. 5 is a diagram illustrating a state in which the ADC performs a hold operation in synchronization with a system clock in the A / D conversion circuit according to the first embodiment. FIG. 4 is an operation diagram of each unit of the A / D conversion circuit according to the first embodiment.

  Hereinafter, an A / D conversion circuit according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration block diagram of an A / D conversion circuit according to the first embodiment of the present invention.

  The A / D conversion circuit includes an ADC clock generator 1, ADCs 2a and 2b (hereinafter, ADCs) that sample an input potential, an ADC clock generator 1, and flip-flops (FFs) 3a and 3b. In this example, two ADCs are used, but three or more ADCs may be provided.

  The ADCs 2a and 2b include switches 21a and 21b, sampling capacitors 22a and 22b, comparators 23a and 23b, digital / analog converters (DACs) 24a and 24b, and successive comparison data generators 25a and 25b. The power supply Vcc supplies power to the ADCs 2a and 2b.

  After storing the input analog potential in the sampling capacitors 22a and 22b (sampling), the ADCs 2a and 2b separate (hold) the input and the sampling capacitors 22a and 22b with the switches 21a and 21b (hold) and store them in the sampling capacitors 22a and 22b. The potential is converted into a digital value by the comparators 23a and 23b (conversion operation). The switches 21a and 21b and the sampling capacitors 22a and 22b correspond to a sampling and holding circuit (SH circuit) of the present invention. The hold operation in the ADCs 2a and 2b is executed at a timing synchronized with a system clock described later.

  The digital / analog converters (DACs) 24a and 24b correspond to the comparison potential generation circuit of the present invention, and generate a comparison potential generation operation for generating an analog predicted potential predicted with respect to the sampling potential of the SH circuit based on a digital value. I do.

  The comparators 23a and 23b perform a potential comparison operation of comparing the sampling potential of the SH circuit with the predicted potential, and convert the sampling potential into a digital value. The successive comparison data generators 25a and 25b are constituted by successive comparison registers, store the digital values of the comparators 23a and 23b for each bit, and convert the stored digital values into digital / analog converters (DACs). 24a and 24b.

  The ADCs 2a and 2b generally convert an analog potential into a digital value by performing a comparison operation several times with a resolution bit. For example, in the case of a 12-bit resolution ADC, 12 comparison operations are required. If this comparison operation is controlled by a clock, the ADC conversion operation of 12-bit resolution requires a 12-cycle clock.

  Here, when the comparison operation time of the ADCs 2a and 2b is sufficiently faster than the system clock, for example, the ADCs 2a and 2b are operated by the system clock by applying a clock having a frequency twice the system clock to the ADCs 2a and 2b. The converted value can be obtained in half the time as compared with the time.

  The ADC clock generator 1 generates an ADC clock. The ADCs 2 a and 2 b operate with the ADC clock generated by the ADC clock generator 1. The ADC clock has a higher frequency than the system clock that controls the entire LSI. That is, the cycle of the ADC clock is shorter than the cycle of the system clock.

  The ADC clock is generated based on, for example, the rising edge timing of the system clock and the timing delayed by the delay circuit. The ADC clock generates clock pulses of a plurality of cycles fixed every one cycle of the system clock.

  The ADC clock generator 1 includes a delay circuit 11 (corresponding to a first delay circuit) for delaying a system clock, an inversion circuit 12 for inverting the system clock delayed by the delay circuit 11, an output of the inversion circuit 12, and a system clock. AND circuit 13 that outputs a logical product of the outputs to the delay circuit 14a and a logical sum of outputs of the odd-numbered delay circuits 14a, 14c, and 14e among the plurality of delay circuits 14a to 14f to the DACs 24a and 24b. The circuit includes a single OR circuit 16 and a second OR circuit 15 that outputs the logical sum of the outputs of the even-numbered delay circuits 14b, 14d, and 14f among the plurality of delay circuits 14a to 14f to the comparators 23a and 23b. The ADC clock generator 1 generates an ADC clock having a higher frequency than the system clock and synchronized with the system clock.

  The flip-flops (FF) 3a and 3b generate conversion start signals CS1 and CS2 in synchronization with the system clock, and output the conversion start signals CS1 and CS2 to the switches 21a and 21b and the successive comparison data generators 25a and 25b. , The time when the sampling, holding, and conversion operations are started is controlled in synchronization with the system clock.

  Next, the ADCs 2a and 2b generate noise in the course of the conversion operation. The operation of generating noise will be described. The ADCs 2a and 2b perform a "conversion operation" for converting the potentials stored in the sampling capacitors 22a and 22b into digital values. The “conversion operation” includes, as shown in FIG. 2A, a comparison potential creation operation for creating a predicted potential predicted with respect to a sampled sampling potential, and a potential comparison operation for comparing the predicted potential with the sampling potential. Are divided into the following two operations.

  The ADCs 2a and 2b repeat the comparison potential generation operation and the potential comparison operation by the number of resolution bits. Noise to the power supply Vcc is generated at the time of the comparison potential generation operation, as shown in FIG.

  Next, the hold time will be described. As shown in FIG. 3A, when another ADC performs a hold while a certain ADC performs the comparison potential generation operation, the other ADC holds the erroneous sampling potential due to power supply noise caused by the comparison potential generation operation. The ADC cannot obtain a correct conversion result.

  As shown in FIG. 3B, when one ADC is other than the comparison potential generation operation, that is, when another ADC performs hold while stopping, sampling, or during the potential comparison operation, the power supply noise is reduced. Since the level is low, the ADC can obtain a correct conversion result. Also, as shown in FIG. 4, even when a plurality of ADCs operate synchronously and at the same timing, the ADC can obtain a correct conversion result.

  Next, the ADC clock generated by the ADC clock generator 1 will be described. As shown in FIG. 5, for example, the ADC clock generator 1 includes a plurality of delay circuits 14a to 14f connected in series, and a plurality of ADCs by sequentially delaying a system clock by the plurality of delay circuits 14a to 14f. A clock is generated, and the timing of the comparison potential generation operation (DAC operation) and the timing of the potential comparison operation are controlled by the DAC operation clock and the comparison operation clock. It is desirable that the clock cycle be fast as long as it satisfies the sum of the comparison potential generation operation time and the potential comparison operation time.

  It is necessary to set the time for the comparison potential generation operation + the time for the potential comparison operation <the cycle of the ADC clock.

  If the ADC clock generator 1 is provided to generate a high-speed ADC clock, a high-speed ADC circuit can be realized even when the frequency of the LSI system clock is low. The ADC clock generator 1 can be realized by, for example, the delay circuits 11, 14a to 14f and simple logic circuits 12, 13, 15, 16 shown in FIG. Note that the ADC clock generator 1 may use another clock generation circuit system as long as the ADC clock having the above characteristics can be obtained in synchronization with the timing of the system clock.

  The time for the comparison potential generation operation and the time for the potential comparison operation fluctuate due to variations in LSI devices and the use conditions (power supply voltage, temperature) of the LSI. In order to obtain a stable operation, it is desirable that the time for the comparison potential generation operation, the time for the potential comparison operation, and the delay time of the delay circuit are designed to be equal to the conditions.

  As shown in FIG. 6, when the time of the comparison potential generation operation and the time of the potential comparison operation are not accurately matched with the delay time of the delay circuit 14a, for example, the time of the comparison potential generation operation + the potential comparison operation It is necessary to design a clock so as to satisfy the following relationship: time <delay time of the delay circuit.

  The delay time of the delay circuit is, for example, a total delay time of the delay circuit 14b and the delay circuit 14c, and is a cycle of the ADC clock. The cycle of the ADC clock is the cycle of the DAC operation clock or the cycle of the comparison operation clock.

  Next, a problem when the ADC clock is asynchronous with respect to the system clock will be described. The ADC clock is asynchronous with respect to the system clock. The system operates with the system clock, and the ADC operates with the ADC clock. If the system clock and the ADC clock are asynchronous, the system cannot know the operation state of the ADC during the conversion operation (whether the comparison potential generation operation or the potential comparison operation is being performed).

  It is desirable that the ADC can be held at any time from the system. However, if the system cannot know the operation state of another ADC, the ADC cannot hold at the correct timing.

  In order to solve this problem, a rule for the ADC clock is provided as follows to ensure that no other ADC is performing the comparison potential generation operation when the system causes the ADC to perform the hold operation.

  ADC clock provided with a delay circuit in which n is an integer of 2 or more that satisfies the cycle time of comparison potential generation operation time + potential comparison operation time <delay circuit delay time, and delay circuit delay time × n <system clock cycle The generator 1 generates n ADC clocks during one cycle of the system clock.

  The ADCs 2a and 2b perform the comparison potential generation operation and the potential comparison operation n times at a timing synchronized with the n clocks of the ADC clock. That is, the comparison potential generation operation and the potential comparison operation are executed by a plurality of circuits during one cycle of the system clock. Accordingly, the ADCs 2a and 2b perform a conversion operation for n bits during one cycle of the system clock and stop.

  This conversion operation is shown in FIG. FIG. 7 shows an example in which a 3-bit conversion operation is performed during one cycle of the system clock. The conversion operation of the ADCs 2a and 2b starts at the rise of the system clock, and stops after performing the conversion operation for 3 bits. At the next rise of the system clock, the conversion operation for the next three bits is restarted.

  According to the A / D conversion circuit, as shown in FIG. 8, the ADC conversion operation is always stopped at the moment when the system clock rises, and it is ensured that no noise is generated at this time. Therefore, the system operating with the system clock can cause the ADC to execute the hold operation at the time when an arbitrary system clock rises. That is, it is not necessary to consider the operation state of another ADC, and it is not necessary to control another ADC.

  Further, conventionally, when the ADC is held, it is necessary to perform a process of stopping the operation of the other ADC during the conversion operation. However, in the present invention, in an arbitrary cycle when viewed from the system operating with the system clock, The ADC can hold.

  Further, according to the present invention, it is not necessary to consider the operation state of another ADC and to control another ADC for an action held by a certain ADC, so that the mechanism of ADC control is simple. is there.

  Also, since the ADC operation is not stopped halfway by another ADC operation, the conversion operation time of the ADC can be completed at a predetermined time expected from the operation start time, and the processing schedule is not disrupted.

  FIG. 9 shows an operation diagram of each unit of the A / D conversion circuit according to the first embodiment. The conversion operation of the ADCs 2a and 2b shown in FIG. 1 will be described with reference to FIG. First, when the system clock rises at time t0, the flip-flops 3a and 3b output the conversion start signals CS1 and CS2 to the switches 21a and 21b and the successive comparison data generators 25a and 25b in synchronization with the system clock.

  Analog inputs 1 and 2 are input to terminals Tm1 and Tm2, and sampling is performed by switches 21a and 21b and sampling capacitors 22a and 22b.

  At time t10, the ADC 2a holds the sampling potential and starts the conversion operation. At time t11, the system clock is delayed by the delay circuit 14a, and the comparison potential generation operation clock (DAC operation clock) via the OR circuit 16 is output to the DAC 24a. The DAC 24a performs a DAC operation (comparison potential generation operation). At this time, power supply noise occurs.

  Next, from time t12 to time t13, the system clock is delayed by the delay circuit 14b, and the potential comparison operation clock (comparison operation clock) via the OR circuit 15 is output to the comparator 23. The comparator 23 performs a comparison operation. At this time, power supply noise does not occur.

  At time t14, the system clock is delayed by the delay circuit 14c, and the DAC operation clock via the OR circuit 16 is output to the DAC 24a. The DAC 24a performs a DAC operation. At this time, power supply noise occurs.

  Next, from time t15 to time t16, the system clock is delayed by the delay circuit 14d, and the comparison operation clock via the OR circuit 15 is output to the comparator 23. The comparator 23 performs a comparison operation. At this time, power supply noise does not occur.

  At time t17, the system clock is delayed by the delay circuit 14e, and the DAC operation clock via the OR circuit 16 is output to the DAC 24a. The DAC 24a performs a DAC operation. At this time, power supply noise occurs.

  Next, from time t18 to time t19, the system clock is delayed by the delay circuit 14f, and the comparison operation clock via the OR circuit 15 is output to the comparator 23. The comparator 23 performs a comparison operation. At this time, power supply noise does not occur.

  Here, the delay time (for example, time t11-t14) of the delay circuit is larger than the total time of the DAC operation and the total time of the comparison operation. Further, the delay time of the delay circuit × 3 <the period of the system clock (for example, time t10-t20) is satisfied.

  Further, the sampling potential of the ADC 2b is held at the rising timing of the system clock (time t20).

  As described above, according to the A / D conversion circuit of the first embodiment, the cycle of the ADC clock is longer than the total time of the comparison potential generation operation time and the potential comparison operation time, and is one cycle of the system clock. Since n (n ≧ 2) ADC clocks are generated and the SH circuits 21a, 21b, 22a, and 22b sample and hold the analog potential at the rise of the system clock, each ADC can sample and hold at an arbitrary timing. . Further, an accurate value can be determined without being affected by power supply noise due to the ADC conversion operation at the time of ADC sampling and holding.

  The speed of the comparison potential generation operation (DAC operation) varies depending on variations in LSI devices and usage conditions. When the DAC operation is fast, the magnitude of the current and the rising speed associated therewith increase, and the noise superposition on the power supply increases. When the DAC operation is slow, the magnitude of the current and the rising speed are also slow, so that the superposition of noise is reduced. According to the present invention, when the DAC operation is fast, the ADC clock is fast, and when the DAC operation is slow, the ADC clock is slow.

  In other words, the frequency of the ADC clock is proportional to the current flowing through the DAC during DAC operation. Therefore, when the DAC operation speeds up and the noise increases, the ADC clock also occurs earlier in the cycle of the system clock than in the case where it is less.

  For this reason, the time for which the noise is established has a margin, and the operation principle is less affected by the noise. Conversely, when the DAC operation is slow, the current is reduced and the noise is also reduced. Therefore, if the conditions for generating the ADC clock with respect to the system clock are satisfied, the influence of the noise is reduced.

  In this embodiment, in order to make the explanation of the operation easy to understand, the ADC clock includes a comparison potential generation operation clock (DAC operation clock) for controlling the comparison potential generation operation and a potential comparison operation for controlling the potential comparison operation. Although an example in which two clock signals called clocks (comparison operation clocks) are described, the ADC clock may be a plurality of clock signals prepared for each operation, or one clock signal may be used as the comparison potential. The creation operation and the potential comparison operation may be controlled.

1 ADC clock generators 2a, 2b ADC
3a, 3b flip-flop circuit (FF)
11, 14a to 14f Delay circuit 12 Inverting circuit 13 Logical product circuit 15, 16 Logical sum circuit 21a, 21b Switch 22a, 22b Sampling capacity 23a, 23b Comparator 24a, 24b Digital / analog converter (DAC)
25a, 25b Successive comparison data generator Vcc power supply

Claims (7)

A sampling and holding circuit (hereinafter, referred to as an SH circuit) for sampling and holding an analog potential, and a comparison potential creation operation for creating a comparison potential creation operation for creating a predicted analog potential based on a digital value with respect to the sampling potential of the SH circuit. Circuit, a comparator for performing a potential comparison operation of comparing the sampling potential and the predicted potential and converting the sampling potential to the digital value, storing the digital value converted by the comparator and storing the digital value A plurality of A / D converters (hereinafter, ADCs) each including a successive comparison data generator that outputs
The hold operation in the plurality of ADCs is performed at a timing synchronized with a system clock at least during a period in which the comparison potential generation operation is not performed,
An A / D conversion circuit, wherein in each of the plurality of ADCs, the comparison potential generation operation and the potential comparison operation are performed a plurality of times during one cycle of the system clock. A clock generator that generates an ADC clock shorter than a cycle of the system clock and synchronized with the system clock;
2. The A / D conversion circuit according to claim 1, wherein the comparison potential creation operation and the potential comparison operation are performed in synchronization with the ADC clock.   The A / D conversion circuit according to claim 2, wherein the hold operation is performed in synchronization with a timing synchronized with the system clock.   The A / D conversion circuit according to claim 2, wherein the clock generator generates n ADC clocks (n is a natural number of 2 or more) during one cycle of the system clock.   3. The A / D conversion circuit according to claim 2, wherein a cycle of the ADC clock is longer than a total time of the comparison potential generation operation time and the potential comparison operation time.   3. The A / D conversion circuit according to claim 2, wherein a cycle of the system clock is longer than a total time of n ADC clocks. A clock generator having a frequency higher than the system clock and generating an ADC clock synchronized with the system clock;
A sampling and holding circuit (hereinafter referred to as SH circuit) for sampling and holding an analog potential and holding the analog potential at a timing synchronized with the system clock;
A comparison potential creation circuit that performs a comparison potential creation operation of creating an analog predicted potential based on a digital value with respect to a sampling potential of the SH circuit at a timing synchronized with the ADC clock;
A comparator that performs a potential comparison operation of comparing the sampling potential with the predicted potential at a timing synchronized with the ADC clock and converts the sampling potential into the digital value;
A successive comparison data generator that stores the digital value converted by the comparator and outputs the stored digital value to the comparison potential generation circuit;
An A / D converter circuit, wherein a frequency of the ADC clock is proportional to a magnitude of a current flowing through the comparison potential creation circuit and a comparison potential creation speed when the comparison potential creation operation is performed.

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