CN117040535B - Phase indicating circuit, converter chip and multi-chip synchronization system - Google Patents

Phase indicating circuit, converter chip and multi-chip synchronization system Download PDF

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CN117040535B
CN117040535B CN202311301564.4A CN202311301564A CN117040535B CN 117040535 B CN117040535 B CN 117040535B CN 202311301564 A CN202311301564 A CN 202311301564A CN 117040535 B CN117040535 B CN 117040535B
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clock
module
delay
phase
sampling
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CN117040535A (en
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刘家瑞
郁发新
王志宇
陈华
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention provides a phase indication circuit, a converter chip and a multi-chip synchronization system, wherein the phase indication circuit comprises a delay line module, a parallel sampling module, a phase indication module and a register module; the delay line module receives the synchronous signal and is used for carrying out 2 on the synchronous signal M Stage delay and generate 2 M The delay signals M are integers greater than 1; the parallel sampling module is connected with the delay line module, takes the reference clock as the sampling clock, and is used for the period of 2 M Synchronous sampling of the delay signals and generation of 2 M Sampling signals; the phase indication module is connected with the parallel sampling module, takes the reference clock as the working clock, and is according to 2 M The values of the sampling signals indicate the phase deviation of the synchronous signal relative to the reference clock, and the synchronous clock is generated when the phase deviation is smaller than the preset deviation; the register module is connected with the phase indication module and is used for indicating the phase of 2 M The sampled signals are stored. The invention solves the problem that the synchronous signal cannot be subjected to phase deviation indication in the prior art.

Description

Phase indicating circuit, converter chip and multi-chip synchronization system
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a phase indication circuit, a converter chip, and a multi-chip synchronization system.
Background
When a high-speed analog-to-digital converter (ADC) or digital-to-analog converter (DAC) chip is applied to a scene requiring multi-chip synchronization, two synchronous global signals are often required; one is a reference clock (commonly named REFCLK) which provides a synchronized sampling clock for each ADC/DAC chip, ensuring that each chip samples at the same time; the other is a synchronization signal (commonly named SYSREF) that scales the phase for each ADC/DAC chip so that the sampled data is synchronized.
However, if the system scale is large, the distance between the chips is long, which may cause the SYSREF to reach the chips with a large deviation; in addition, if the frequency of SYSREF is low, the rising or falling edge of the signal is slow, which may cause a system synchronization error. Therefore, it is necessary to indicate the phase deviation of SYSREF in order for the system to make a corresponding phase adjustment.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a phase indication circuit, a converter chip and a multi-chip synchronization system for solving the problem that the phase deviation indication cannot be performed on the synchronization signal in the prior art.
To achieve the above and other related objects, the present invention provides a phase indicating circuit comprising: the device comprises a delay line module, a parallel sampling module, a phase indication module and a register module;
the delay line module receives a synchronous signal and is used for carrying out 2 on the synchronous signal M Stage delay and generate 2 M A delay signal, wherein M is an integer greater than 1;
the parallel sampling module is connected with the delay line module, takes a reference clock as a sampling clock, and is used for the period of 2 M Synchronous sampling is carried out on each time delay signal to generate 2 M Sampling signals;
the phase indication module is connected with the parallel sampling module, takes the reference clock as a working clock and is according to 2 M Values of the sampling signals indicate a phase deviation of the synchronization signal relative to the reference clock, and generate a synchronization clock when the phase deviation is less than a preset deviation;
the register module is connected with the phase indication module and is used for performing phase adjustment on 2 M And storing the sampling signals.
Optionally, the delay line module comprises 2 M The circuit structure of each delay unit is the same, and the delay unit comprises a first inverter, a second inverter and a delay amount configurator;
the input end of the first inverter is used as the input end of the delay unit, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is used as the output end of the delay unit; the delay amount configurator is connected between the output end of the first phase inverter and the reference ground and is used for configuring the delay amount of the delay unit;
the delay amount of each delay unit is the same, and the total delay amount of the delay line module is greater than half of the clock period of the reference clock and less than the clock period of the reference clock.
Optionally, the delay amount configurator comprises 2 N The circuit structure of each switch capacitor part is the same, and comprises a switch and a capacitor which are connected in series, and each switch is controlled by a corresponding switch control signal; wherein N is an integer greater than 1.
Optionally, the parallel sampling module comprises 2 M A number D of flip-flops;
2 M the clock end of each D trigger is connected with the reference clock, 2 M The data ends of the D triggers are correspondingly connected with 2 M And each of the delay signals, 2 M The output of each D flip-flop generates 2 M And each of the sampling signals.
Optionally, the synchronization signal comprises a single pulse signal or a periodic pulse signal; the D flip-flop includes a falling edge D flip-flop when a first rising edge of the synchronization signal and a first rising edge of the reference clock arrive at the same time; the D flip-flop includes a rising edge D flip-flop when a first falling edge of the synchronization signal and a first rising edge of the reference clock arrive at the same time.
Optionally, the phase indication module includes a clock selection unit and an indication processing unit;
the clock selection unit is controlled by a system starting signal to start working, outputs the reference clock as a working clock to the indication processing unit, and performs output reset according to a clock reset signal;
the indication processing unit is connected with the clock selection unit and the parallel sampling module and is used for processing the clock according to 2 M The values of the sampling signals are indicative of the phase of the synchronization signal relative to the reference clockAnd outputting the sampling signal corresponding to the first-stage delay as the synchronous clock when the phase deviation is smaller than the preset deviation, and generating the clock reset signal according to an indication result.
Optionally, the phase indication circuit further comprises: the manual selection module is connected with the parallel sampling module and is used for selecting and controlling the signal according to the sequence from 2 M And selecting one of the sampling signals as the synchronous clock output.
The invention also provides a converter chip comprising a phase indication circuit as described above.
Optionally, the converter chip comprises an analog-to-digital converter chip or a digital-to-analog converter chip.
The present invention also provides a multi-chip synchronization system comprising at least two converter chips as described above.
As described above, the phase indication circuit, the converter chip and the multi-chip synchronization system of the invention utilize the reference clock to perform phase deviation indication on the synchronization signal through the design of the delay line module, the parallel sampling module, the phase indication module and the register module, thereby being beneficial to performing phase adjustment on the synchronization signal; the circuit has simple structure, does not need a high-frequency clock, is easy to integrate on a chip, and has lower power consumption.
Drawings
Fig. 1 is a schematic diagram of a phase indication circuit.
Fig. 2 shows a schematic structure of the delay line module.
Fig. 3 shows a schematic diagram of the structure of the delay unit.
Fig. 4 shows a schematic structure of a switched capacitor section.
Fig. 5 shows a schematic structure of a parallel sampling module.
Fig. 6 is a schematic diagram of a phase indication module.
Fig. 7 is a schematic diagram showing the states of the sampling signals stored in the register modules of the respective converter chips and their corresponding characterizations in a multi-chip synchronous system.
Fig. 8 shows waveforms of corresponding nodes of the phase indication circuit in each of the converter chips corresponding to the second column of fig. 7.
Description of element reference numerals
The device comprises a 10-phase indicating circuit, a 100-delay line module, a 110-delay unit, a 111-delay amount configurator, a 111a switched capacitor part, a 200-parallel sampling module, a 210D trigger, a 300-phase indicating module, a 310-clock selecting unit, a 320-indicating processing unit, a 400-register module and a 500-manual selecting module.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a phase indication circuit 10, which includes a delay line module 100, a parallel sampling module 200, a phase indication module 300 and a register module 400; further, a manual selection module 500 is included. Wherein:
the delay line module 100 receives the synchronization signal SYSREF and performs 2 on the synchronization signal SYSREF M Stage delay and generate 2 M Delayed signals P2 M -1:0]M is an integer greater than 1. Wherein the synchronization signal SYSREF comprises a single pulse signal or a periodic pulse signal.
Specifically, as shown in fig. 2 and 3, the delay line module 100 includes 2 M Delay of cascadeThe unit 110, the circuit structure of each delay unit 110 is the same, including the first inverter INV1, the second inverter INV2 and delay amount configurator 111; the input end of the first inverter INV1 is used as the input end of the delay unit 110, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, and the output end of the second inverter INV2 is used as the output end of the delay unit 110; the delay amount configurator 111 is connected between the output end of the first inverter INV1 and the reference ground, and is used for configuring the delay amount of the delay unit 110.
As an example, as shown in fig. 4, the delay amount configurator 111 includes 2 N A plurality of parallel switched capacitor portions 111a, each switched capacitor portion 111a having the same circuit structure and including a switch S1 and a capacitor C1 connected in series, each switch S1 being controlled by a corresponding switch control signal, i.e. 2 N The corresponding switches are 2 N Switch control signals DC 2 N -1:0]N is an integer greater than 1.
For delay element 110, pass 2 N Switch control signals DC 2 N -1:0]Respectively control 2 N The switches S1 are opened or closed to control the number of the switched capacitors C1, thereby controlling the total capacity of the switched capacitors, thereby configuring the delay amount of the delay unit 110. In practical use, 2 of the switched capacitor portions 111a N The capacities of the capacitors C1 are the same, and when the delay amount is configured, the larger the number of the accessed capacitors C1 is, the larger the total capacity of the accessed capacitors is, and the larger the delay amount of the delay unit 110 is.
For the delay line module 100, the delay amounts of the delay units 111 are the same, and the total delay amount of the delay line module 110 is greater than half the clock period of the reference clock REFCLK and less than the clock period of the reference clock REFCLK, i.e., T REFCLK /2<2 M *T DELAY <T REFCLK ，T DELAY T is the delay amount of the delay unit 111 REFCLK Is the clock period of the reference clock REFCLK.
The parallel sampling module 200 is connected to the delay line module 100, and takes the reference clock REFCLK as the sampling clock, for 2 M Delayed signals P2 M -1:0]Synchronous sampling and generating 2 M Sampling signal Q [2 ] M -1:0]。
Specifically, as shown in FIG. 5, the parallel sampling module 200 includes 2 M A number D of flip-flops 210;2 M The clock terminals of the D flip-flops 210 are connected to a reference clock REFCLK,2 M Data end corresponding connection 2 of D flip-flops 210 M Delayed signals P2 M -1:0]，2 M The output of the D flip-flops 210 generates 2 M Sampling signal Q [2 ] M -1:0]。
In practical applications, the timing of the synchronization signal SYSREF and the reference clock REFCLK are divided into two cases, the first case is that the first rising edge of the synchronization signal SYSREF and the first rising edge of the reference clock REFCLK arrive at the same time, and the second case is that the first falling edge of the synchronization signal SYSREF and the first rising edge of the reference clock REFCLK arrive at the same time.
For the two cases, the trigger time of the D flip-flop 210 in the parallel sampling module 200 is slightly different; the first case, i.e. the case where the first rising edge of the synchronization signal SYSREF and the first rising edge of the reference clock REFCLK arrive at the same time, the D flip-flop 210 in the parallel sampling module 200 is a falling edge D flip-flop; the second case, i.e. the case where the first falling edge of the synchronization signal SYSREF and the first rising edge of the reference clock REFCLK arrive at the same time, the D flip-flop 210 in the parallel sampling module 200 is a rising edge D flip-flop.
It should be noted that, when the synchronization signal SYSREF is a single pulse signal, the first rising edge of the synchronization signal SYSREF is a rising edge of the single pulse signal, and the first falling edge of the synchronization signal SYSREF is a falling edge of the single pulse signal; when the synchronization signal SYSREF is a periodic pulse signal, the first rising edge of the synchronization signal SYSREF is the rising edge of the first pulse signal, and the first falling edge of the synchronization signal SYSREF is the falling edge of the first pulse signal.
The phase indication module 300 is connected to the parallel sampling module 200 and uses the reference clock REFCLK as an operation clock according to 2 M Sampling signal Q [2 ] M -1:0]Indicates a phase deviation of the synchronization signal SYSREF with respect to the reference clock REFCLK, and generates the synchronization clock SYNC when the phase deviation is less than a preset deviation.
Specifically, as shown in fig. 6, the phase indication module 300 includes a clock selection unit 310 and an indication processing unit 320.
The clock selecting unit 310 is controlled by the system start signal ST to start working, and outputs the reference clock REFCLK as a working clock to the instruction processing unit 320, and performs output reset according to the clock reset signal RST, so that the instruction processing unit 320 stops working, thereby achieving the purpose of reducing power consumption.
The instruction processing unit 320 is connected to the parallel sampling module 200 and the clock selection unit 310 for performing the operations according to 2 M Sampling signal Q [2 ] M -1:0]Indicates the phase deviation of the synchronous signal SYSREF relative to the reference clock REFCLK, and when the phase deviation is smaller than the preset deviation, the sampling signal Q [2 ] corresponding to the first stage delay M -1]As a synchronous clock SYNC output, and generates a clock reset signal RST according to the indication result.
In one possible implementation, by configuration 2 M Sampling signal Q [2 ] M -1:0]The preset deviation is set by comparing the sampled value with the configuration value to achieve a comparison of the phase deviation with the preset deviation.
The register module 400 is connected to the phase indication module 300 for pair 2 M Sampling signal Q [2 ] M -1:0]The storing is performed so as to facilitate the subsequent phase adjustment, and reduce or even eliminate the phase deviation of the synchronization signal SYSREF.
The manual selection module 500 is connected with the parallel sampling module 200 for selecting the control signal CTL from 2 M Sampling signal Q [2 ] M -1:0]One of which is selected as the synchronization clock SYNC output. In practice, the manual selection module 500 generally works when the phase indication module 300 has no output, and is controlled from 2 according to the system requirement M Sampling signal Q [2 ] M -1:0]One of the outputs is selected.
Next, please refer to fig. 1 and 6, the operation of the phase indication module 300 and the register module 400 of the present embodiment will be described.
Upon detecting the rising edge of the synchronization start signal ST, the clock selection unit 310 starts operation and outputs the reference clock REFCLK as an operation clock to the instruction processing unit 320;
an initial state indicating that the processing unit 320 starts to operate, pulls the synchronization clock SYNC to a low level, and thereafter starts to see 2 every cycle M Sample signals Q [0:2 ] M -1]Is a value of (2);
if 2 M Sample signals Q [0:2 ] M -1]The value of (1) is all 0, which indicates that the circuit does not sample the synchronization signal SYSREF, indicating that the processing unit 320 has no output, the synchronization clock SYNC remains unchanged and is still at a low level, indicating that the processing unit 320 continues to operate;
if 2 M Sample signals Q [0:2 ] M -1]In the value of (1), Q [0:1 ]]At least two consecutive 1's, e.g. Q2, appear in the remainder of 00 M -2:2 M -1]Is 11, or Q2 M -2:2 M -1]At 00 but two consecutive 1's occur in the other values, representing that the phase deviation is smaller than the preset deviation, the synchronization clock SYNC is set to Q [2 ] M -1]And will 2 M Sample signals Q [0:2 ] M -1]The value of (2) is output to the register module 400 to be stored and then stopped, i.e., a clock reset signal RST is generated to stop the instruction processing unit 320 from operating by resetting the operating clock;
if 2 M Sample signals Q [0:2 ] M -1]In the value of (1), Q [0:1 ]]01, the remaining values being all 1 or at most only one 0, representing a phase deviation greater than the preset deviation, indicating that the processing unit 320 is not outputting, the synchronization clock SYNC remains unchanged, remains low, indicating that the processing unit 320 is to be 2 M Sample signals Q [0:2 ] M -1]The value of (2) is output to the register module 400 for storage and then stops working;
if 2 M Sample signals Q [0:2 ] M -1]Has a value of 1 or, alternatively, Q [0:1 ]]11, Q2 M -2:2 M -1]00, representing a system start signal timing error (i.e., one of the phase deviations being greater than the preset deviation), indicates that the processing unit 320 has no output, the synchronization clock SYNC remains unchanged, remains low, indicates that the processing unit 320 will be 2 M Sample signals Q [0:2 ] M -1]The value of (2) is output to the register module 400 for storage and then stops working;
if the above situation does not occur, the instruction processing unit 320 will be 2 M Sample signals Q [0:2 ] M -1]The value of (2) is output to the register module 400 and stored, and then continues to operate, indicating that the processing unit 320 has no output, and the synchronization clock SYNC remains unchanged and is still at a low level.
Correspondingly, the present embodiment also provides a converter chip, including the phase indication circuit 10 as described above; wherein the converter chip comprises an analog-to-digital converter chip or a digital-to-analog converter chip.
Correspondingly, the embodiment also provides a multi-chip synchronization system, which comprises at least two converter chips as described above; wherein, the types of the converter chips are the same, and are both analog-digital converter chips or digital-analog converter chips.
In the multi-chip synchronization system, the time for the synchronization signal SYSREF to reach each converter chip may be different due to the position difference of each converter chip; in order to ensure that the phase indication circuit 10 in each converter chip is able to recognize the synchronization signal SYSREF, it is required that the maximum time deviation of the synchronization signal SYSREF to reach each converter chip cannot exceed the clock period T of the reference clock REFCLK REFCLK 。
Taking the case that the multi-chip synchronization system includes 5 converter chips as an example, a process of performing phase adjustment according to the register module 400 in the multi-chip synchronization system will be described; where m=3, the clock period of the reference clock REFCLK is 100MHz, and the total delay amount of the delay line module 100 is 7.5ns.
1) The system starts, at this time, the system start signal ST jumps to the high level;
2) Transmitting a synchronization signal SYSREF to each converter chip, the synchronization signal SYSREF comprising a single pulse signal or a periodic pulse signal;
3) Checking the possible states of the register modules 400 of the phase indication circuit 10 among the 5 converter chips, the 5 converter chips are shown in fig. 7;
in the state shown in the first column, the synchronous signals SYSREF of the 5 converter chips have no phase deviation and do not need to be adjusted;
in the state shown in the second column, the phase deviation occurs in the synchronizing signals SYSREF of the 5 converter chips and the phase is linearly deviated, wherein the phase deviation of the synchronizing signals SYSREF of the first 4 converter chips is smaller than the preset deviation, and the phase deviation of the synchronizing signals SYSREF of the 5 th converter chip is larger than the preset deviation, which can be improved by respectively adjusting the delay amount of the synchronizing signals SYSREF in the phase indicating circuits 10 of the respective converter chips;
in the state shown in the third column, the phase deviation occurs in the synchronizing signals SYSREF of the 5 converter chips and the phase is in a fixed deviation, wherein the phase deviation of the synchronizing signals SYSREF of the 5 converter chips is smaller than the preset deviation, and the delay amount of the synchronizing signals SYSREF in the phase indicating circuit 10 of each converter chip can be uniformly adjusted to improve.
Taking the second column as an example, each node waveform of the phase indication circuit 10 in the 5 converter chips is as shown in fig. 8, the phase indication module 300 starts to operate at time t0, the parallel sampling module 200 samples at time t1, and the phase indication module 200 outputs the synchronization clock SYNC at time t 2.
In summary, according to the phase indicating circuit, the converter chip and the multi-chip synchronization system disclosed by the invention, the reference clock is utilized to indicate the phase deviation of the synchronization signal through the design of the delay line module, the parallel sampling module, the phase indicating module and the register module, so that the phase adjustment of the synchronization signal is facilitated; the circuit has simple structure, does not need a high-frequency clock, is easy to integrate on a chip, and has lower power consumption. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A phase indication circuit, the phase indication circuit comprising: the device comprises a delay line module, a parallel sampling module, a phase indication module and a register module;
the delay line module comprises 2 M The first delay unit receives the synchronous signal, and each delay unit generates a delay signal; the delay line module is used for carrying out 2 on the synchronous signal M Stage delay and generate 2 M The delay signals M are integers greater than 1;
the parallel sampling module is connected with the delay line module, takes a reference clock as a sampling clock, and is used for the period of 2 M Synchronous sampling is carried out on each time delay signal to generate 2 M Sampling signals;
the phase indication module is connected with the parallel sampling module, takes the reference clock as a working clock and is according to 2 M Values of the sampling signals indicate a phase deviation of the synchronization signal relative to the reference clock, and generate a synchronization clock when the phase deviation is less than a preset deviation;
the register module is connected with the phase indication module and is used for performing phase adjustment on 2 M Storing the sampling signals;
the delay amount of each delay unit is the same, and the total delay amount of the delay line module is greater than half of the clock period of the reference clock and less than the clock period of the reference clock.
2. The phase indication circuit of claim 1, wherein each of the delay cells has the same circuit structure and comprises a first inverter, a second inverter and a delay amount configurator;
the input end of the first inverter is used as the input end of the delay unit, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is used as the output end of the delay unit; the delay amount configurator is connected between the output end of the first phase inverter and the reference ground and is used for configuring the delay amount of the delay unit.
3. The phase indication circuit of claim 2 wherein the delay amount configurator comprises 2 N The circuit structure of each switch capacitor part is the same, and comprises a switch and a capacitor which are connected in series, and each switch is controlled by a corresponding switch control signal; wherein N is an integer greater than 1.
4. The phase indication circuit of claim 1 wherein the parallel sampling module comprises 2 M A number D of flip-flops;
2 M the clock end of each D trigger is connected with the reference clock, 2 M The data ends of the D triggers are correspondingly connected with 2 M And each of the delay signals, 2 M The output of each D flip-flop generates 2 M And each of the sampling signals.
5. The phase indication circuit of claim 4, wherein the synchronization signal comprises a single pulse signal or a periodic pulse signal; the D flip-flop includes a falling edge D flip-flop when a first rising edge of the synchronization signal and a first rising edge of the reference clock arrive at the same time; the D flip-flop includes a rising edge D flip-flop when a first falling edge of the synchronization signal and a first rising edge of the reference clock arrive at the same time.
6. The phase indication circuit of claim 1, wherein the phase indication module comprises a clock selection unit and an indication processing unit;
the clock selection unit is controlled by a system starting signal to start working, outputs the reference clock as a working clock to the indication processing unit, and performs output reset according to a clock reset signal;
the indication processing unit is connected with the clock selection unit and the parallel sampling module and is used for processing the clock according to 2 M The values of the sampling signals are used for indicating the synchronous signalsAnd outputting the sampling signal corresponding to the first-stage delay as the synchronous clock when the phase deviation is smaller than the preset deviation, and generating the clock reset signal according to an indication result.
7. The phase indication circuit of any one of claims 1-6, wherein the phase indication circuit further comprises: the manual selection module is connected with the parallel sampling module and is used for selecting and controlling the signal according to the sequence from 2 M And selecting one of the sampling signals as the synchronous clock output.
8. A converter chip, characterized in that it comprises a phase indication circuit according to any of claims 1-7.
9. The converter chip according to claim 8, characterized in that the converter chip comprises an analog-to-digital converter chip or a digital-to-analog converter chip.
10. A multi-chip synchronization system comprising at least two converter chips according to claim 8 or 9.
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