CN116232325A - Phase calibration circuit and chip for multiple analog-to-digital converters - Google Patents
Phase calibration circuit and chip for multiple analog-to-digital converters Download PDFInfo
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- CN116232325A CN116232325A CN202310212121.1A CN202310212121A CN116232325A CN 116232325 A CN116232325 A CN 116232325A CN 202310212121 A CN202310212121 A CN 202310212121A CN 116232325 A CN116232325 A CN 116232325A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
A phase calibration circuit and chip of a plurality of analog-to-digital converters belong to the technical field of analog-to-digital conversion, each analog-to-digital converter is connected with a training signal, and samples the training signal according to a reference clock to obtain each digital sequence signal value, wherein the digital sequence signal value comprises sampling values corresponding to each sampling moment; the deviation detector obtains phase compensation values corresponding to the analog-to-digital converters according to sampling time differences among sampling peaks of the digital sequence signal values, wherein the sampling peaks are maximum values of sampling values corresponding to sampling moments; the phase regulator performs phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter so as to output the working clock corresponding to each analog-to-digital converter, thereby counteracting the phase deviation among different analog-to-digital converters, reducing the phase error of actual sampling among each analog-to-digital converter and improving the phase consistency of a plurality of analog-to-digital converters.
Description
Technical Field
The application belongs to the technical field of analog-to-digital conversion, and particularly relates to a phase calibration circuit and a chip of a plurality of analog-to-digital converters.
Background
At present, a plurality of analog-to-digital converters integrated on a chip are required to have the phase consistency in many application scenes, but in practical application, due to noise interference among circuits on the chip, unavoidable process errors during chip manufacturing and other reasons, the phase of the analog-to-digital converters cannot achieve high consistency in practice, and cannot meet the actual needs in the use process, the prior art tries to directly reduce the interference of chip noise, process errors and the like, but is extremely difficult to avoid the interference, namely: the phase consistency of the multiple analog-to-digital converters cannot be improved.
Disclosure of Invention
The present invention provides a phase calibration circuit and a chip for a plurality of analog-to-digital converters, which aim to solve the problem that the phase consistency of the plurality of analog-to-digital converters cannot be improved due to noise interference among circuits on the chip, unavoidable process errors during chip manufacturing, and the like.
The embodiment of the application provides a phase calibration circuit of a plurality of analog-to-digital converters, which comprises: a plurality of analog-to-digital converters, a deviation detector, and a phase adjuster:
each analog-to-digital converter is configured to be connected with a training signal, and samples the training signal according to a reference clock so as to obtain each digital sequence signal value; the digital sequence signal value comprises sampling values corresponding to sampling moments;
the deviation detector is connected with each analog-to-digital converter and is configured to obtain a phase compensation value corresponding to each analog-to-digital converter according to the sampling time difference between the sampling peak values of each digital sequence signal value; the sampling peak value is the maximum value of the sampling value corresponding to each sampling time;
the phase adjuster is connected with the analog-to-digital converter and the deviation detector and is configured to perform phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter so as to output the working clock corresponding to each analog-to-digital converter.
In one embodiment, the deviation detector comprises a plurality of sub-detectors, a calculation unit and a plurality of registers;
each sub-detector is connected with each analog-to-digital converter in a one-to-one correspondence manner and is configured to acquire the peak sampling time of the sampling peak value of each digital sequence signal value;
the calculating unit is connected with each sub-detector and is used for calculating each time difference according to each peak value sampling moment and obtaining a phase compensation value corresponding to each analog-digital converter according to each time difference;
and each register is connected with the computing unit and the phase regulator and is used for recording each phase compensation value.
In one embodiment, the sub-detector comprises:
the buffer is connected with the analog-to-digital converter and is configured to record the digital sequence signal value;
the searching circuit is connected with the buffer and is configured to search the maximum value of each sampling value in the digital sequence signal value to obtain the sampling peak value, and the sampling time corresponding to the sampling peak value is taken as the peak value sampling time;
and the time stamp register is connected with the search circuit and the calculation unit and is used for recording the peak sampling time.
In one embodiment, the phase regulator comprises a plurality of sub-regulating modules connected with a plurality of registers one by one;
and each sub-regulation module is connected with each register and is configured to perform phase compensation on the reference clock according to each phase compensation value so as to output the working clock corresponding to each analog-to-digital converter.
In one embodiment, the phase compensation value is an m-bit binary value, and the m-bit binary value corresponds to the m sub-compensation signals one by one; the sub-regulation module comprises m delay units connected in series;
each delay unit is configured to access each sub-compensation signal, and delay or forward the reference clock according to each sub-compensation signal.
In one embodiment, the delay unit includes a buffer and a selector;
the input end of the buffer and the first input end of the selector are used as reference clock input ends of the delay units, the output end of the buffer is connected with the second input end of the selector, the output end of the selector is used as reference clock output ends of the delay units, and the control end of the selector is used as a sub compensation signal input end of the delay units.
In one embodiment, each analog-to-digital converter is further configured to sample each analog input signal according to an operation clock corresponding to each analog-to-digital converter to output each digital signal.
In one embodiment, the phase calibration circuit of the plurality of analog-to-digital converters further comprises:
and the signal generator is connected with the analog-to-digital converters and is configured to output the training signals.
In one embodiment, the signal generator is further configured to output a plurality of enable signals after outputting the training signal;
the phase calibration circuit further includes a plurality of tri-state gates;
each tri-state gate is connected with each analog-to-digital converter in a one-to-one correspondence manner, and each tri-state gate is also connected with the signal generator;
each of the tri-state gates is configured to access each of the analog input signals and forward each of the analog input signals in accordance with each of the enable signals.
The embodiment of the invention also provides an analog-to-digital conversion chip, and the amplifier comprises the phase calibration circuit of the plurality of analog-to-digital converters.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the deviation detector obtains phase compensation values corresponding to the analog-to-digital converters according to sampling time differences among sampling peaks of the digital sequence signal values; and the phase regulator performs phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter so as to output the working clock corresponding to each analog-to-digital converter, thereby counteracting the phase deviation among different analog-to-digital converters, reducing the phase error of actual sampling among each analog-to-digital converter and improving the phase consistency of a plurality of analog-to-digital converters.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a schematic diagram of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present application;
FIG. 2 is a waveform diagram of a training signal of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present application;
fig. 3 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a portion of an exemplary circuit of a delay unit in a phase calibration circuit of a plurality of analog-to-digital converters according to one embodiment of the present application;
fig. 8 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of another structure of a phase calibration circuit of a plurality of analog-to-digital converters according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 1 is a schematic diagram of a phase calibration circuit of a plurality of analog-to-digital converters according to a preferred embodiment of the present application, and for convenience of explanation, only the portions related to the embodiment are shown, which are described in detail below:
the phase calibration circuit of the analog-to-digital converters includes a plurality of analog-to-digital converters 100, a deviation detector 200, and a phase adjuster 300.
Each analog-to-digital converter 100 is configured to access a training signal and sample the training signal according to a reference clock to obtain each digital sequence signal value; the digital sequence signal value comprises sampling values corresponding to all sampling moments;
a deviation detector 200, connected to each analog-to-digital converter 100, configured to obtain a phase compensation value corresponding to each analog-to-digital converter 100 according to a sampling time difference between sampling peaks of each digital sequence signal value; the sampling peak value is the maximum value of the sampling value corresponding to each sampling moment;
the phase adjuster 300, connected to the analog-to-digital converter 100 and the deviation detector 200, is configured to perform phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter 100, so as to output the operation clock corresponding to each analog-to-digital converter 100.
It should be noted that, the phase adjuster 300 is further configured to access the reference clock, so as to perform phase compensation on the reference clock at the phase compensation value corresponding to each analog-to-digital converter 100, so as to output the working clock corresponding to each analog-to-digital converter 100, thereby achieving phase consistency among the analog-to-digital converters 100.
Wherein, as shown in fig. 2, the training signal is sinusoidal.
The sine wave is a periodic signal with a single frequency and meeting a certain condition, so as to facilitate detection of the actual phase difference between the analog-to-digital converters 100.
By way of example and not limitation, as shown in fig. 3, the deviation detector 200 includes a plurality of sub-detectors 210, a calculation unit 220, and a plurality of registers 230;
each sub-detector 210 is connected to each analog-to-digital converter 100 in a one-to-one correspondence, and is configured to obtain a peak sampling time of a sampling peak of each digital sequence signal value.
The calculating unit 220 is connected to each sub-detector 210, and is configured to calculate each time difference according to each peak sampling time, and obtain a phase compensation value corresponding to each analog-to-digital converter 100 according to each time difference.
Each register 230 is connected to the calculation unit 220 and the phase adjuster 300 for recording each phase compensation value.
Wherein the calculation unit 220 may be a phase difference calculator.
The calculating unit 220 calculates the phase compensation value corresponding to each analog-to-digital converter 100 by comparing the peak sampling time of the two analog-to-digital converters and combining the sampling phase differences between the analog-to-digital converters 100 calculated by the reference clock to obtain the phase differences between the analog-to-digital converters 100.
The plurality of sub-detectors 210, the computing unit 220 and the plurality of registers 230 obtain the phase compensation values corresponding to the analog-to-digital converters 100 according to the peak sampling time of the sampling peak values of the digital sequence signal values, so that the accuracy of the phase compensation values is improved, and the phase consistency among the analog-to-digital converters 100 is further improved.
By way of example and not limitation, as shown in fig. 4, sub-detector 210 includes a buffer 211, a search circuit 212, and a timestamp register 213.
A buffer 211, coupled to the analog-to-digital converter 100, configured to record the digital sequence signal values;
a search circuit 212, connected to the buffer 211, configured to perform maximum value search on each sampling value in the digital sequence signal value, so as to obtain a sampling peak value, and take a sampling time corresponding to the sampling peak value as a peak value sampling time;
a time stamp register 213, coupled to the search circuit 212 and the calculation unit 220, is used to record the peak sample time.
The maximum value search is performed on each sampling value in the digital sequence signal value through the buffer 211, the search circuit 212 and the time stamp register 213, so as to obtain a sampling peak value and a corresponding peak sampling time, and accurately obtain the sampling peak value, thereby improving the phase consistency among the analog-to-digital converters 100.
By way of example and not limitation, as shown in fig. 5, phase adjuster 300 includes a plurality of sub-adjustment modules 310 that are connected one-to-one with a plurality of registers 230.
Each sub-adjustment module 310 is connected to each register 230 and configured to perform phase compensation on the reference clock according to each phase compensation value, so as to output an operation clock corresponding to each analog-to-digital converter 100.
The sub-adjustment module 310 is further configured to access the reference clock and phase compensate the reference clock according to the respective phase compensation values.
The reference clocks are phase-compensated according to the phase compensation values by the sub-adjustment modules 310, so that the anti-interference capability between the working clocks is improved.
By way of example and not limitation, as shown in fig. 6, the phase compensation value is an m-bit binary value, which corresponds one-to-one to the m sub-compensation signals; the sub-regulation module 310 includes m delay units 311 connected in series.
Each delay unit 311 is configured to access each sub-compensation signal and delay or forward the reference clock according to each sub-compensation signal.
In the specific implementation, two cases may be used.
In the first case, when the binary value corresponding to the sub-compensation signal is 1, the corresponding delay unit 311 delays the reference clock, and when the binary value corresponding to the sub-compensation signal is 0, the corresponding delay unit 311 forwards the reference clock without delaying.
In the second case, when the binary value corresponding to the sub-compensation signal is 0, the corresponding delay unit 311 delays the reference clock, and when the binary value corresponding to the sub-compensation signal is 1, the corresponding delay unit 311 forwards the reference clock without delaying.
The output ends of the register 230 can be connected to the control end of the delay unit 311 by delaying or forwarding the reference clock by each delay unit 311 according to each sub-compensation signal, namely: the output signal of the register 230 is directly used as the control signal of the delay unit 311, so that the output signal of the register 230 is not required to be converted, and a hardware circuit is simplified.
By way of example and not limitation, as shown in fig. 7, the delay unit 311 includes a buffer BUF and a selector MUX;
the input end of the buffer BUF and the first input end of the selector MUX are used as the reference clock input end of the delay unit 311, the output end of the buffer BUF is connected with the second input end of the selector MUX, the output end of the selector MUX is used as the reference clock output end of the delay unit 311, and the control end of the selector MUX is used as the sub compensation signal input end of the delay unit 311.
It will be appreciated that the principle of operation of the delay element 311 is two.
In the first case, when the binary value corresponding to the sub compensation signal is 1, the output terminal of the sub compensation signal control selector MUX is connected to the first input terminal of the selector MUX, and the delay unit 311 directly forwards the reference clock.
In the second case, when the binary value corresponding to the sub compensation signal is 0, the output terminal of the sub compensation signal control selector MUX is connected to the first input terminal of the selector MUX, and the delay unit 311 directly forwards the reference clock. When the binary value corresponding to the sub compensation signal is 1, the sub compensation signal controls the output end of the selector MUX to be communicated with the second input end of the selector MUX, and the reference clock is forwarded by the selector MUX after being delayed by the buffer BUF. The control terminal of the selector MUX inputs the sub compensation signal to control whether the reference clock delays.
The delay unit 311 has simple structure and reliable performance.
By way of example and not limitation, each analog-to-digital converter 100 is further configured to sample each analog input signal according to a corresponding operating clock of each analog-to-digital converter 100 to output each digital signal.
After the phase compensation setting of each analog-to-digital converter 100 is completed, the configuration may be configured to sample each analog input signal according to the working clock corresponding to each analog-to-digital converter 100, so as to improve the phase consistency of sampling each analog input signal.
By way of example and not limitation, as shown in fig. 8, the phase calibration circuit of the plurality of analog-to-digital converters further includes: the signal generator 400 is connected to the plurality of analog-to-digital converters 100 and configured to output training signals.
The training signal is output by the signal generator 400, which is simple and reliable.
By way of example and not limitation, as shown in fig. 9, the signal generator 400 is further configured to output a plurality of enable signals after outputting the training signal.
The phase calibration circuit further includes a plurality of tri-state gates 500.
Each tri-state gate 500 is connected with each analog-to-digital converter 100 in a one-to-one correspondence, and each tri-state gate 500 is also connected with the signal generator 400; each tri-state gate 500 is configured to access a respective analog input signal and forward the respective analog input signal in accordance with a respective enable signal.
It will be appreciated that each tri-state gate 500 is further configured to cease forwarding each analog input signal to each analog-to-digital converter 100 when no enable signal is received; at this time, each analog-to-digital converter 100 accesses the training signal, and samples the training signal according to the reference clock to obtain each digital sequence signal value; the digital sequence signal value comprises sampling values corresponding to all sampling moments; the deviation detector 200 obtains the phase compensation value corresponding to each analog-to-digital converter 100 according to the sampling time difference between the sampling peaks of each digital sequence signal value; the sampling peak value is the maximum value of the sampling value corresponding to each sampling moment; the phase adjuster 300 performs phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter 100, so as to output the working clock corresponding to each analog-to-digital converter 100. Then, the signal generator 400 outputs a plurality of enable signals; each tri-state gate 500 forwards each analog input signal according to each enable signal; each analog-to-digital converter 100 samples each analog input signal according to an operating clock corresponding to each analog-to-digital converter 100 to output each digital signal.
By the plurality of tri-state gates 500, the timing of the phase compensation process and the analog input signal sampling process is achieved, improving the ease of use of the phase calibration circuits of the plurality of analog-to-digital converters.
The embodiment of the invention also provides an analog-to-digital conversion chip which comprises the phase calibration circuit of the plurality of analog-to-digital converters.
In specific implementation, the analog-to-digital conversion chip can be widely applied to scenes with consistency requirements on phases of a plurality of analog-to-digital converters, including but not limited to scenes in which multiple microphones are required to be used for improving voice recognition in the field of audio application, scenes in which sound source positioning is performed through matrix operation analysis when a microphone array is used in the field of voice recognition application, and the like.
According to the embodiment of the invention, each analog-to-digital converter is connected with a training signal, and samples the training signal according to a reference clock to obtain each digital sequence signal value, wherein the digital sequence signal value comprises sampling values corresponding to each sampling moment; the deviation detector obtains phase compensation values corresponding to the analog-to-digital converters according to sampling time differences among sampling peaks of the digital sequence signal values, wherein the sampling peaks are maximum values of sampling values corresponding to sampling moments; the phase regulator performs phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter so as to output the working clock corresponding to each analog-to-digital converter, thereby counteracting the phase deviation among different analog-to-digital converters, reducing the phase error of actual sampling among each analog-to-digital converter and enabling the phases of the analog-to-digital converters to achieve high consistency.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A phase calibration circuit for a plurality of analog-to-digital converters, comprising a plurality of analog-to-digital converters, a deviation detector, and a phase adjuster:
each analog-to-digital converter is configured to be connected with a training signal, and samples the training signal according to a reference clock so as to obtain each digital sequence signal value; the digital sequence signal value comprises sampling values corresponding to sampling moments;
the deviation detector is connected with each analog-to-digital converter and is configured to obtain a phase compensation value corresponding to each analog-to-digital converter according to the sampling time difference between the sampling peak values of each digital sequence signal value; the sampling peak value is the maximum value of the sampling value corresponding to each sampling time;
the phase adjuster is connected with the analog-to-digital converter and the deviation detector and is configured to perform phase compensation on the reference clock according to the phase compensation value corresponding to each analog-to-digital converter so as to output the working clock corresponding to each analog-to-digital converter.
2. The phase calibration circuit of a plurality of analog-to-digital converters of claim 1, wherein said deviation detector comprises a plurality of sub-detectors, a computing unit, and a plurality of registers;
each sub-detector is connected with each analog-to-digital converter in a one-to-one correspondence manner and is configured to acquire the peak sampling time of the sampling peak value of each digital sequence signal value;
the calculating unit is connected with each sub-detector and is used for calculating each time difference according to each peak value sampling moment and obtaining a phase compensation value corresponding to each analog-digital converter according to each time difference;
and each register is connected with the computing unit and the phase regulator and is used for recording each phase compensation value.
3. The phase calibration circuit of a plurality of analog-to-digital converters of claim 2, wherein the sub-detector comprises:
the buffer is connected with the analog-to-digital converter and is configured to record the digital sequence signal value;
the searching circuit is connected with the buffer and is configured to search the maximum value of each sampling value in the digital sequence signal value to obtain the sampling peak value, and the sampling time corresponding to the sampling peak value is taken as the peak value sampling time;
and the time stamp register is connected with the search circuit and the calculation unit and is used for recording the peak sampling time.
4. The phase calibration circuit of a plurality of analog-to-digital converters of claim 2, wherein said phase adjuster comprises a plurality of sub-adjustment modules connected one-to-one with a plurality of said registers;
and each sub-regulation module is connected with each register and is configured to perform phase compensation on the reference clock according to each phase compensation value so as to output the working clock corresponding to each analog-to-digital converter.
5. The phase calibration circuit of a plurality of analog-to-digital converters as recited in claim 4, wherein said phase compensation value is an m-bit binary value, said m-bit binary value corresponding one-to-one to m sub-compensation signals; the sub-regulation module comprises m delay units connected in series;
each delay unit is configured to access each sub-compensation signal, and delay or forward the reference clock according to each sub-compensation signal.
6. The phase calibration circuit of a plurality of analog-to-digital converters of claim 5, wherein said delay unit comprises a buffer and a selector;
the input end of the buffer and the first input end of the selector are used as reference clock input ends of the delay units, the output end of the buffer is connected with the second input end of the selector, the output end of the selector is used as reference clock output ends of the delay units, and the control end of the selector is used as a sub compensation signal input end of the delay units.
7. The phase calibration circuit of a plurality of analog-to-digital converters of claim 1, wherein each of the analog-to-digital converters is further configured to sample each analog input signal according to a corresponding operating clock of each of the analog-to-digital converters to output each digital signal.
8. The phase calibration circuit of a plurality of analog-to-digital converters of claim 1, further comprising:
and the signal generator is connected with the analog-to-digital converters and is configured to output the training signals.
9. The phase calibration circuit of a plurality of analog-to-digital converters of claim 8, wherein the signal generator is further configured to output a plurality of enable signals after outputting the training signal;
the phase calibration circuit further includes a plurality of tri-state gates;
each tri-state gate is connected with each analog-to-digital converter in a one-to-one correspondence manner, and each tri-state gate is also connected with the signal generator;
each of the tri-state gates is configured to access a respective analog input signal and forward the respective analog input signal in accordance with the respective enable signal.
10. An analog to digital conversion chip comprising a plurality of analog to digital converter phase calibration circuits according to any one of claims 1 to 9.
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| CN202310212121.1A CN116232325A (en) | 2023-02-24 | 2023-02-24 | Phase calibration circuit and chip for multiple analog-to-digital converters |
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| CN202310212121.1A CN116232325A (en) | 2023-02-24 | 2023-02-24 | Phase calibration circuit and chip for multiple analog-to-digital converters |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117040535A (en) * | 2023-10-10 | 2023-11-10 | 浙江大学 | Phase indicating circuit, converter chip and multi-chip synchronization system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117040535A (en) * | 2023-10-10 | 2023-11-10 | 浙江大学 | Phase indicating circuit, converter chip and multi-chip synchronization system |
| CN117040535B (en) * | 2023-10-10 | 2023-12-22 | 浙江大学 | Phase indicating circuit, converter chip and multi-chip synchronization system |
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