JP4838060B2 - Analog waveform generator - Google Patents

Description

The present invention relates to an analog waveform generator that generates an arbitrary analog waveform signal, and more particularly, to an analog waveform generator that freely changes a waveform change on a time axis by a digital direct synthesizer (DDS).

  Conventionally, an analog waveform generator using a digital direct synthesizer (DDS) as shown in FIG. 7 is known.

  In FIG. 7, a control memory 102 known as a specification memory, a clock generation unit 104, an address counter 106, a waveform memory 108, a latch 110 using a flip-flop FF, an inverter 112, and an analog waveform generator on a circuit board 100 A DA converter 114 is provided.

  The control memory 102 and the waveform memory 108 are connected to an external CPU 118 via a bus 116. The CPU 118 stores the waveform data corresponding to the waveform ID indicating the type of waveform in the waveform memory 108, and stores the waveform data number N and the clock generator 104 that determines the maximum address of the address counter 106 corresponding to the waveform ID in the control memory 102. The clock cycle setting data for determining the clock cycle ΔT generated in the above is stored in advance.

  When generating an arbitrary analog waveform, the CPU 118 notifies the control memory 102 and the waveform memory 108 of the waveform ID and activates it. The control memory 102 that has received the activation instruction by designating the waveform ID from the CPU 118 outputs the clock cycle setting data corresponding to the waveform ID to the clock generation unit 104 to the clock generation unit 104, and generates a clock having a cycle determined by the clock cycle setting data. Generate and output from the reference clock.

Further, the control memory 102 outputs the maximum number of data N to the address counter 106, sets the maximum address A _N , inputs the clock from the clock generation unit 104 and integrates it, so that the clock is within the range of the maximum address A _N. Synchronously generate addresses.

  The waveform memory 108 generates a waveform data read mode corresponding to the waveform ID instructed by the CPU 118, and sequentially reads the waveform data corresponding to the address output from the address counter 106. The waveform data read from the waveform memory 108 is input to the latch 110, sampled and latched by a clock having the same phase as the operation clock of the address counter 106, and output to the DA converter as latch waveform data.

  The DA converter 114 receives a clock having a phase opposite to that of the operation clock of the address counter 106 inverted by the inverter 112, and converts the waveform data into an analog signal in synchronization with the reverse phase clock and outputs the analog signal.

  Here, the clock generation unit 104 is generally called a digital direct synthesizer (DDS).

  In an analog waveform generator equipped with such a digital direct synthesizer (DDS), the inclination on the time axis is required by changing the clock cycle generated by the clock generator 104 according to the clock cycle setting data. It is possible to generate a waveform that is freely changed according to the above.

FIG. 8 shows a case where a waveform linearly increasing with respect to a time change is generated, and FIG. 8A shows a case of a clock cycle ΔT. When this is changed to a double clock cycle 2ΔT, FIG. As in (B), the slope on the time axis can be halved.
JP-A-5-27978

  However, in such an analog waveform generator using a conventional digital direct synthesizer (DDS), the clock cycle cannot be changed without limitation, and the clock generator 104, the address counter 106, Since the waveform memory 108, the latch 110 using the flip-flop FF, the inverter 112, and the DA converter 114 have a synchronous circuit configuration, an inherent delay τd including a delay amount inherent in each circuit unit and a propagation delay between the circuit units. There is a problem that it cannot operate in the following clock cycle.

This intrinsic delay τd is a delay time obtained by adding a propagation delay time from the address counter 106 to the waveform memory 108 to the response delay time of the address counter 106, T1 as a response time of the waveform memory 108, and from the waveform memory 108 to the latch 110. If the propagation delay time of T is T3,
The intrinsic delay time τd is τd = T1 + T2 + T3
It becomes.

  FIG. 9 is a time chart of each part when the clock period ΔT is sufficiently longer than the intrinsic delay τd, FIG. 9A is the clock, FIG. 9B is the waveform memory address, and FIG. 9C is the waveform memory output. 9D is a latch input, and FIG. 9E is a DA converter input.

  The address counter 106 operates in synchronization with the rise of the clock time t1 of the clock output from the clock generation unit 104 in FIG. 9A, the address A1 in FIG. 9B is generated after the delay time T1, and the propagation time T2 9C, the waveform data D1 in FIG. 9C is read out, and is input to the latch 110 as shown in FIG. 9D after the propagation time T3, and the intrinsic delay time τd has elapsed at time t2. After that, it is latched at the rising edge of the clock at time t3, and the waveform data D1 is input to the DA converter 114 as shown in FIG.

  At the clock rising timing at time t3, the waveform data D1 read from the waveform memory 108 is fixed, and the correct waveform data D1 can be sampled and latched. It works fine with a slower clock period.

  FIG. 10 is a time chart of each part when the clock period ΔT is shorter and faster than the intrinsic delay τd. The address counter 106 operates in synchronization with the rising of the clock time t1 of the clock output from the clock generation unit 104 in FIG. 10A, the address A1 in FIG. 10B is generated after the delay time T1, and the propagation time T2 After reaching the waveform memory 108, the waveform data D1 in FIG. 10C is read out and input to the latch 110 as shown in FIG. 10D after the propagation time T3.

  However, since the clock cycle is short, the clock rises and latches the data D1 at time t2 while the data D1 read from the waveform memory 108 is propagated to the latch 110, but the undefined portion of the data is sampled. Since it latches, it cannot operate normally.

  In order to solve this problem, if the sampling operation of the latch 110 is performed in synchronization with the time t3 of the clock having the opposite phase to the operation clock of the address counter 106 delayed by 180 ° with respect to the clock phase of the time t1, the waveform is obtained. Sampling can be performed with the data fixed, and it operates normally. However, the sampling with the clock having the opposite phase has a problem that it cannot operate normally when the clock period becomes longer than the intrinsic delay time τd as shown in FIG.

An object of the present invention is to provide an analog waveform generation device that enables a waveform generation operation to be performed normally regardless of whether the clock cycle is shortened or lengthened with respect to the inherent delay time, and widens the generated waveform.

  The present invention provides an analog waveform generator having a digital direct synthesizer (DDS).

That is, the present invention
A clock generator for outputting a clock having a period corresponding to the clock period setting value based on the reference clock;
An address counter that generates an address by accumulating the clocks output from the clock generator in a range up to a set maximum address;
Waveform memory for storing the waveform data for the maximum number of addresses and reading the waveform data corresponding to the address generated by the address counter;
A DA converter that converts the waveform data read from the waveform memory into an analog signal in synchronization with the clock;
In an analog waveform generator composed of
The clock cycle setting value of the clock generator is compared with a predetermined determination value, and if the clock cycle setting value is larger than the determination value, a first determination signal is output, and if the clock setting cycle is less than the determination value, the second determination signal is output. A clock cycle determination unit that outputs
When the first determination signal is output from the clock cycle determination unit, the waveform data read from the waveform memory is sampled with a clock having the same phase as the operation clock of the address counter and output to the DA unit, and the second determination signal is A sample select unit that samples the waveform data read from the waveform memory with a clock having a phase opposite to the operation clock of the address counter and outputs the sampled data to the DA converter;
Is provided.

  Here, the judgment value set as the clock period judgment value is the sum of the response time of the address counter, the propagation delay time from the address counter to the waveform memory, the response time of the waveform memory, and the propagation delay time from the waveform memory to the sampling select section. The inherent delay time.

  The clock cycle setting value of the clock generation unit is the clock frequency, and the clock cycle determination unit compares the frequency of the reciprocal of the inherent delay time with the clock frequency as a determination value.

The sample selector part
A first latch that inputs a first clock having the same phase as the operation clock of the address counter, latches waveform data read from the waveform memory at the rising timing, and outputs the latched waveform data as in-phase sample data;
A second latch that inputs a second clock having a phase opposite to the operation clock of the address counter inverted by the inverter, latches the waveform data read from the waveform memory at the rising timing, and outputs the latched data as the anti-phase sample data; ,
In-phase sample data of the first latch, anti-phase sample data of the second latch, in-phase clock in phase with the operation clock of the address counter, and anti-phase clock in phase opposite to the operation clock of the address counter inverted by the inverter When the first determination signal is output from the clock cycle determination unit, the in-phase sample data and the anti-phase clock are selected and output to the DA conversion unit, and the second determination signal is output from the clock cycle determination unit In this case, a selector that selects the same phase clock as the antiphase sample data and outputs the same phase clock to the DA converter,
Is provided.

The analog waveform generator of the present invention further includes a control memory connected to an external CPU by a bus, and a waveform memory and a clock cycle determination unit are connected to the CPU bus.
The CPU stores the waveform data in the waveform memory corresponding to the waveform identifier, and stores the number of waveform data and the clock cycle setting value for determining the maximum address in the address counter,
When the CPU receives a request to generate an arbitrary analog waveform, it outputs the waveform identifier of the requested waveform to the waveform memory to generate the corresponding waveform data read state, and outputs the waveform identifier of the requested waveform to the control memory. The maximum address corresponding to the address counter is set, and the clock cycle setting value corresponding to the clock generation unit is set to start waveform generation.

  According to the present invention, it is determined whether the clock cycle is short or long with respect to the intrinsic delay time determined by the response time of the circuit units constituting the analog waveform generator and the propagation delay time between the circuit units. The phase of the clock that samples the waveform data with respect to the operation clock of the address counter can be switched to the same phase or the opposite phase to operate normally, and the clock is not limited by the inherent delay time of the analog waveform generator. Waveforms with a wide band can be generated by changing from low speed to high speed as necessary.

In addition, the clock cycle can be shortened to less than the intrinsic delay time, enabling reading at the limit speed of the waveform memory, and increasing the clock speed increases the number of waveform data that can be read in the same waveform generation time. Thus, the resolution of the waveform data is improved, and a finer arbitrary analog waveform can be generated with high accuracy.

  FIG. 1 is a circuit block diagram showing an embodiment of an analog waveform generator according to the present invention. 1, in this embodiment, each circuit unit of an analog waveform generator is mounted on a circuit board 10, and the analog waveform generator includes a control memory 12, a clock generator 14, an address counter 16, a waveform memory 18, and a sampling select. Unit 20, DA converter 22, and clock cycle determination unit 24.

  The control memory 12 and the waveform memory 18 on the circuit board 10 are connected to a bus 28 so that the CPU 26 can store data necessary for analog waveform shaping. The CPU 26 has CPU setting data 30 necessary for generating the analog waveform shown in FIG. 2 and stores it in the control memory 12 and the waveform memory 18 on the circuit boat 10 via the bus 28.

  The CPU setting data 30 includes a waveform ID, waveform data Di, number N of waveform data, and clock cycle setting data F. The CPU 26 stores the waveform data Di in the CPU setting data 30 in FIG. 2 in the waveform memory 18 together with the waveform ID. At the same time, the number N of waveform data of the CPU setting data 30 and the clock cycle setting data F are stored in the control memory 12.

A plurality of CPU setting data 30 in FIG. 2 are prepared according to the type of waveform to be generated, and stored on the circuit board side as necessary. Here, the waveform data Di is data obtained by dividing an analog waveform that changes on the time axis into N pieces of data, and each waveform data D1 to Dn is stored as a memory table at addresses A _{1 to} A _N where i = 1 to _N. This is stored in the waveform memory 18.

  Referring again to FIG. 1, the clock generator 14 generates a clock CLK1 having a clock period corresponding to the clock period setting data F set from the control memory 12 based on the reference clock CLK0. The clock CLK1 output from the clock generation unit 14 serves as an operation clock for the address counter 16 and serves as a sampling clock for the sampling select unit 20. The clock cycle setting data F set from the control memory 12 to the clock generator 14 is, for example, clock frequency data.

Address counter 16 is the waveform data number N set from the control memory 12 as the maximum address A _N, the maximum range of addresses A _N address Ai in clock count (accumulated) by the clock CLK1 from the clock generating unit 14, i.e. the address A _{1 to} A _N are generated.

  The waveform memory 18 selects the memory table of the waveform data Di stored from the CPU 26 according to the waveform ID designated by the CPU 26 at the start of waveform generation and sets the readout state, and subsequently the waveform corresponding to the address Ai output from the address counter 16. The data Di is read and output to the sampling select unit 20.

  The sampling select unit 20 samples the waveform Di read from the waveform memory 18 based on the clock CLK1 from the clock generator 14, outputs the sampled waveform data Di to the DA converter 22, and at the same time, the sampling select unit 20 Is converted to an analog signal at the timing of CLK2 output from the output.

  The clock cycle determination unit 24 combines the response time in each circuit unit of the address counter 16, the waveform memory 18, the sampling select unit 20, and the DA converter 22 mounted on the circuit board 10, and the propagation delay time between the circuits, and thus the inherent delay time. The determination value Fth corresponding to τd is set from the CPU 26, compared with the clock cycle setting data F set in the clock generator 14 from the control memory 12 during the generation operation of the analog waveform, and selected according to the comparison result. The signal Es is output to the sampling select unit 20 to cause the sampling select unit 20 to perform the next sampling select operation.

(1) When the clock cycle setting data F is larger than the determination value Fth, the waveform data Di read out from the waveform memory 18 at that time using the same phase sampling clock as the operation clock of the address counter 16 Is sampled.
(2) When the clock cycle setting data F is equal to or less than the determination value Fth, the waveform data Di output from the waveform memory 18 at that time is sampled by the antiphase sampling clock having the opposite phase to the operation clock of the address counter 16. .

  FIG. 3 is a circuit block diagram showing details of the clock cycle determination unit 24 of FIG. In FIG. 3, the clock cycle determination unit 24 is provided with a comparison circuit 32. The comparison circuit 32 inputs the clock cycle setting data F to the input terminal A, inputs the determination value Fth to the input terminal B, and the clock cycle setting data. If F is larger than the determination value Fth, a select signal Es (first determination signal) that is L level is output, and if the clock cycle setting data F is equal to or less than the determination value Fth, the select signal Es (second determination signal) that is H level. ) Is output.

  Here, the determination value Fth set in the clock cycle determination unit 24 is based on the inherent delay time τd that is the sum of the response time and propagation delay time of each circuit unit from the address counter 16 in FIG. It is decided.

That is, the propagation time T1 transmitted from the address counter to the address waveform memory 18, the response time T2 when the waveform memory 18 reads the waveform data, and the time until the waveform data propagates from the waveform memory 18 to the sampling select 20. Assuming T3, the intrinsic delay τd is τd = T1 + T2 + T3
Given in.

  The intrinsic delay time τd in the analog waveform generator of the circuit board 10 is calculated by using design data at the design stage, or is obtained by actual measurement in the assembled state of the circuit board 10, and the CPU 26 shown in FIG. Set as shown in the setting data 30.

For example, when the propagation delay time τd calculated or actually measured for this embodiment is τd = 20 ns, the CPU 26 sets a determination value Fth that is the reciprocal of the inherent delay time τd as the determination value Fth for the clock cycle determination unit 24. . That is, the determination value Fth is Fth = 1 / τd = 1/20 ns = 50 MHz.
The determination value Fth = 50 MHz is set in the clock cycle determination unit 24.

On the other hand, the clock cycle setting data F set from the CPU 26 to the clock generator 14 via the control memory 12 is the inverse of F = 1 / ΔT, where ΔT is the clock cycle to be set.
And is compared with the determination value Fth by the clock cycle determination unit 24.

  Of course, in this embodiment, the frequency is used as the clock cycle setting data and the determination value, but the cycle may be used.

  FIG. 4 is a circuit block diagram showing details of the sampling select section 20 of FIG. In FIG. 4, the sampling select unit 20 includes a first latch 34 using an FF, a second latch 35 using a flip-flop FF, a 4-input 2-output selector 36, and an inverter 38.

  The first latch 34 receives the waveform data Di read from the waveform memory 18 and the same clock CLK 1 as the operation clock of the address counter 16 output from the clock generator 14. Here, the clock CLK1 having the same phase as the operation clock of the address counter 16 is referred to as an in-phase sample clock.

  The first latch 34 samples and latches the waveform data Di at the rising timing of the in-phase sample clock CLK1, and outputs it to the C-side input terminal of the selector 36. The sample data output from the first latch 34 to the selector 36 is referred to as in-phase sample data Ds.

The second latch 35 receives the waveform data Di read from the waveform memory 18 and receives the inverted clock CLK1 inverted by the inverter 38. Here, the inverted clock CLK1 is shown with an underline. The second latch 35 samples and latches the waveform data Di at the rising timing of the inverted clock CLK1 from the inverter 38, and outputs the sample data Ds to the D side of the selector 36.

The inverted clock CLK1 inverted by the inverter 38 is called an antiphase sample clock because its rising edge is in an opposite phase that is 180 degrees out of phase with the operation clock of the address counter 16. The waveform data sampled by the antiphase sample clock CLK1 output from the second latch 35 is underlined to be antiphase sample data Ds .

Further, the reverse phase sample clock CLK1 inverted by the inverter 38 is input to the C side of the selector 36, and the in-phase sample clock CLK1 is input to the D side.

The selector 36 selects the in-phase sample data Ds on the C side and the anti-phase sample clock CLK1 when the select signal Es output from the clock cycle determination unit 24 shown in FIG. 3 is L level (when the first determination signal is output). The waveform data Di and the clock CLK2 are output to the DA converter 22.

On the other hand, when the select signal Es is at the H level (when the second determination signal is output), the D-phase opposite phase sample data Ds and the same phase sample clock CLK1 are selected, and the DA converter at the next stage is selected as the waveform data Di and the clock CLK2. 22 to output.

  Next, the operation of generating an analog waveform in this embodiment of FIG. 1 will be described. FIG. 5 is a time chart of the waveform generation operation when the clock cycle setting data F set in the clock generation unit 14 is larger than the determination value Fth set in the clock cycle determination unit 24, that is, when the clock cycle Δd is longer than the intrinsic delay time τd. It is.

  5A is a clock CLK1 output from the clock generator 14, FIG. 5B is a waveform memory address output from the address counter 16, and FIG. 5C is a waveform read from the waveform memory 16. 5D is a latch input of waveform data to the first latch 34 and the second latch 35 of FIG. 4 provided in the sampling select unit 20, and FIG. 5E is a sampled waveform to the DA converter 22. The data DA value input is shown.

  Prior to the generation of the analog signal waveform, the CPU 26 uses the bus 28 based on the waveform data Di, the number N of waveform data, and the clock cycle setting data F corresponding to the waveform ID as shown in the CPU setting data 30 of FIG. The waveform data Di is stored in the waveform memory 18 using the waveform ID as an identifier, and at the same time, the number N of waveform data and the clock cycle setting data F are stored in the control memory 12.

  Further, a determination value Fth based on the inherent delay time τd in the analog waveform generation device of the circuit board 10 obtained from the design data or obtained by actual measurement is stored in the clock cycle determination unit 24.

  When the CPU 26 receives a waveform generation request designating an arbitrary waveform ID in a state where necessary data is stored in the circuit board 10, the requested waveform ID is notified to the control memory 12 and the waveform memory 18, and the waveform is Start generating operation.

  The control memory 12 that has received the generation request by designating the waveform ID from the CPU 26 sets the clock cycle setting data F corresponding to the waveform ID already stored in the clock generator 14 and inputs it to the clock cycle determiner 24 at the same time. .

Further, the number N of waveform data is output to the address counter 16 to set the maximum address A _N. On the other hand, in the waveform memory 18, upon receipt of the activation request designating the waveform ID from the CPU 26, a readable state of the waveform data Di corresponding to the designated waveform ID is created.

  The clock cycle determination unit 24 compares the clock cycle setting data F output from the control memory 12 with the determination value Fth set in the CPU 26, and when the clock cycle setting data F is larger than the determination value Fth, that is, the clock cycle ΔT. Is longer than the intrinsic delay time τd, the L selection signal Es (first determination signal) is output to the sampling selection unit 20.

Upon receipt of the L level select signal Es, the sampling selector 20 receives the in-phase sample data Ds from the first latch 34 for the C side of the selector 36 and the inverted phase inverted by the inverter 38, as shown in FIG. The selected state of the sample clock CLK1 is established.

  When the clock cycle setting data F is larger than the determination value Fth, that is, when the clock cycle ΔT is longer than the intrinsic delay time τd, the operation shown in the time chart of FIG. 5 is performed.

  First, the rising timing of the time t1 in the clock CLK1 in FIG. 5A becomes the address counter operation timing 40 of the address counter 16, and the same timing delayed by one cycle becomes the sampling timing in the sampling select unit 20, and both are clocks of the same phase. It becomes the timing by.

At time t1, the address counter 16 operates in synchronization with the rise of the clock CLK1, and after the response time T1, the waveform memory address A1 shown in FIG. 5B is output. The waveform memory address A ₁ obtains the propagation delay time T2 and is transmitted to the waveform memory 18, and the waveform data D1 corresponding to the address A ₁ is output from the waveform memory 18 as shown in FIG.

  The waveform data D1 output from the waveform memory 18 is input to the sampling select unit 20 after the propagation delay time T3. That is, the signal is input to the C-side latch 34 in the selected state by the selector 36 in the sampling select unit 20 of FIG.

  The clock CLK1 rises to the H level at the time t3 after the clock period ΔT from the time t1, and this becomes the sample timing, and the waveform data D1 input at that time is sampled as in-phase sample data by the first latch 34 of FIG. The waveform data D1 is output to the DA converter 22 in the next stage via the selector 36 in the C-side selector state.

At the same time, the reverse phase sample clock CLK1 inverted by the inverter 38 input to the C side is output from the selector 36 to the DA converter 22 as the clock CLK2, and is input to the DA converter 22 as shown in FIG. Are converted into analog data and output over a clock cycle.

  On the other hand, in the clock cycle determination unit 24 of FIG. 1, when the clock cycle setting data F set in the clock generation unit 14 is equal to or less than the determination value Fth, that is, when the clock cycle ΔT is shorter than the intrinsic delay time τd, The clock cycle determination unit 24 outputs a select signal Es (second determination signal) that becomes H level to the sampling select unit 20.

Upon receiving the select signal Es at H level, the sampling select section 20 in FIG. 4 selects the in-phase sample clock CLK1 and the anti-phase sample data Ds from the second latch 35 input to the D side by the selector 36. .

  The operation when the clock period ΔT is shorter than the intrinsic delay time τd is as shown in the time chart of FIG. In the clock CLK1 of FIG. 6A, that is, the operation clock of the address counter 16, for example, the rising edge at the time t1 becomes the address counter operation timing 40.

On the other hand, the sampling timing by the antiphase sample clock CLK1 inverted by the inverter 38 for the D-side latch 35 selected by the selector 36 of FIG. 4 in the sampling select unit 20 is relative to the address counter operation timing 40 at time t1. The sample timing 42 has an antiphase that is 180 degrees out of phase.

Therefore after the response time T1 address counter 16 at the rising edge of the clock CLK1 is operated at time t1 in FIG. 6 (A), the output waveform memory address A ₁ shown in FIG. 6 (B) in the waveform memory 18, waveform memory 18 From FIG. 6C, the waveform data D1 is read through the propagation delay time T2, and then the waveform data from the waveform memory 18 through the propagation delay time T3 to the sampling select unit 20 as shown in FIG. 6D. Di inputs.

  However, since the clock period ΔT is shorter than the intrinsic delay time τd, if the address counter operation timing 40 and the sample timing 42 are in phase as shown in FIG. 5, the clock is in an undefined state during the propagation delay time T3. When CLK1 rises, waveform data is sampled. With this, undefined data is sampled, so waveform output cannot be performed normally.

On the other hand, in the present embodiment, the waveform data by the second latch 35 using the antiphase sample clock CLK1 of the antiphase that is 180 degrees out of phase with the address counter operation timing 40 of the address counter 16 as the sample timing 42. Sampling at the time t3 when the clock period ΔT has elapsed, the data input to the sampling select unit 20 at this point is in a state that has been determined past the indefinite state, and the correct waveform data Di is sampled. As in 6 (E), the signal can be input to the DA converter 22 and converted into an analog signal.

  In the above embodiment, the analog waveform device configured as a mounting circuit on the circuit board 10 is taken as an example. However, the circuit board 10 may be configured as a single IC instead of being mounted. In addition to mounting the IC on the circuit board 10 and configuring the circuit, the control memory 12, the clock generation unit 14, the address counter 16, the waveform memory 18, the sampling selection unit 20, and the clock cycle determination unit 24 are controlled by the program of the CPU 26. You may comprise the analog waveform generator which performs a control process and outputs a process result from DA conversion port which is an output port of CPU.

  As the waveform data stored in the waveform memory 18, in addition to the waveform data linearly changing with respect to the time axis as shown in FIG. 8, a periodic waveform that repeatedly changes at a constant cycle such as a sine waveform, etc. The waveform data necessary for an appropriate analog waveform may be prepared and stored as necessary. Of course, in the case of periodic waveform data, waveform data for a certain period is stored in the waveform memory 18 and is repeatedly generated.

The present invention is not limited to the above-described embodiment, includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above-described embodiment. The features of the present invention are summarized here. And enumerate as follows.

(Appendix 1)
A clock generator for generating a clock having a period corresponding to the clock period setting value based on the reference clock;
An address counter that generates an address by accumulating the clocks output from the clock generator in a range up to a set maximum address;
Waveform memory for storing the waveform data for the maximum number of addresses and reading out waveform data corresponding to the address generated by the address counter;
A DA converter that converts the waveform data read from the waveform memory into an analog signal in synchronization with the clock;
In an analog waveform generator composed of
The clock cycle setting value set in the clock generator is compared with a predetermined determination value, and if the clock cycle setting value is larger than the determination value, a first determination signal is output, and the clock setting cycle is the determination value. A clock cycle determination unit that outputs a second determination signal in the following cases;
When the first determination signal is output from the clock cycle determination unit, the waveform data read from the waveform memory is sampled with a clock having the same phase as the operation clock of the address counter and output to the DA conversion unit, When the second determination signal is output, a sampling select unit that samples the waveform data read from the waveform memory with a clock having a phase opposite to that of the operation clock of the address counter, and outputs the sampled data to the DA conversion unit;
An analog waveform generator characterized by comprising: (1)

(Appendix 2)
In the analog waveform generation device according to attachment 1, the determination value of the clock cycle determination unit includes a response time of the address counter, an address propagation delay time from the address counter to the waveform memory, a response time of the waveform memory, and An analog waveform generating apparatus characterized in that the inherent delay time is a sum of propagation delay times from the waveform memory to the sampling select section. (2)

(Appendix 3)
In the analog waveform generator according to appendix 1, the clock cycle setting value of the clock generator is a clock frequency, and the clock cycle determination unit uses the reciprocal frequency of the inherent delay time as a determination value as the clock frequency. An analog waveform generator characterized by comparing.

(Appendix 4)
In the analog waveform generator according to appendix 1, the sampling select unit includes:
A first latch that inputs a first clock having the same phase as the operation clock of the address counter, latches waveform data read from the waveform memory at a rising timing, and outputs the latched waveform data as in-phase sample data;
A second latch that inputs a second clock having a phase opposite to the operation clock of the address counter inverted by the inverter, latches the waveform data read from the waveform memory at the rising timing, and outputs the latched data as the anti-phase sample data; ,
In-phase sample data of the first latch, anti-phase sample data of the second latch, in-phase clock having the same phase as the operation clock of the address counter, and anti-phase of the operation clock of the address counter inverted by the inverter When the first determination signal is output from the clock cycle determination unit, the in-phase sample data and the reverse phase clock are selected and output to the DA conversion unit, and the clock cycle determination unit When the second determination signal is output from the selector that selects the opposite phase sample data and the same phase clock and outputs to the DA converter,
An analog waveform generator characterized by comprising: (3)

(Appendix 5)
The analog waveform generator according to appendix 1, further comprising a control memory connected to an external CPU by a bus, the waveform memory and a clock cycle determining unit being connected to the bus of the CPU,
The CPU stores waveform data in the waveform memory corresponding to the waveform identifier and stores the number of waveform data and a clock cycle setting value for determining the maximum address in the address counter,
When the CPU receives a request for generating an arbitrary analog waveform, it outputs the waveform identifier of the requested waveform to the waveform memory to generate a read state of the corresponding waveform data, and controls the waveform identifier of the requested waveform. An analog waveform generating apparatus characterized in that the waveform generation is started by setting a maximum address corresponding to the address counter by outputting to a memory and setting a clock cycle setting value corresponding to the clock generator.

1 is a circuit block diagram showing an embodiment of an analog waveform generator according to the present invention. Explanatory drawing of data structure set from CPU Circuit block diagram of clock cycle determination unit in the present embodiment Circuit block diagram showing details of sampling select section in this embodiment Flow chart of waveform generation operation when clock cycle is longer than intrinsic delay time Flow chart of waveform generation operation when clock cycle is shorter than intrinsic delay time Circuit block diagram of conventional analog waveform generator Generated waveform time chart showing the slope of the waveform on the time axis when the clock period is changed Flow chart of normal operation of the conventional device when the clock cycle is longer than the intrinsic delay time Flow chart of abnormal operation of conventional device when clock cycle is shorter than intrinsic delay time

Explanation of symbols

10: Circuit board 12: Control memory 14: Clock generation unit 16: Address counter 18: Waveform memory 20: Sampling selection unit 22: DA converter 24: Clock cycle determination unit 26: CPU
28: Bus 30: CPU setting data 32: Comparison circuit 34: First latch 35: Second latch 36: Selector 38: Inverter 40: Address counter operation timing 42: Sample timing

Claims (3)

A clock generator for generating a clock having a period corresponding to the clock period setting value based on the reference clock;
An address counter that generates an address by accumulating the clocks output from the clock generator in a range up to a set maximum address;
Waveform memory for storing the waveform data for the maximum number of addresses and reading out waveform data corresponding to the address generated by the address counter;
A DA converter that converts the waveform data read from the waveform memory into an analog signal in synchronization with the clock;
In an analog waveform generator composed of
The clock cycle setting value set in the clock generator is compared with a predetermined determination value, and if the clock cycle setting value is larger than the determination value, a first determination signal is output, and the clock setting cycle is the determination value. A clock cycle determination unit that outputs a second determination signal in the following cases;
When the first determination signal is output from the clock cycle determination unit, the waveform data read from the waveform memory is sampled with a clock having the same phase as the operation clock of the address counter and output to the DA conversion unit, When the second determination signal is output, a sampling select unit that samples the waveform data read from the waveform memory with a clock having a phase opposite to that of the operation clock of the address counter, and outputs the sampled data to the DA conversion unit;
An analog waveform generator characterized by comprising:
2. The analog waveform generation device according to claim 1, wherein the determination value of the clock cycle determination unit includes a response time of the address counter, an address propagation delay time from the address counter to the waveform memory, and a response time of the waveform memory. And an analog waveform generator characterized by a total delay time of propagation delay times from the waveform memory to the sampling select section.
The analog waveform generator according to claim 1, wherein the sampling select unit includes:
A first latch that inputs a first clock having the same phase as the operation clock of the address counter, latches waveform data read from the waveform memory at a rising timing, and outputs the latched waveform data as in-phase sample data;
A second latch that inputs a second clock having a phase opposite to the operation clock of the address counter inverted by the inverter, latches the waveform data read from the waveform memory at the rising timing, and outputs the latched data as the anti-phase sample data; ,
In-phase sample data of the first latch, anti-phase sample data of the second latch, in-phase clock having the same phase as the operation clock of the address counter, and anti-phase of the operation clock of the address counter inverted by the inverter When the first determination signal is output from the clock cycle determination unit, the in-phase sample data and the reverse phase clock are selected and output to the DA conversion unit, and the clock cycle determination unit When the second determination signal is output from the selector that selects the opposite phase sample data and the same phase clock and outputs to the DA converter,
An analog waveform generator characterized by comprising:

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