JP5533424B2 - Integrated circuit device and skew adjustment method for integrated circuit device - Google Patents

Description

  The present invention relates to a skew adjustment circuit and a skew adjustment method.

  An integrated circuit device (LSI) has an output buffer that outputs a plurality of signals to an external LSI or to another internal macro. For example, a signal line of a data bus of a plurality of bits is latched by a plurality of latch circuits such as flip-flops in response to a reference clock, and an output of the latch circuit is output via a corresponding output buffer. When a plurality of signals change from the L level to the H level at the same time, a large current flows through the power supply wirings of the plurality of output buffers to generate power supply noise. Conversely, when a plurality of signals simultaneously change from the H level to the L level, a large current flows through the ground wiring of the plurality of output buffers, thereby generating ground noise. Such noise is called simultaneous switching noise (SSN), and becomes particularly large when a plurality of output buffers having a large driving capability are simultaneously switched in the same direction.

  Patent Documents 1, 2, and 3 describe methods for suppressing such simultaneous switching noise. In either case, a predetermined delay is added to a plurality of signals to cause skew in the plurality of signals to suppress simultaneous switching.

JP 2007-129601 A JP 2004-334271 A JP-A-9-181593

  However, since the output timing of a plurality of signals varies depending on various factors, there are cases where noise due to simultaneous switching cannot be suppressed appropriately only by adding a predetermined delay.

  For example, since the operation speed in the LSI differs depending on the operating environment of the LSI and the timing of the internal signal differs, there may be a case where simultaneous switching noise cannot be appropriately reduced by a method in which a fixed delay circuit is inserted into the output signal. In addition, AC specifications in an external LSI that receives an LSI output signal, such as input setup time and hold time, differ depending on the LSI. However, in the method of inserting a fixed delay in an output signal, the AC spec. You may not be satisfied.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a skew adjustment circuit that can provide a plurality of signals with a skew adapted to the operating state of an LSI.

A first side of the skew adjustment circuit is provided in the integrated circuit device, and includes a plurality of signal lines that respectively propagate a plurality of signals,
A plurality of buffer circuits to which a plurality of signals propagating through the plurality of signal lines are respectively input;
A plurality of delay circuits respectively provided in a preceding stage of the plurality of buffer circuits;
A monitoring circuit for monitoring signal changes of the plurality of signal lines;
A delay adjustment circuit that determines a delay amount of the plurality of delay circuits based on a monitoring result output of the monitoring circuit and sets the delay amounts in the plurality of delay circuits;
The monitoring circuit detects, as the monitoring result, the number of signal changes, which is the number of signal lines in which a signal change has occurred within a monitoring period,
The delay adjustment circuit determines the delay amount based on the number of signal changes.

  According to the first aspect, since the appropriate skew is generated by delaying the signal of each signal line in accordance with the number of signal changes generated in a plurality of signal lines, simultaneous switching noise can be appropriately suppressed.

It is a figure which shows the integrated circuit device which has the skew adjustment circuit in this Embodiment. FIG. 2 is a signal waveform diagram illustrating an outline of skew adjustment by the skew adjustment circuit 10 of FIG. 1. It is a figure which shows the skew adjustment circuit in 1st Embodiment. It is a figure which shows a simultaneous change monitoring circuit. 2 is a diagram illustrating a delay adjustment circuit 30. FIG. 6 is a time chart of operations of the simultaneous change monitoring circuit 20 and a delay adjustment circuit 30 described later with reference to FIG. It is a figure which shows a delay circuit and the relationship between the tap value and delay amount. It is a figure which shows the format of delay amount ROM. It is a figure which shows the specific example of delay amount ROM. It is a figure which shows the delay amount and skew which are set to a delay circuit. It is a figure explaining the allowable delay amount. It is a figure which shows the modification of the skew adjustment circuit in 1st Embodiment. 2 is a diagram illustrating an example of an operation state monitoring circuit 50. FIG. It is a figure which shows the specific example of delay amount ROM. It is a figure which shows the 2nd modification of the skew adjustment circuit in 1st Embodiment. It is a figure which shows the delay adjustment circuit in the 2nd modification. It is a figure of the 3rd modification of the skew adjustment circuit in 1st Embodiment. It is a figure of the skew adjustment circuit in 2nd Embodiment. 6 is a diagram showing a Rise / Fall change monitoring circuit 60. FIG. 4 is a diagram illustrating a format of a delay amount ROM 40. FIG. 5 is a diagram showing a specific example of a delay amount ROM 40. FIG. It is a figure which shows the 1st modification of the skew adjustment circuit in 2nd Embodiment. 5 is a diagram showing a specific example of a delay amount ROM 40. FIG. It is a figure which shows the 2nd modification of the skew adjustment circuit in 2nd Embodiment. It is a figure which shows the 3rd modification of the skew adjustment circuit in 2nd Embodiment.

  FIG. 1 is a diagram illustrating an integrated circuit device having a skew adjustment circuit according to the present embodiment. FIG. 1 shows a circuit of an output portion of the LSI. In FIG. 1, a plurality of data signals Data # 1 to Data # N are latched by a plurality of flip-flops FF # 1 to FF # N in response to a clock CLK. The plurality of latched data signals are output as output data signals O_Data # 1 to O_Data # N to other external LSIs or to other internal macros via the output buffers OB_1 to OB_N.

  Data signals Data # 1 to Data # N propagate through signal wirings between the plurality of flip-flops and the output buffer, respectively. When the data signal is input to the output buffer, the output buffer drives the output terminal in response to the change from the L level to the H level (Rise) or the change from the H level to the L level (Fall). . At that time, a drive current flows through the power supply VDD and the ground VSS connected to the output buffers OB_1 to OB_N.

  When the timings of changes of the data signals supplied to the output buffers OB_1 to OB_N match, a plurality of output buffers perform the driving operation simultaneously. In that case, if all the changes in the data signal are the same or the changes in many data signals are the same, a large current flows through the power supply VDD and the ground VSS due to the simultaneous drive operation of the output buffer, generating power supply noise or ground noise.

  Therefore, in FIG. 1, the skew adjustment circuit 10 monitors the number and timing of changes in the data signal propagated through each signal wiring, and determines the delay amount of each signal wiring according to the detected number and timing of signal changes. To do. Then, the delay amount of the delay circuits DL_1 to DL_N provided immediately before the output buffers OB_1 to OB_N is set to the determined delay amount, and the timings of the driving operations in the plurality of output buffers OB_1 to OB_N do not match as much as possible. Like that.

  Further, the skew adjustment circuit 10 monitors changes in the operation state of the LSI (process condition, voltage condition, temperature condition), and determines an optimum delay amount according to the operation state. In addition, as the delay amount, a delay amount suitable for the AC specifications of other LSIs to which the output data signals O_Data # 1 to O_Data # N are input, for example, the setup time is selected. Other macros that receive the output data signals O_Data # 1 to O_Data # N can be similarly adapted to the AC specifications.

  FIG. 2 is a signal waveform diagram showing an outline of skew adjustment by the skew adjustment circuit 10 of FIG. In FIG. 1, in response to a clock CLK, a plurality of flip-flops FF # 1 to FF # N latch data signals Data # 1 to Data # N. In the example of FIG. 2, the latch timings coincide. The skew adjustment circuit monitors changes in the outputs of the flip-flops FF # 1 to FF # N, and if signal changes are detected in all or many signal wirings as shown in FIG. The amount Delay # 1 to Delay # N is appropriately controlled to generate an appropriate skew in the data signals FF # 1_Q to FF # N_Q input to the output buffers OB_1 to OB_N.

  In this way, the skew adjustment circuit 10 adjusts the delay amount of the delay circuit provided in the signal wiring, thereby shifting the timing of the propagated data signal to have an appropriate skew. As a result, the simultaneous switching noise due to the simultaneous switching operation by the output buffer is suppressed.

[First Embodiment]
FIG. 3 is a diagram illustrating the skew adjustment circuit according to the first embodiment. FIG. 3 shows the configuration of the output section of the LSI. The final stage flip-flop 1 that latches eight data signals Data # 0 to Data # 7 in response to the reference clock Ref_CLK, and the output of the flip-flop 1 8 signal lines SL_0 to SL_7 connected to the terminals, and output buffers OB_0 to OB_7 for inputting the signals SG_0 to SG_7 propagating through the signal lines and outputting them to other external LSIs or to other internal macros Have. In the figure, output buffers OB_0 to OB7 also show input buffers for inputting signals in addition to buffer circuits for outputting signals. That is, OB_0 to OB_7 shown in the figure are input / output buffers.

  In the skew adjustment circuit 10, delay circuits DL_0 to DL_7 are provided on the eight signal lines SL_0 to SL_7 immediately before the output buffers OB_0 to OB_7. As described above, by adjusting the delay amount of this delay circuit, an appropriate skew is generated in the signals SG_0 to SG_7 propagating through the signal lines SL_0 to SL_7. This suppresses the generation of noise due to simultaneous switching by shifting the switching timing in the output buffer.

  The skew adjustment circuit 10 determines that the level change (Rise) from the L level to the H level and the level change (Fall) from the H level to the L level of the signals SG_0 to SG_7 propagating through the eight signal lines are within a predetermined monitoring period. It has a monitoring circuit 20 for monitoring whether or not it has occurred inside. Since this monitoring period is a period that is short enough to be regarded as a simultaneous change of signals, it is considered that a signal line in which a change in signal level has occurred within this monitoring period has changed simultaneously. Thus, if there are a plurality of signal lines in which the signal level changes within a short period that can be regarded as simultaneous changes, it may cause power supply noise and ground noise due to simultaneous switching in the output buffer.

  The skew adjustment circuit 10 further sets a delay amount to be set in the delay circuits DL_0 to DL_7 according to the number of signal lines (number of signal changes) whose signal level has changed in a short period of time detected by the simultaneous change monitoring circuit 20. It has a delay adjustment circuit 30 for determining. The delay adjustment circuit 30 determines a delay amount by referring to a delay amount memory (ROM) 40 that stores a delay amount that generates an appropriate skew between signals corresponding to the number of signal changes, and delays the delay amount. Set to circuits DL_0 to DL_7.

  FIG. 4 is a diagram showing a simultaneous change monitoring circuit. The simultaneous change circuit 20 includes signal change detection circuits 201_0 to 201_7 that detect changes in signals of the eight signal lines SL_0 to SL_7, respectively. This signal change detection circuit 201_0 calculates the exclusive OR of the register SR # 0 that latches the signals on the signal lines SL_0 to SL_7 in response to the reference clock Ref_CLK, and the signal on the signal line and the output of the register SR # 0 An XOR circuit. When the signal on the signal line changes from the L level to the H level, the XOR circuit generates a detection pulse having a pulse width from the change of the signal to the reference clock in response to the reference clock Ref_CLK immediately after that. Similarly, when the signal on the signal line changes from H level to L level, the XOR circuit generates a detection pulse.

  The control enable signal Cnt_EN is generated by a circuit (not shown). However, when a stable system clock is input and a stable internal reference clock Ref_CLK is generated in the system initialization operation of the skew adjustment circuit, the control enable signal Cnt_EN Becomes H level. In response to the control enable signal Cnt_EN = H, the skew adjustment operation of the skew adjustment circuit 10 starts. The timing generation counter 203 repeats the operation of incrementing the 4-bit count value Count in synchronization with the reference clock in response to the control enable signal Cnt_EN = H. The count value Count of the output of the timing generation counter 203 controls the operation timing in the skew adjustment circuit 10 as will be described later.

  The control enable signal Cnt_EN can be configured to be controlled from an upper system to an enable state (H level) and a disable state (L level). With this configuration, the skew adjustment circuit can be stopped after the skew adjustment circuit is automatically operated and the skew adjustment is performed after the initialization operation such as when the power is turned on. In addition, when the temperature of the LSI rises, the control enable signal Cnt_EN can be controlled to be in an enable state, skew adjustment can be performed, and then the disable state can be controlled. By controlling the operation and stop of the skew adjustment circuit in this way, it is possible to avoid generation of useless current consumption.

  FIG. 6 is a time chart of operations of the simultaneous change monitoring circuit 20 and a delay adjustment circuit 30 (FIG. 5) described later. The configuration and operation of the simultaneous change monitoring circuit will be described with reference to this time chart.

  The monitoring result holding registers Moni_R # 0 to Moni_R # 7 latch the signal change detection pulse of the XOR circuit when the count value Count output from the timing generation counter 203 becomes zero. Further, the selector 205 sequentially selects the monitoring result holding registers Moni_R # 0 to Moni_R # 7 in accordance with the timing when the count value Count becomes 1 to 8, and performs parallel / serial conversion. The selector output change enable signal chg_en = 1 is counted, and the counted number of changes is output to the delay adjustment circuit 30. The simultaneous change number counter 207 is reset when the count value Count = 0, and then starts counting, and counts the change enable signal chg_en = 1 from the selector in response to the reference clock Ref_CLK. In FIG. 6, the count value of the change number counter is “5” at the timing of the timing count value Count = 8.

  That is, in the simultaneous change monitoring circuit 20, the signal change detection circuits 201_0 to 201_7 detect signal changes that occur simultaneously within the monitoring period, which is one cycle of the reference clock Ref_CLK, and detect it at the timing of the count value Count = 0. The signal change is latched in the monitoring result holding registers Moni_R # 0 to Moni_R # 7, and the counter 207 counts the signal change at the next count value Count = 1 to 8. Signal changes to be detected are both L level to H level changes and H level to L level changes. Therefore, the simultaneous change monitoring circuit 20 detects the simultaneous change of signals at intervals of once every 16 cycles of the reference clock Ref_CLK, and outputs the number of signal changes.

  FIG. 5 is a diagram illustrating the delay adjustment circuit 30. The delay adjustment circuit 30 shown in FIG. 5 includes a change number holding register 301 that latches the number of signal changes detected by the simultaneous change monitoring circuit 20 with a count value Count = 10, and a change number holding register 301 with a count value Count = 15. And a setting state holding register 303 that latches the current simultaneous change number held by the old simultaneous change number as the old simultaneous change number. Further, the delay adjustment circuit 30 includes a change number comparison circuit 305, which includes the old simultaneous change number of the setting state holding register 303 and the current simultaneous change number of the change number holding register 301 at a count value Count = 11. And a setting tap information register 309 that latches setting tap information corresponding to the delay amount R-data read from the delay ROM 40 with the count value Count = 14. Further, the tap setting register 311 that latches the tap information of the setting tap information register 309 with the count value Count = 15 is provided, and the tap values set in the tap setting register 311 are set in the delay circuits DL_0 to DL_7. A reference clock Ref_CLK is supplied to each of the registers 301, 303, 309 and the comparator 307, and is latched or compared in synchronization with the rising edge of the clock. By the inverter 310, the tap setting register 311 latches the setting value of the setting tap information register 309 in synchronization with the falling edge of the reference clock Ref_CLK.

  In another embodiment to be described later, the delay adjustment circuit 30 in FIG. 5 inputs the number of changes from the rise / fall change monitoring circuit 60 and the comparison result, and performs a predetermined delay adjustment based on the comparison result. In the present embodiment, the comparison result is not used.

  The operation of the delay adjustment circuit 30 of FIG. 5 is as follows, as shown in the time chart of FIG. The simultaneous change monitoring circuit 20 in FIG. 4 detects the number of simultaneous changes with the count value Count = 8, and outputs it to the delay adjustment circuit 30. In FIG. 6, the number of simultaneous changes is “5”. Then, when the count value is Count = 10, the simultaneous change number is stored in the change number holding register 301 as the current simultaneous change number. Then, when the count value Count = 11, the change number comparator 307 calculates the old simultaneous change number (“2” in FIG. 6) and the current simultaneous change number (“5” in FIG. 6) held in the setting state holding register 303. Compare. If the comparison results are not equal (comparison ≠), the number of simultaneous changes has changed, so the change number comparator 307 outputs a read command Read to the delay amount ROM 40. The address of this read operation is the data of the current simultaneous change number (“5” in FIG. 6). If the comparison results are equal, the ROM is not read and the tap value of the tap setting register 311 is not updated.

  As described later, the delay amount ROM 40 stores delay amount data to be applied to each signal line in correspondence with the number of simultaneous changes as tap values to the delay circuits DL_0 to DL_7. Therefore, the read data R_data read from the delay amount ROM 40 is a tap value corresponding to the delay amount, and is stored in the setting tap information register 309 with the count value Count = 14. When the count value Count = 15, the old simultaneous change number in the setting state holding register 303 is updated with the current simultaneous change number, and the tap setting register 311 is updated with the tap value stored in the setting tap information register 309. Is done. The tap setting register 311 is updated in response to the falling edge of the reference clock Ref_CLK being inverted to the rising edge by the inverter 310, and the setting state holding register 303 is updated in response to the rising edge of Ref_CLK. .

  As described above, according to the 4-bit count value Count of the timing generation counter 203, the detection of the simultaneous change number, the comparison between the old simultaneous change number and the current simultaneous change number, and the comparison result are obtained in 16 count cycles of the count value. When the values are not equal, the reading of the tap value to the delay ROM 40 and the setting to the tap setting register 311 are repeated. Therefore, when the detected number of simultaneous changes changes, the delay amount corresponding to the number of simultaneous changes is set in the delay circuits DL_0 to DL_7.

  FIG. 7 is a diagram illustrating the delay circuit and the relationship between the tap value and the delay amount. The delay circuit DL_ # includes a buffer group 313 including a plurality of buffers for delaying the input data signal Data, and a selector 315 that selects a plurality of nodes in the buffer group 313 based on the setting code S_CODE. FIG. 7 shows a correspondence table between the tap value of the selector and the setting code S_CODE. The smaller the setting code S_CODE, that is, the smaller the tap value, the smaller the delay amount inserted by the delay circuit DL_ #. In this case, the amount of delay increases. Each 4-bit setting code S_CODE for the eight delay circuits DL_0 to DL_7 is set in the tap setting register 311 of FIG. Therefore, this setting code S_CODE is stored in the delay amount ROM 40 corresponding to the number of simultaneous changes.

  FIG. 8 is a diagram showing the format of the delay amount ROM. The address includes a simultaneous change monitoring group Gr, an operation state, and the number of simultaneous changes, and data corresponding thereto is a delay circuit tap setting value (setting code S_CODE of each delay circuit). The 32-bit tap setting value is a 4-bit setting code set in the delay circuit of 8 signal lines. The format shown here also corresponds to an embodiment described later, and in this embodiment, the address information is only the number of simultaneous changes.

  Here, the simultaneous change monitoring group is a signal group to be monitored for simultaneous change, and in this embodiment, eight signal lines SL_0 to SL_7 correspond to one group Gr = 0. For example, when the data bus is 32 bits, the 32 signal lines are divided into 4 groups each including 8 signal lines, and the number of simultaneous changes described above is monitored for the 8 signal lines of each group. Then, delay amounts are set for the eight signal lines in each group.

  FIG. 9 is a diagram showing a specific example of the delay amount ROM. In this example, the address has the group Gr = 0 to x and the number of simultaneous changes (0 to 2, 3 to 5, 6 to 8), and the data is 32 bits corresponding to the delay amount of each delay circuit. Tap setting value (setting code S_CODE of each delay circuit).

  As an example, the group Gr = 0 will be described. When the number of simultaneous changes is 0 to 2, the tap setting values are all “0x0” (zero delay amount). On the other hand, when the number of simultaneously changing lines is 3 to 5, the tap setting values are “0x0” and “0x4”, and the even-numbered data signal lines for data signals Data # 0 to Data # 7 “0x0” (delay amount zero) is set in the delay circuit, and “0x4” (delay amount 4/16) is set in the delay circuit of the odd-numbered data signal line. Furthermore, when the number of simultaneous changes is 6 to 8, the tap setting values are “0x0”, “0x2”, “0x4”, and “0x6”, and data signals Data # 0 to # 4 and data signal Data # These four types of tap setting values are set in 5 to # 7. That is, the eight signal lines are divided into four groups, and different delay amounts are set in the delay circuits of the signal lines of each group.

  FIG. 10 is a diagram showing the delay amount and skew set in the delay circuit. The delay circuit set by the tap setting value of FIG. 9 and the signal waveform after skew adjustment are shown.

  (1) When the number of simultaneous changes is 0 to 2, the eight delay circuits are set to a delay amount of zero. This is because since the number of simultaneous changes is small, it can be considered that the simultaneous switching noise is small, so there is little need to generate a skew between signals.

  (2) When the number of simultaneous changes is 3 to 5, the delay circuit of the even-numbered data signal line for the data signals Data # 0 to Data # 7 is “0x0” (zero delay amount), and the odd-numbered “0x4” (delay amount 4/16) is set in the delay circuit of the data signal line. That is, since the number of simultaneous changes is relatively large, the data signal lines are divided into two groups, and the delay amount zero is set on one side and the delay amount 4 is set on the other side to generate skew as shown in the figure. Thereby, it is possible to reduce the probability that the switching operations in the output buffer by the simultaneously changed signal lines coincide with each other.

  (3) When the number of simultaneous changes is as large as 6 to 8, the data signal lines are divided into 4 groups each having 2 data lines, and each group is set with zero delay amount, delay amount 2, delay amount 4, and delay amount 6 Thus, a skew as shown in the figure is generated. When the number of simultaneous changes is large, it is desirable to suppress the probability of simultaneous change by varying the delay amount for each of the many groups.

  The delay amount in FIG. 10 is an example, and the difference in the number of simultaneously changing lines may be made finer, and different delay amounts may be set for each number of simultaneously changing lines. For example, when the number of simultaneous changes is 8, all the delay amounts of the 8 signal lines may be made different.

  As shown in FIGS. 8, 9, and 10, in this embodiment, when the simultaneous change of the signal on the signal line is detected, the delay amount of the delay circuit provided on each signal line is adjusted to reduce the skew between the signals. Adjust appropriately to suppress simultaneous switching by the output buffer. However, this delay amount cannot exceed the allowable delay amount that conforms to the AC specifications of the input circuits of other LSIs or macros that are supplied with the output of the output buffer. Therefore, the delay amount set in the delay amount ROM is set to be less than the allowable delay amount conforming to this AC specification.

  FIG. 11 is a diagram illustrating the allowable delay amount. In the figure, a reference clock Ref_CLK inside the LSI and a system clock S_CLK for a plurality of LSIs are shown. These clocks are synchronized and have the same period T, but there may be a predetermined phase difference dT between the two clocks as shown.

  In FIG. 3, at the output stage of the LSI, the final stage flip-flop 1 latches the data signal in response to the reference clock Ref_CLK. Then, the data signal is output to another LSI or other macro in the subsequent stage through the signal line SL and the output buffer OB. The other LSI or other macro input circuit in the subsequent stage takes in the input signal at the rising edge of the system clock S_CLK, and the setup time Ts and hold time Th are determined as AC specifications for the input circuit.

  In FIG. 11, for data A and data B, the sum TOx of the output delay from the final-stage flip-flop and the delay of the output buffer, and the allowable delay value satisfying the setup time Ts are shown. The delay value TOx on the output side varies depending on the process conditions, temperature conditions, power supply voltage, etc., so there are maximum and minimum values. Therefore, the cases where the delay values TOx are the maximum and the minimum are shown for the data A and B, respectively.

The allowable delay values that satisfy the setup time Ts are as follows for the data A and B, respectively.
DataA = T-Toa_max-Ts + dT
DataB = T-Tob_max-Ts + dT
Since the delay value TOx of data B is larger, the allowable delay value of data B is smaller. Therefore, a delay amount less than the allowable delay value of the data B is set in the delay amount ROM 40. As a result, it is guaranteed that the skew-adjusted output signal is supplied to the subsequent LSI or macro input circuit at a timing that satisfies the setup time Ts.

[First Embodiment (2)]
FIG. 12 is a diagram illustrating a modified example of the skew adjustment circuit according to the first embodiment. 3 is different from the skew adjustment circuit 10 in FIG. 3 in that it has an operation state monitoring circuit 50 and the delay amount ROM 40 stores a delay amount corresponding to the number of simultaneous changes and the operation speed detected by the operation state monitoring circuit. It is that you are. The delay circuits DL_0 to DL_7 are the same as in FIG. 7, and the simultaneous change monitoring circuit 20 is the same as in FIG.

  In this modified example, the operation state monitoring circuit 50 monitors the change in the gate speed in the LSI caused by the operation state (process condition, temperature condition, voltage condition variation), and the operation state signal Fast when the speed is high. And an operation state signal Typical in a typical case and an operation state signal Slow in a low speed are output. Corresponding to this speed, the delay ROM 40 can store a delay amount for skew adjustment and set a delay amount suitable for the operation state in the delay circuit.

  Specifically, compared with the delay amount when the speed is typical, when the speed is high, the delay amount in the delay circuit DL is increased, that is, the number of delay buffers is increased, and the absolute delay time, that is, absolute The amount of skew is equivalent to that of a typical speed. On the other hand, when the speed is low, the delay amount in the delay circuit DL is reduced, that is, the number of delay buffers is reduced, and the absolute delay time, that is, the absolute skew is set to a typical speed. Make equal.

  The reasons why the operating speed varies depending on whether the operating speed is high or low are firstly the process conditions such as manufacturing variations caused by the target value at the time of manufacturing the device, secondly, whether the power supply voltage is high or low, Whether the temperature is high or low. As described above, the delay amount of the delay circuit is a value that gives an appropriate skew for simultaneous switching noise reduction and needs to be set to a value less than the allowable delay amount. Therefore, it is desirable to change the number of delay buffers in the delay circuit in accordance with the variation in operation speed.

  FIG. 13 is a diagram illustrating an example of the operation state monitoring circuit 50. The operation state monitoring circuit detects the phase difference between the delay circuit 501 that delays the clock CLK0 having the phase 0 ° and outputs the clock CLK90 having the phase 90 °, and the two clocks CLK0 and CLK90, and the phase difference is 90 °. A delay control circuit 503 for generating a delay control signal 507 for the delay circuit. The delay circuit 501 has the same configuration as the delay circuit shown in FIG. Therefore, the delay control signal 507 is a control signal that selects a signal that has propagated more buffers if the LSI gate speed is high, and a control signal that selects a signal that has propagated less buffers if the gate speed of the LSI is low. Become. In the example of FIG. 13, the delay control signal 507 is decoded by the decoder 505 and converted into three types of operation state signals Fast, Typical, and Slow.

  As shown in the delay adjustment circuit 30 of FIG. 5, in this embodiment, the operation state signal output from the operation state monitoring circuit 50 is latched in the operation state register 313. The latch timing may be an appropriate timing after the control enable signal Cnt_EN becomes H. For example, it is possible to synchronize with the comparison operation timing of the simultaneous change number comparator 307 by latching with the timing count value Count = 11. The delay adjustment circuit 30 uses an operation state signal in addition to the simultaneous change number as an address when referring to the delay amount ROM 40.

  FIG. 14 is a diagram illustrating a specific example of the delay amount ROM. In the case of this ROM, in addition to the simultaneous change monitoring group Gr and the number of simultaneous changes as an address, it has an operating state. The data is a tap setting value of 4 bits × 8 = 32 bits set in 8 delay circuits. Compared with the ROM of FIG. 9, the operation state is added to the address, and the tap setting values of FIG. 9 are stored as data corresponding to each of the three operation states. The tap setting value corresponding to the number of simultaneous changes is the same as in FIG. 9, and the skew added to the delay circuit and the signal set thereby is the same as in FIG.

  However, as shown in FIG. 14, the tap setting value when the operation state is high speed Fast is set to be larger than that at the typical speed typical, and the tap setting value at low speed Slow is larger than that at the typical speed typical. It is set small.

  By referring to the delay amount ROM 40, an appropriate delay amount corresponding to the operation state and corresponding to the number of simultaneous changes can be set in the delay circuits DL_0 to DL_7.

  The delay amount ROM 40 may be a rewritable memory. If it is a rewritable memory, the optimal delay can be rewritten according to the operating environment of the LSI, for example, AC specifications of other LSIs that input output signals, and optimal skew adjustment is possible. .

[First Embodiment (3)]
FIG. 15 is a diagram illustrating a second modification of the skew adjustment circuit according to the first embodiment. Similarly to FIG. 3, the skew adjustment circuit 10 includes a simultaneous change monitoring circuit 20, a delay adjustment circuit 30, and delay circuits DL_0 to DL_7. The simultaneous change monitoring circuit 20 has the same configuration as that in FIG. 4, and the delay circuit has the same configuration as that in FIG.

  However, unlike FIG. 3, the memory storing the delay amount is stored in the RAM 70 provided outside the LSI, and the tap setting of the delay circuit is performed by the external CPU. Accordingly, the delay adjustment circuit 30 of the second modification has the configuration of FIG. 16 instead of the configuration of FIG. In addition, a CPU interface 62 that interfaces with an external CPU bus is provided, and an interface operation between the delay adjustment circuit 30 and the CPU is performed.

  The CPU downloads an optimal delay amount from the RAM 70 as appropriate. By making the delay amount of the RAM 70 rewritable in this way, for example, it is possible to dynamically set a delay amount that conforms to the AC specifications of other LSIs or other macros that input signals output from the output buffer. it can.

  Further, the RAM 70 and the CPU may be provided in a common LSI. That is, when the LSI is a system LSI, a CPU and a RAM are provided in the LSI, and these may be used.

  FIG. 16 is a diagram showing a delay adjustment circuit in the second modification. The delay adjustment circuit 30 includes a change number register 315 that latches the 4-bit change number data output from the simultaneous change monitoring circuit 20 at the timing of the timing count value Count = 10, and a tap value corresponding to the delay amount from the RAM 70 as the CPU. It has a delay setting register 317 that is stored via the interface 62, and a tap setting register 311 that stores the tap value stored in the delay setting register 317 in response to the inverter 310 (the falling edge of the reference clock Ref_CLK). The configuration of the simultaneous change monitoring circuit 20 is the same as that in FIG.

  The simultaneous change monitoring circuit 20 outputs the number of simultaneous changes at the timing count value Count = 8, as described with reference to FIGS. The change number register 315 in the delay adjustment circuit 30 in FIG. 16 takes in the change number data with the timing count value Count = 10, and sets the change number effective bit to “1” when the change number data is read.

  The CPU periodically checks the change number valid bit via the CPU interface 62, and reads the change number data from the change number register 315 when the valid bit becomes valid “1”. The CPU reads the tap value (setting code S_CODE of each 32-bit delay circuit) corresponding to the delay amount stored in the delay amount RAM 70 using the change number data as an address, and stores the CPU interface 62 in the delay setting register 317. When writing is completed, the tap switching on bit in the delay setting register is set to valid “1”.

  When the tap switching on bit becomes valid “1”, the tap setting register 311 latches the setting code in the delay setting register 317 in response to the falling edge of the reference clock Ref_CLK, and delays the delay circuits DL_0 to DL_7. The volume setting is complete. At the same time, when the tap switching on bit becomes valid “1”, the change number valid bit of the change number register 315 is cleared to “0”. When the setting of the delay amount is completed, the tap switching on bit is also cleared to “0”. Thereafter, as long as this valid bit is cleared to “0”, the CPU does not read the tap setting value from the memory and set it.

  A configuration example of the RAM 70 is the same as that in FIG. That is, the address has the simultaneous change number monitoring group Gr and the simultaneous change number, and correspondingly, the tap value (32-bit setting code S_CODE of each delay circuit) is stored as data.

  As described above, the RAM 70 is a memory controlled by the CPU, and data with a delay amount conforming to the AC specifications of other LSIs and other macros to which the output signal from the output buffer is supplied is downloaded as appropriate by the CPU. . Therefore, the setting timing of the tap value to the delay circuit corresponding to the simultaneous change number is controlled by the CPU, not the timing count value Count.

[First Embodiment (4)]
FIG. 17 is a diagram illustrating a third modification of the skew adjustment circuit according to the first embodiment. In the third modification example, unlike the second modification example of FIG. 15, the skew adjustment circuit 10 includes an operation state monitoring circuit 50. The simultaneous change monitoring circuit 20 is the same as in FIG. 4, and the delay circuits DL_0 to DL_7 are the same as in FIG.

  The delay adjustment circuit 30 is as shown in FIG. 16, and unlike the second modification, the operation state signal from the operation state monitoring circuit 50 is latched in the change number register 315 with the timing count value Count = 10. When the change number valid bit becomes valid “1”, the CPU reads the tap value for the delay amount in the delay amount RAM 70 using the simultaneous change number and the operation state signal as addresses, and sets them in the delay setting register 317. The subsequent operation is the same as in the second modification.

  The configuration example of the delay amount RAM 70 is the same as that in FIG. 14, and there is operation state data in addition to the simultaneous change number monitoring group Gr and the simultaneous change number in the address. Therefore, the delay amounts are stored separately corresponding to the three operation states.

  As described above, in the first embodiment, the skew adjustment circuit monitors the number of simultaneous changes in the monitoring period of, for example, eight signal lines for monitoring the number of simultaneous changes, and the number of simultaneous changes increases as the number of simultaneous changes increases. , The eight signal lines are divided into more groups, and different delay amounts are set for the respective groups. Thereby, simultaneous switching noise due to simultaneous change can be suppressed.

[Second Embodiment]
In the first embodiment, regardless of whether a signal change of a plurality of signal lines is rising (Rise) or falling (Fall), the number of simultaneous changes is monitored, and a delay amount corresponding to the number of changes is set for each signal. Giving to the line. However, even if they change at the same time, power supply noise occurs at the rise and ground noise occurs at the fall. Therefore, even if all of the eight signal lines change simultaneously, if there is one rising edge and six falling edges, the ground noise, which has a large number of changes, becomes a problem as simultaneous switching noise. It is sufficient to adjust the skew with respect to the six signal lines in which the occurrence of the error occurs. In addition, LSIs may be highly resistant to power supply noise or may be highly resistant to ground noise. Therefore, depending on whether the simultaneous change is on the rising side or the falling side, it may be desirable to appropriately select the delay amount according to the degree of the tolerance.

  In the second embodiment, the skew adjustment circuit has a Rise / Fall change monitoring circuit, detects the number of simultaneous rising changes and the number of simultaneous falling changes, and determines the optimum delay amount according to the detection result. To decide.

  FIG. 18 is a diagram of a skew adjustment circuit according to the second embodiment. The skew adjustment circuit 10 includes a rise / fall change monitoring circuit 60, a delay adjustment circuit 30, and a delay amount ROM 40. Further, the skew adjustment circuit 10 includes delay circuits DL_0 to DL_7 on the plurality of signal lines SL_0 to SL_7, respectively, and the delay adjustment circuit 30 sets the respective delay amounts.

  The Rise / Fall change monitoring circuit 60 monitors the simultaneous rise change and fall change of the eight signal lines SL_0 to SL_7, and sets the rise or fall as the simultaneous change number, whichever has the larger change number between the rise and fall. It is supplied to the delay adjustment circuit 30 together with the falling data. Then, the delay adjustment circuit 30 reads the tap value (setting code) corresponding to the delay amount from the delay amount ROM 40 using the number of simultaneous changes and the rising or falling data as an address, and the tap value as the delay amount of the delay circuit. Set.

  FIG. 19 is a diagram showing the Rise / Fall change monitoring circuit 60. The Rise change monitoring circuit 610 detects rising changes occurring in the eight signal lines during the monitoring period corresponding to one cycle of the reference clock, and counts the number thereof. Therefore, rising change detection circuits 611_0 to 611_7 are provided for the eight signal lines SL_0 to SL_7, respectively.

  This rising change detection circuit 611_0 includes a register SR # 0 that latches the signal line signal in response to the reference clock Ref_CLK, and an AND gate that calculates the AND of the signal line signal and the inverted output of the register SR # 0. Have. When the signals of the signal lines SL_0 to SL_7 change from the L level to the H level, the AND gate generates a rising detection pulse having a pulse width from the signal change to the reference clock in response to the subsequent reference clock Ref_CLK.

  The monitoring result holding registers Moni_R # 0 to Moni_R # 7 latch the AND gate detection pulse when the count value Count output from the timing generation counter 613 becomes zero. Further, the selector 615 sequentially selects the monitoring result holding registers Moni_R # 0 to Moni_R # 7 corresponding to the timing when the count value Count becomes 1 to 8, and the Rise change number counter 617 enables the rise of the selector output. The signal Rise_en = 1 is counted and the counted change number is output to the change number comparator 620. The Rise change number counter 617 is reset when the count value Count = 0, and then starts counting, and counts the rising enable signal Rise_en = 1 in response to the reference clock Ref_CLK.

  On the other hand, the Fall change monitoring circuit 620 detects falling changes that occurred in the eight signal lines during the monitoring period, and counts the number thereof. For this purpose, falling change detection circuits 621_0 to 621_7 are provided for the eight signal lines SL_0 to SL_7, respectively.

  This falling change detection circuit 621_0 calculates the AND of the register SR # 0 that latches the signal of the signal line in response to the reference clock Ref_CLK, and the inverted signal of the signal of the signal line and the non-inverted output of the register SR # 0 And an AND gate. When the signal of the signal line changes from the H level to the L level, the AND gate generates a falling detection pulse having a pulse width from the change of the signal to the reference clock in response to the subsequent reference clock Ref_CLK.

  The remaining configuration is the same as that of the Rise change monitoring circuit 610. When the count value Count = 0, the monitoring result holding registers Moni_R # 0 to # 7 latch the falling change, and when the count value Count = 1 to 8, the selector 625 Parallel / serial conversion is performed, and the Fall change number counter 627 counts.

  The change number comparison circuit 620 compares the Rise change number with the Fall change number at the timing of the count value Count = 9, and outputs the larger change number and a comparison result indicating which is larger to the delay adjustment circuit 30. .

  As described above, the Rise / Fall change monitoring circuit 60 detects the number of Rise changes and the number of Fall changes of the eight signal lines once every 16 cycles of the count value Count generated by the timing generation counter 613, and the larger of them is detected. The number of changes and the comparison result with the larger Rise / Fall are output.

  The delay adjustment circuit 30 of FIG. 18 is shown in FIG. In FIG. 5, since the number of changes from the rise / fall change monitoring circuit 60 and the comparison result are supplied to the delay adjustment circuit 30, they are held in the change number holding register 301 at the timing of the count value Count = 10. The subsequent comparison operation in the change number comparator 307, the read operation to the delay ROM 40, the read data setting operation to the setting tap information register 309, and the update operation to the tap setting register 311 are the same as the operations in FIG. is there.

  FIG. 20 is a diagram showing the format of the delay amount ROM 40. The address of the delay amount ROM has a comparison result (Rise or Fall) in addition to the simultaneous change monitoring target group Gr and the number of changes. Then, tap setting values (32-bit setting codes) of the delay circuit corresponding to those addresses are stored as data. In other words, the tap setting value corresponding to the number of simultaneously changing lines is stored in the delay amount ROM depending on whether the simultaneously changed signal rises (Rise) or falls (Fall).

  FIG. 21 is a diagram showing a specific example of the delay amount ROM 40. As can be understood by comparing with the specific example of the delay amount ROM shown in FIG. 9, the ROM of FIG. 21 has an address in which the comparison result is Rise in addition to the simultaneous change monitoring target group Gr and the number of simultaneous changes. And a tap setting value (32-bit setting code) corresponding to the delay amount for each of the cases of falling and falling. According to the data example of FIG. 21, the same tap setting value is used for the rise (Rise) and the fall (Fall). For example, the tap setting value on the rising side may be set to a larger delay amount. .

  The delay amount corresponding to the number of simultaneous changes stored in the delay amount ROM 40 is the same as that in FIG. 9, and as shown in FIG. 10 according to the number of simultaneous changes in rising or falling with the larger number of changes. The delay amount is set so as to cause a skew. That is, an appropriate delay amount corresponding to rising and falling can be set. Further, the delay amount is set to be less than the allowable delay amount as shown in FIG.

  Therefore, the delay adjustment circuit 30 reads the tap setting value of the delay circuit from the delay amount ROM 40 using the group Gr, the number of simultaneous changes, and the comparison result as addresses, and sets them in the setting tap information register 309. The set tap value is updated in the tap setting register 311 in synchronization with the falling edge of the reference clock Ref_CLK at the timing of the count value Count = 15.

  In the second embodiment, unlike the first embodiment, the delay amount of the delay circuit is set in accordance with the number of simultaneously rising or falling lines. Therefore, the number of detected simultaneous changes is smaller than the number of simultaneous changes in both rising and falling. Therefore, it is only necessary to perform a minimum necessary skew adjustment corresponding to the number of simultaneous changes. Further, an optimum delay amount can be set for each of the rising edge and the falling edge.

[Second Embodiment (2)]
FIG. 22 is a diagram illustrating a first modification of the skew adjustment circuit according to the second embodiment. The skew adjustment circuit 10 includes an operation state monitoring circuit 50 in addition to the configuration of FIG. The Rise / Fall change monitoring circuit 60 is the circuit shown in FIG. 19, and the delay adjustment circuit 30 is the circuit shown in FIG. The operation state monitoring circuit 50 is the circuit shown in FIG.

  FIG. 23 is a diagram illustrating a specific example of the delay amount ROM 40. Unlike the case of FIG. 21, the delay amount ROM 40 includes an operation state signal output from the operation state monitoring circuit 50 in its address. The rest is the same as FIG. When the operating state signal is Fast, the tap setting value is a value that can set a larger delay amount. Conversely, when the operating state signal is Slow, the tap setting value is a value that can set a smaller delay amount. It has become. The setting of the delay amount for this operation state signal is the same as the ROM delay amount in FIG.

  In the example of FIG. 23, the delay amounts corresponding to Rise and Fall are the same. However, it is more preferable that the delay amounts are made different according to the characteristics of the LSI.

[Second Embodiment (3)]
FIG. 24 is a diagram illustrating a second modification of the skew adjustment circuit according to the second embodiment. The skew adjustment circuit 10 sets a delay amount with reference to a delay amount RAM 70 outside the LSI. Then, the CPU outside the LSI reads the delay amount from the delay amount RAM 70 and sets the tap setting value of the delay circuit. Further, the CPU appropriately downloads a delay amount corresponding to the AC specifications of another LSI to which the output signal of the output buffer is input or another macro in the LSI, and stores it in the RAM 70.

  The Rise / Fall change monitoring circuit 60 is the circuit shown in FIG. 19, and the delay adjustment circuit 30 is the circuit shown in FIG. A specific example of the delay amount RAM 70 is the same as the specific example of FIG.

  The delay circuit tap setting operation by the CPU for the delay adjustment circuit 30 is as described with reference to FIG.

[Second Embodiment (4)]
FIG. 25 is a diagram illustrating a third modification of the skew adjustment circuit according to the second embodiment. The skew adjustment circuit 10 includes an operation state monitoring circuit 50 in addition to the configuration of FIG. The Rise / Fall change monitoring circuit 60 is the circuit shown in FIG. 19, the delay adjustment circuit 30 is the circuit shown in FIG. 16, and the specific example of the delay amount RAM 70 is the same as that in FIG. The operation state monitoring circuit 50 is the circuit shown in FIG.

  As described above, according to the skew adjustment circuit of the second embodiment, the number of simultaneous changes in the signal on the signal line is monitored by distinguishing between rising and falling, and the delay is determined according to the information on the larger number of simultaneous changes. Set the amount. Therefore, a more appropriate delay amount can be set based on a more accurate monitoring result. Also, an appropriate delay amount can be set for each of the rising edge and the falling edge.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of signal lines that are provided in the integrated circuit device and respectively propagate a plurality of signals;
A plurality of buffer circuits to which a plurality of signals propagating through the plurality of signal lines are respectively input;
A plurality of delay circuits respectively provided in a preceding stage of the plurality of buffer circuits;
A monitoring circuit for monitoring signal changes of the plurality of signal lines;
A delay adjustment circuit that determines a delay amount of the plurality of delay circuits based on a monitoring result output of the monitoring circuit and sets the delay amounts in the plurality of delay circuits;
The monitoring circuit detects, as the monitoring result, the number of signal changes, which is the number of signal lines in which a signal change has occurred within a monitoring period,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount based on the number of signal changes.

(Appendix 2)
In Appendix 1,
The delay adjustment circuit determines the delay amount of the plurality of delay circuits as N types of delay amounts when the number of signal changes is a first number, and when the number of signal changes is a second number greater than the first number. A skew adjustment circuit that determines delay amounts of the plurality of delay circuits to M types of delay amounts greater than N.

(Appendix 3)
In Appendix 1 or 2,
The monitoring circuit includes a plurality of signal change detection circuits that detect signal changes of the plurality of signal lines, respectively, and a counter that counts signal changes of the plurality of signal change detection circuits and outputs the number of signal changes. Skew adjustment circuit.

(Appendix 4)
In Appendix 1 or 2,
The monitoring circuit periodically and repeatedly detects the number of signal changes within the monitoring period;
The delay adjustment circuit is a skew adjustment circuit that newly determines the delay amount and sets the delay amount in the plurality of delay circuits when the number of signal changes detected by the monitoring circuit changes between different periods.

(Appendix 5)
In Appendix 1 or 2,
The monitoring circuit periodically and repeatedly detects the number of signal changes within the monitoring period;
The delay adjustment circuit is a skew adjustment circuit that newly determines the delay amount and sets the delay amount in response to detection of the number of signal changes by the monitoring circuit.

(Appendix 6)
In Appendix 1,
The monitoring circuit is
A plurality of first signal change detection circuits for respectively detecting a first signal change from a first level to a second level of the plurality of signal lines; and a plurality of signal lines from the second level to the first level. A plurality of second signal change detection circuits for respectively detecting second signal changes, and a signal change number comparison circuit for comparing the number of first signal changes and the number of second signal changes;
The delay adjustment circuit is a skew adjustment circuit that determines the amount of delay based on the larger number of multiple signal changes among the number of first or second signal changes.

(Appendix 7)
In Appendix 6,
The delay adjustment circuit is a skew adjustment circuit for determining the delay amount based on change data on a larger side of the first and second signal changes in addition to the number of multiple signal changes.

(Appendix 8)
In Appendix 6 or 7,
The delay adjustment circuit determines the delay amount of the plurality of delay circuits as N types of delay amounts when the number of large signal changes is a first number, and sets a second number greater than the first number. In some cases, the skew adjustment circuit determines a delay amount of the plurality of delay circuits to M types of delay amounts larger than the N.

(Appendix 9)
In any of Supplementary Notes 6 to 8,
The monitoring circuit periodically and repeatedly detects the number of the first and second signal changes within the monitoring period;
The delay adjustment circuit is a skew adjustment circuit that newly determines the delay amount and sets the delay amount in the plurality of delay circuits when the number of large signal changes detected by the monitoring circuit changes between different periods.

(Appendix 10)
In any of Supplementary Notes 6 to 8,
The monitoring circuit periodically and repeatedly detects the number of the first and second signal changes within the monitoring period;
The delay adjustment circuit is a skew adjustment circuit that newly determines the delay amount and sets the delay amount in the plurality of delay circuits in response to detection of the number of changes in the multiple signals by the monitoring circuit.

(Appendix 11)
In Appendix 1 or 2,
And a delay amount memory for storing a delay amount corresponding to the number of signal changes,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount with reference to the delay amount memory.

(Appendix 12)
In any of Supplementary Notes 6 to 8,
And a delay amount memory for storing a delay amount corresponding to the number of the first and second signal changes,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount with reference to the delay amount memory.

(Appendix 13)
In Appendix 11 or 12,
The delay amount memory is a rewritable memory, and a skew adjustment circuit in which the delay amount is rewritten.

(Appendix 14)
In Appendix 11 or 12,
The skew adjustment circuit, wherein the delay amount in the delay amount memory is a delay amount conforming to a setup time specification of another integrated circuit device to which outputs of a plurality of buffer circuits of the integrated circuit device are input.

(Appendix 15)
In any one of Supplementary Notes 1, 2, 6, 7, and 8,
And an operation state monitoring circuit for monitoring an operation state of the gate in the integrated circuit device,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount according to the operation state detected by the operation state monitoring circuit.

(Appendix 16)
In any one of appendices 1-15,
Skew adjustment having a control enable signal for controlling operation enable and operation disable of the monitoring circuit and the delay adjustment circuit, and controlling the start and stop of the operation of the monitoring circuit and the delay adjustment circuit according to the control enable signal circuit.

(Appendix 17)
A signal change that is a plurality of signal lines provided in the integrated circuit device and that is the number of signal lines that have undergone a signal change within a monitoring period among a plurality of signal lines that respectively propagate signals to a plurality of buffer circuits Detect the number,
Skew adjustment for determining a delay amount of a plurality of delay circuits respectively provided in a preceding stage of the plurality of buffer circuits based on the number of signal changes, and adjusting a delay amount of the plurality of delay circuits to the determined delay amount Method.

(Appendix 18)
In Appendix 17,
When the number of signal changes is the first number, the delay amounts of the plurality of delay circuits are determined as N types of delay amounts, and when the number of signal changes is a second number greater than the first number, A skew adjustment circuit method for determining a delay amount to M types of delay amounts larger than N.

10: Skew adjustment circuit 20: Simultaneous change monitoring circuit 30: Delay adjustment circuit 40: Delay amount ROM
DL_0 to DL_7: Delay circuit OB_0 to OB_7: Output buffer
SL_0 to SL_7: Signal line SG_0 to SG_7: Signal

Claims (8)

A plurality of signal lines for propagating a plurality of signals, respectively,
A plurality of buffer circuits to which a plurality of signals propagating through the plurality of signal lines are respectively input;
A plurality of delay circuits respectively provided in a preceding stage of the plurality of buffer circuits;
A monitoring circuit for detecting the number of signal changes, which is the number of signal lines in which a signal change has occurred within a monitoring period ;
A delay amount memory for storing a plurality of types of delay amounts according to the number of signal changes;
A delay adjustment circuit that refers to the delay amount memory, determines delay amounts of the plurality of delay circuits from the plurality of types of delay amounts in the delay amount memory in accordance with the number of signal changes, and sets the delay amounts in the plurality of delay circuits. And an integrated circuit device . In claim 1,
The delay adjustment circuit determines the delay amount of the plurality of delay circuits as N types of delay amounts when the number of signal changes is a first number, and when the number of signal changes is a second number greater than the first number. An integrated circuit device that determines a delay amount of the plurality of delay circuits as M types of delay amounts larger than the N. A plurality of signal lines respectively propagating a plurality of signals;
A plurality of buffer circuits to which a plurality of signals propagating through the plurality of signal lines are respectively input;
A plurality of delay circuits respectively provided in a preceding stage of the plurality of buffer circuits;
A plurality of first signal variation detecting circuit for detecting the number of the first signal changes from the first level within the monitoring period of the plurality of signal lines to the second level, within the monitoring period of the plurality of signal lines A plurality of second signal change detection circuits for detecting the number of second signal changes from the second level to the first level, and a signal for comparing the number of first signal changes and the number of second signal changes a monitoring circuit for chromatic and change number comparing circuit,
A delay amount memory for storing a plurality of types of delay amounts according to the number of the first and second signal changes;
Referring to the delay amount memory, the delays of the plurality of delay circuits are determined from the plurality of types of delay amounts in the delay amount memory in accordance with the larger number of signal changes of the first or second signal changes. A delay adjustment circuit that determines an amount and sets the delay circuit in the plurality of delay circuits . In claim 3,
The delay adjustment circuit determines the delay amount of the plurality of delay circuits as N types of delay amounts when the number of large signal changes is a first number, and sets a second number greater than the first number. In some cases, the integrated circuit device determines a delay amount of the plurality of delay circuits as M types of delay amounts greater than the N. In claim 1 or 3 ,
The delay amount memory is a rewritable memory, and an integrated circuit device in which the delay amount is rewritten. In claim 1 or 3 ,
Wherein the delay amount of the delay amount in the memory, the integrated circuit other integrated circuit device is a delay conforming to the specifications of the set-up time integrated circuit device for receiving the output of a plurality of buffer circuits of the device. In any one of Claims 1, 2, 3, and 4,
And an operation state monitoring circuit for monitoring an operation state of the gate in the integrated circuit device,
The delay adjustment circuit is an integrated circuit device that determines the delay amount according to the operation state detected by the operation state monitoring circuit. A plurality of signal lines respectively propagating a plurality of signals;
A plurality of buffer circuits to which a plurality of signals propagating through the plurality of signal lines are respectively input;
A skew adjustment method for an integrated circuit device, comprising: a plurality of delay circuits provided in front of the plurality of buffer circuits;
Detecting the number signal change number is the signal line to which a signal change has occurred in the monitoring period,
A delay amount memory that stores a plurality of types of delay amounts corresponding to the number of signal changes, and a delay amount of the plurality of delay circuits from the plurality of types of delay amounts in the delay amount memory according to the number of signal changes determining the skew adjustment method for an integrated circuit device for adjusting the delay amount of the plurality of delay circuits in the delay amount of the determined.

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