KR20110109556A - Sense amplifier enable signal generation circuit of semiconductor memory apparatus - Google Patents

Sense amplifier enable signal generation circuit of semiconductor memory apparatus Download PDF

Info

Publication number
KR20110109556A
KR20110109556A KR1020100029341A KR20100029341A KR20110109556A KR 20110109556 A KR20110109556 A KR 20110109556A KR 1020100029341 A KR1020100029341 A KR 1020100029341A KR 20100029341 A KR20100029341 A KR 20100029341A KR 20110109556 A KR20110109556 A KR 20110109556A
Authority
KR
South Korea
Prior art keywords
sense amplifier
signal
amplifier enable
enable signal
delay
Prior art date
Application number
KR1020100029341A
Other languages
Korean (ko)
Inventor
이준규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100029341A priority Critical patent/KR20110109556A/en
Publication of KR20110109556A publication Critical patent/KR20110109556A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Landscapes

  • Dram (AREA)

Abstract

The sense amplifier enable signal generation circuit of the semiconductor memory device may include a copy circuit unit configured to copy a data bus sense amplifier inside the semiconductor memory device, a comparator configured to compare two internal signals of the copy circuit unit to generate a comparison signal, and in response to the comparison signal. And a code generator configured to count the delay control code, and a delay line configured to delay the preliminary sense amplifier enable signal in response to the delay control code to output a sense amplifier enable signal.

Figure P1020100029341

Description

SENSE AMPLIFIER ENABLE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a sense amplifier enable signal generation circuit of a semiconductor memory device.

As shown in FIG. 1, the data bus sense amplifier 10 according to the related art has a form in which a bit line sense amplifier 11 and a latch 12 are connected.

The data bus sense amplifier 10 starts to operate according to the sense amplifier enable signal EN activated at a predetermined timing.

At this time, when the activation timing of the sense amplifier enable signal EN is fast, the latch 12 is at a level opposite to that of the actual data, and is maintained at the wrong level.

Therefore, in the related art, the timing of activation of the sense amplifier enable signal EN is delayed as much as possible so that the data bus sense amplifier 10 can operate after sufficient charge sharing is performed.

However, as the activation time of the sense amplifier enable signal EN is delayed, the data sensing speed becomes slower, resulting in a loss of address access time tAA.

It is an object of the present invention to provide a sense amplifier enable signal generation circuit of a semiconductor memory device which increases data sensing speed and enables stable data sensing.

An embodiment of the present invention provides a duplicated circuit unit configured to duplicate a data bus sense amplifier inside a semiconductor memory device, a comparator configured to compare two internal signals of the duplicated circuit unit to generate a comparison signal, and to count a delay control code in response to the comparison signal. And configured to output the sense amplifier enable signal by delaying the preliminary sense amplifier enable signal in response to the configured code generator and the delay control code.

Embodiments of the invention provide a latch configured to generate an output signal in response to an input signal, a bit line sense amplifier configured to provide a fixed level of output as an input signal, a first comparison signal and a first signal by comparing the input signal with the output signal. A comparator configured to generate a two comparison signal, a code generator configured to count a delay control code in response to the first comparison signal and the second comparison signal, and adjusting the activation timing of the sense amplifier enable signal in response to the delay control code. And a delay line configured to be configured.

According to an exemplary embodiment of the present invention, the timing of activation of the sense amplifier enable signal is adjusted in real time according to a process / voltage / temperature (PVT) variation, thereby increasing the data sensing speed of the data bus sense amplifier and at the same time enabling stable data sensing.

1 is a circuit diagram of a data bus sense amplifier 10 according to the prior art,
2 is a block diagram of a sense amplifier enable signal generation circuit 100 according to an embodiment of the present invention;
3 is a circuit diagram of the delay line 300 of FIG.
4A and 4B are output waveform diagrams of a latch 220 according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the sense amplifier enable signal ENV generated by the sense amplifier enable signal generation circuit 100 according to the embodiment of the present invention is provided to the data bus sense amplifier 10.

Although only one data bus sense amplifier 10 is shown in FIG. 2, in practice, a myriad of data bus sense amplifiers 10 are configured in an actual semiconductor memory device, and a sense amplifier enable signal generation circuit according to an embodiment of the present invention. The sense amplifier enable signal ENV generated at 100 may be commonly provided to them.

The sense amplifier enable signal generation circuit 100 includes a copy circuit unit 200, a delay line 300, a code generator 400, a comparator 500, and a dummy comparator 501.

The copy circuit 200 includes a bit line sense amplifier 210 and a latch 220.

Since the duplicated circuit unit 200 is configured by replicating the data bus sense amplifier 10, the bit line sense amplifier 210 and the latch 220 have a circuit configuration substantially the same as that of the bit line sense amplifier 11 and the latch 12. Have

However, the bit line sense amplifier 210 is designed to have a fixed output value. The output signal of the bit line sense amplifier 210, that is, the input signals IN and INB of the latch 220 are fixed to logic high '1' and logic low '0', respectively.

The latch 220 generates output signals OUT and OUTB according to the input signals IN and INB.

The delay line 300 is configured to delay the preliminary sense amplifier enable signal EN_PRE by a variable delay time in response to the delay control code CDL <0: N> to output the sense amplifier enable signal ENV. .

At this time, the initial delay time of the delay line 300 is set to a maximum, and the sense amplifier enable signal ENV generated accordingly may be activated at the same timing as the sense amplifier enable signal EN of the prior art.

Therefore, the preliminary sense amplifier enable signal EN_PRE is activated at a timing in consideration of the maximum initial delay time.

The code generator 400 is configured to count the delay control codes CDL <0: N> in response to the comparison signals UP and DN.

In this case, the code generator 400 may include a gray code counter, and the gray code counter may be configured as a shift register using a flip-flop.

The comparator 500 is configured to compare the input signal IN and the output signal OUT to generate the comparison signals UP and DN.

At this time, the comparator 500 activates the first comparison signal UP when the output signal OUT level is higher than the input signal IN level, and the output signal OUT level is lower than the input signal IN level. And to activate the second comparison signal DN.

The dummy comparator 501 is configured to receive an input signal INB and an output signal OUTB. In this case, the dummy comparator 501 is configured to apply a load such as an input signal IN and an output signal OUT to the input signal INB and the output signal OUTB nodes.

As shown in FIG. 3, the delay line 300 includes a plurality of delay cells DC, a plurality of capacitors C, and a plurality of switches SW.

The delay line 300 has a switch SW connected when the delay control code CDL <0: N> is logic high, that is, '1', so that the input signal is next without passing through the delay cell DC. Bypass is performed to the delay cell DC of the stage.

On the other hand, when the delay control code CDL <0: N> is logic low, that is, '0', the switch SW is opened, and accordingly, the input signal passes through the delay cell DC to the next delay cell DC. Is delivered.

As a result, the delay line 300 increases as the number of signal bits having a value of '0' among the signal bits constituting the delay control code CDL <0: N> increases. The more signal bits with values of ', the lower the delay time.

Referring to the operation of the embodiment of the present invention configured as described above are as follows.

In the initial operation, as the sense amplifier enable signal ENV is activated, the output signals OUT and OUTB of the latch 220 are generated.

At this time, since the levels of the input signals IN and INB are already determined, the levels of the output signals OUT and OUTB are also determined.

That is, as shown in FIG. 4A, the input signal IN is at the core voltage VCORE level and the output signal OUT is at the external voltage VDD level. In this case, the external voltage VDD level is higher than the core voltage VCORE level.

Since the level of the output signal OUT is higher than the level of the input signal IN, the comparator 500 activates and outputs the first comparison signal UP.

As can be seen in FIG. 4A, the activation of the first comparison signal UP means that the activation of the sense amplifier enable signal ENV is performed at an appropriate time, and a margin exists. That is, the activation timing of the sense amplifier enable signal ENV can be advanced earlier than the initial stage.

Therefore, the code generator 400 up-counts and changes the delay control codes CDL <0: N> in response to the activated first comparison signal UP to reduce the delay time of the delay line 300.

For example, suppose a 4-bit delay control code CDL <0: 3> is used. The delay control code CDL <0: 3> is initially '0000', and the first comparison signal UP is used. Each time is activated, it is changed in the order of '1000, 1100, 1110'.

The delay line 300 is initially set to have a maximum delay time according to a delay control code CDL <0: 3> having a value of '0000'.

In response to the activated first comparison signal UP, the delay time of the delay line 300 is gradually decreased according to the delay control codes CDL <0: 3> changed in the order of '1000, 1100, and 1110'. do.

As the delay time of the delay line 300 decreases, the activation timing of the sense amplifier enable signal ENV is advanced earlier than the initial stage, and as shown in FIG. 4B, the output signal OUT of the latch 220 at a specific time point is shown. , OUTB) phase is reversed.

The input signal IN maintains the core voltage VCORE level, but the output signal OUT becomes the ground voltage VSS level.

Since the level of the output signal OUT is lower than the level of the input signal IN, the comparator 500 activates and outputs the second comparison signal DN.

The activation of the second comparison signal DN means that the activation timing of the sense amplifier enable signal ENV has been pulled too far. That is, the activation timing of the sense amplifier enable signal ENV should be returned to the previous state.

Therefore, in response to the activated second comparison signal DN, the code generator 400 down counts the delay control codes CDL <0: N> and changes them to their previous values.

For example, if the current delay control code CDL <0: 3> is '1110', it returns to '1100'.

As a result, the delay time of the delay line 300 is adjusted to the previous value, thereby terminating the sense amplifier enable signal ENV activation timing adjustment operation.

As described above, the sense amplifier enable signal ENV having completed the activation timing adjustment is actually provided to the data bus sense amplifiers 10 used for data sensing.

In the prior art, the timing of activation of the sense amplifier enable signal EN is fixed and made as slow as possible.

However, the embodiment of the present invention, as described above, by using the latch 220 of the replication circuit unit 200 formed by replicating the data bus sense amplifier 10 that is actually used to reflect the PVT fluctuation signal (sense amplifier enable signal ( It can be actively adjusted to optimize the activation timing of ENV).

Accordingly, the data bus sense amplifiers 10 in the semiconductor memory device may not only be stable but also perform high-speed data sensing operations according to the sense amplifier enable signal ENV.

In addition, after the above-described sense amplifier enable signal ENV activation timing adjustment operation is completed, in order to prevent unnecessary current consumption, the delay line 300 and the code generator 400 according to the activation of the second comparison signal DN. Except for), the configuration can be stopped.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Claims (8)

A copy circuit unit configured to copy a data bus sense amplifier inside the semiconductor memory device;
A comparator configured to compare two internal signals of the copy circuit unit to generate a comparison signal;
A code generator configured to count a delay control code in response to the comparison signal; And
And a delay line configured to delay a preliminary sense amplifier enable signal in response to the delay control code to output a sense amplifier enable signal. The method of claim 1,
Replication circuit
A latch configured to generate an output signal in response to the input signal, and
And a bit line sense amplifier configured to provide a fixed level of output as the input signal. The method of claim 2,
The comparator
2. The sense amplifier enable signal generation circuit of the semiconductor memory device configured to receive the input signal and the output signal as two internal signals of the copy circuit unit. The method of claim 1,
The delay line is
And a delay amplifier enable signal generation circuit configured to decrease or increase the delay time according to the delay control code. A latch configured to generate an output signal in response to the input signal;
A bit line sense amplifier configured to provide a fixed level of output as the input signal;
A comparator configured to compare the input signal and the output signal to generate a first comparison signal and a second comparison signal;
A code generator configured to count a delay control code in response to the first comparison signal and the second comparison signal; And
And a delay line configured to adjust an activation timing of a sense amplifier enable signal in response to a delay control code. The method of claim 5, wherein
The comparator
And configured to activate the first comparison signal if the level of the output signal is higher than the level of the input signal. The method of claim 5, wherein
The code generation unit
And a count amplifier enable signal generation circuit of the semiconductor memory device configured to up count the delay control code in response to activation of the first comparison signal. The method of claim 5, wherein
The comparator
And a sense amplifier enable signal generation circuit of the semiconductor memory device configured to stop its operation in response to the activation of the second comparison signal.
KR1020100029341A 2010-03-31 2010-03-31 Sense amplifier enable signal generation circuit of semiconductor memory apparatus KR20110109556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100029341A KR20110109556A (en) 2010-03-31 2010-03-31 Sense amplifier enable signal generation circuit of semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100029341A KR20110109556A (en) 2010-03-31 2010-03-31 Sense amplifier enable signal generation circuit of semiconductor memory apparatus

Publications (1)

Publication Number Publication Date
KR20110109556A true KR20110109556A (en) 2011-10-06

Family

ID=45026744

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100029341A KR20110109556A (en) 2010-03-31 2010-03-31 Sense amplifier enable signal generation circuit of semiconductor memory apparatus

Country Status (1)

Country Link
KR (1) KR20110109556A (en)

Similar Documents

Publication Publication Date Title
US9620214B2 (en) Content addressable memory with reduced power consumption and increased search operation speed
TWI670938B (en) Apparatus having a data receiver with a real time clock decoding decision feedback equalizer
US20100054073A1 (en) Semiconductor memory device
KR20170091286A (en) Jitter detection circuit and semiconductor system using the same
CN106716537B (en) Delay circuit with parallel delay lines and internal switches between delay lines, and method and apparatus for controlling the delay circuit
US20070201286A1 (en) Input circuit of a semiconductor memory device and method of controlling the same
US6333875B1 (en) Semiconductor circuit with adjustment of double data rate data latch timings
KR20200007610A (en) Semiconductor device
KR20140019941A (en) Data output circuit of semiconductor apparatus
GB2545408B (en) Data buffer
US20090046813A1 (en) Method and Data Receiver Apparatus for Implementing Memory Read Data Eye Stretcher
US9281034B2 (en) Data strobe generation
US9269409B2 (en) Bit cell write-assistance
US8068383B2 (en) Semiconductor integrated circuit having address control circuit
KR20110109556A (en) Sense amplifier enable signal generation circuit of semiconductor memory apparatus
CN101399078B (en) Synchronous semiconductor memory device
KR20150014611A (en) Data output circuit
JP2013097618A (en) Memory control device
KR100896461B1 (en) Semiconductor device and operating method thereof
US8929173B1 (en) Data strobe control device
CN110390972A (en) Semiconductor devices
US9355707B2 (en) Gapless pattern detection circuit and semiconductor device including the same
JP5533424B2 (en) Integrated circuit device and skew adjustment method for integrated circuit device
TWI610313B (en) Data write circuit of semiconductor apparatus
US9425774B1 (en) Semiconductor apparatus

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination