KR20020017821A - Apparatus for generating pixel clock synchronized horizontal sync. signal using delay locked loop - Google Patents

Abstract

PURPOSE: An apparatus for generating a pixel clock synchronized with a horizontal synchronous signal using a delay locked loop is provided to generate a pixel clock that is synchronized with a horizontal synchronous signal in one integrated circuit by using a delay locked loop. CONSTITUTION: An apparatus for generating a pixel clock synchronized with a horizontal synchronous signal includes a control signal generator(100) for generating the first, second and third control signals for controlling the delay locked loop in response to input clock signals, and a plurality of unit delay means(120,140,160) that are controlled by the first, second and third control signals and sequentially delay the input clock signals for a predetermined period of time. The apparatus further has a buffer(180) for outputting the pixel clock, and a tri-state inverter(200) for fixing the pixel clock to a low level during a low period of the horizontal synchronous signal in response to the first control signal.

Description

Apparatus for generating pixel clock synchronized with horizontal synchronizing signal using delay locked loop {APPARATUS FOR GENERATING PIXEL CLOCK SYNCHRONIZED HORIZONTAL SYNC. SIGNAL USING DELAY LOCKED LOOP}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating a pixel clock for controlling data displayed on a scan line of a television or a monitor, and in particular, to synchronize a horizontal sync signal using a delay locked loop. It relates to a device for generating a pixel clock.

Conventionally, an LC oscillator is used as shown in FIG. 1 to synchronize a pixel clock and a horizontal synchronization signal necessary for a television or a monitor.

1 is a circuit diagram of a conventional apparatus for generating a pixel clock synchronized with a horizontal synchronization signal using an LC oscillator.

As shown in FIG. 1, a conventional pixel clock generator uses an inductor L and two conductors C1 and C2 to provide a delay circuit 10, an amplifier 12, and a negative logic gate 14. The feedback is formed, and the feedback formed is repeated by the inductor L and the two conductors C1 and C2. At this time, a low value is input to the horizontal synchronization signal HS, and the generated frequency is approximately Becomes

Here, since the operation of the LC oscillator is a technical content well known in the art, its detailed description is omitted (Ref .: MICROELECTRONIC CIRCUITS 3rd edition by SEDRA / SMITH, chapter 12.3: LC and Crystal Oscillator).

If the horizontal synchronizing signal HS is input high, the output of the negative logic gate 14 is fixed low and the feedback is cut off, and the amplification by the LC does not occur so that the pixel clock CK_OUT Is fixed low.

When the horizontal synchronization signal HS transitions from high to low, LC oscillation starts again to generate the pixel clock CK_OUT. That is, since the LC oscillation that has been stopped starts from the moment when the horizontal synchronization signal HS goes from high to low, the pixel clock CK_OUT always occurs after the same time from the moment when the horizontal synchronization signal HS goes low. This means that the synchronization of the pixel clock CK_OUT is consistently performed by the horizontal synchronization signal HS.

This LC oscillator has two problems despite its stability. First, in order to use this LC oscillator in an integrated circuit, the inductor (L) and the two capacitors (C1, C2) are too large. It must be external to the chip, and second, the LC outside the integrated circuit creates noise in the entire system that uses the chip, reducing its stability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an apparatus for generating a pixel clock synchronized with a horizontal synchronization signal in one integrated circuit using a delay locked loop.

1 is a circuit diagram of a conventional apparatus for generating a pixel clock synchronized with a horizontal synchronization signal using an LC oscillator.

2 is a block diagram of an apparatus for generating a pixel clock according to an embodiment of the present invention.

3 is a signal timing diagram of FIG. 2 according to an embodiment of the present invention;

4 is an internal circuit diagram of the control signal generation unit of FIG. 2 according to an embodiment of the present invention.

5 is a signal timing diagram of the control signal generator.

6 is an internal circuit diagram of the unit delay unit of FIG. 2 according to one embodiment of the present invention;

* Description of the main parts of the drawing

100: control signal generator

120, 140, 160: unit delay unit

180: buffer

200: three phase inverter

According to an aspect of the present invention, there is provided a device for generating a pixel clock synchronized with a horizontal synchronization signal using a delay lock loop, wherein the delay is in response to an input clock signal having various phase differences from the horizontal synchronization signal. Control signal generating means for generating first to third control signals for controlling the fixed loop; A plurality of unit delay means controlled by the first to third control signals and sequentially delaying the input clock signal for a predetermined time; Buffering means connected to a common output terminal of the plurality of unit delay means for outputting the pixel clock synchronized with the horizontal synchronization signal through a buffering operation; And first means for fixing the pixel clock low in a low section of the horizontal synchronization signal in response to the first control signal output from the control signal generating means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 2 is a block diagram of an apparatus for generating a pixel clock according to an exemplary embodiment of the present invention, and includes a plurality of signals for controlling a delay locked loop in response to a clock signal CK_IN having various phase differences from a horizontal synchronization signal HS. The control signal generator 100 for generating the control signals HS_B, HS_C, and SHS_B of the control signal is controlled by a plurality of control signals HS_B, HS_C, and SHS_B, and sequentially delays the clock signal CK_IN for a predetermined time. A buffer connected to a common output terminal of the plurality of unit delay units 120, 140 and 160 and the unit delay units 120, 140 and 160 to output a pixel clock CK_OUT synchronized to the horizontal synchronization signal HS through a buffering operation ( 180, a tri-state inverter 200 for fixing the pixel clock CK_OUT low in response to the control signal HS_B output from the control signal generator 100.

First, the characteristics of the horizontal synchronous signal HS and the input clock signal CK_IN input to the apparatus of the present invention and the pixel clock CK_OUT synchronized to the horizontal synchronous signal HS output through the present invention are illustrated in FIG. 3. This will be described with reference to the signal timing diagram shown in FIG.

Referring to the signal timing diagram of FIG. 3, HS is a horizontal synchronization signal input to the circuit of the present invention, and five CK_INs are clocks inputted with various phase differences asynchronously with HS. The pixel clock (CK_OUT) of the scan line used in televisions, monitors, etc. must be synchronized with this independent HS to produce a jitter-free picture. At this time, CK_OUT is output low in the period in which HS is high, but from the moment HS becomes low, it must always survive as a clock after 8 Tdelay time delay. It means that CK_OUT should occur after a certain time Tdelay even if the input CK_IN is input as any phase difference of HS.

In detail, when the horizontal synchronization signal HS and the input clock signal CK_IN are input to the control signal generator 100, the control signal generator 100 generates signals of the control signals HS_B, HS_C, and SHS_B. , And output these signals to the input of the unit delay unit (120, 140, 160). In addition, the input clock signal CK_IN is applied to the input of the first unit delay unit 120. The unit delay units 120, 140, and 160 connected in series are output synchronized with HS as shown in CK_OUT of FIG. Create

4 is an internal circuit diagram of the control signal generator 100 of FIG. 2 according to an embodiment of the present invention, and FIG. 5 is a signal timing diagram of the control signal generator.

As shown in FIG. 4, the control signal generation unit generates the HS_B signal, which is a horizontal synchronization signal of the active row, through the inverter 210, and controls the inverter 220, the delay circuit unit 230, and the AND gate 240. Through this, a signal HS_C having a width equal to the delay time of the delay circuit unit 230 in the vicinity where the HS goes low (see also the signal timing of FIG. 5) is produced. HS is then delayed after being sampled by CK_IN through flip-flops 250, 260, 270, and 280 using the input clock signal CK_IN as the clock input. The active low signal SHS_B near the beginning of the HS sampled by the inverter 290 and the negative logic gate 300 through the outputs of the flip-flop 260 and the flip-flop 280 (see also the signal timing of FIG. 5). )

6 is an internal circuit diagram of the unit delay unit of FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 6, the unit delay unit generates CK_O which has passed through the inverter 310, the delay circuit unit 320, the inverter 330, and the delay circuit unit 340. This CK_O enters the input of CK_I of the next unit delay section of the continuous unit delay section. The maximum unit of jitter produced by the DLL is the delay difference between CK_I and CK_O. In other words, the DLL can synchronize with the HS with the precision of the time difference between CK_I and CK_O.

An active high pulse of the rising edge of CK_I is generated through the inverter 350, the delay circuit unit 360, the inverter 370, and the AND gate 380.

Negative logic gate 390 uses the active high pulses of HS_C and CK_I to find the rising edge of CK_I that is sensed where HS falls low. The output of negative logic gate 390 takes the form of an active low pulse.

The delay circuit unit 400 serves as a kind of low pass filter, and removes the pulse when the pulse width generated by the negative logic gate 390 is too small.

The SR latch 410 of the negative logic type receives the filtered pulse from the delay circuit unit 400 and sets the DC high. The SR latch 410 also resets the DC low by the HS_B signal.

The DC thus made enters the input DP of the next unit delay. The DC of FIG. 6 makes the output of the AND gate 420 high only when the external input DP is low. The flip-flop 430 having the reset terminal samples the output of the AND gate 420 using the clock CK_I. Meanwhile, the flip-flop 430 is reset low by SHS_B. Flip-flop 440 samples the output of flip-flop 430. The output of the flip-flop 430 is made of an SN signal, which enters the SP input of the next unit delay unit. The SN signal is made via the OR gate 450. While the SN signal is initially made high in the first unit delay unit 120 in FIG. 2, the SPs and SNs of the remaining unit delay units are continuously made high.

Again in FIG. 6, the output of flip-flop 440 makes input of flip-flop 470 high only when SP is low via AND gate 460. Flip-flop 470 samples the output of AND gate 460 when the falling edge of CK_I.

The negative logic gate 480 outputs a low output only when HS_B is high and the output of the sampled flip-flop 470 is high. Only at this time, CK_O may be output to CKT_O through the three-phase buffer 490. . If the output of the negative logic gate 480 is high, the three-phase buffer 490 emits a high impedance Hi-Z.

In FIG. 2, the unit delay units 120, 140, and 160 connected in series detect the rising edge of CK_I of each unit delay unit near the falling edge of HS by comparing HS and CK_IN. In this case, the CK_O of the unit delay unit that is detected first is output through the CKT_O.

The three-phase inverter 200 of FIG. 2 causes the CK_OUT to have a low value in a section in which HS is low. The CKT_O generated by the unit delay unit is output through the buffer 180.

By doing this, CK_IN produces HS and CK_OUT which always starts after a certain time.

For reference, the number of unit delay units Must be at least

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above can be integrated inside an integrated circuit, and since the LC oscillator is not used, noise in the system board can be reduced.

Claims (4)

An apparatus for generating a pixel clock synchronized to a horizontal synchronization signal using a delay locked loop, Control signal generation means for generating first to third control signals for controlling the delay locked loop in response to an input clock signal having various phase differences from the horizontal synchronization signal; A plurality of unit delay means controlled by the first to third control signals and sequentially delaying the input clock signal for a predetermined time; Buffering means connected to a common output terminal of the plurality of unit delay means for outputting the pixel clock synchronized with the horizontal synchronization signal through a buffering operation; And First means for fixing the pixel clock low in a low section of the horizontal synchronization signal in response to the first control signal output from the control signal generating means Device comprising a. The method of claim 1, wherein the control signal generating means, Inverting means for receiving the horizontal synchronizing signal and inverting the horizontal synchronizing signal to output the first control signal (HS_B) which is a horizontal synchronizing signal of an active row; Second means for detecting when the horizontal synchronization signal transitions low and outputting the second control signal HS_C having a predetermined pulse width; First to fourth flip-flops receiving the input clock signal to a clock input terminal and sampling and delaying the horizontal synchronization signal; And Negative logic means for receiving the outputs of the second and fourth flip-flops and performing negative logic multiplication to output the third control signal SHS_B. Device comprising a. The method of claim 2, wherein the second means, A delay circuit unit for delaying the horizontal synchronization signal for a predetermined time; And Logic multiplication means for outputting the second control signal (HS_C) by ANDing the output of the delay circuit portion and the horizontal synchronization signal Device comprising a. The method of claim 1, wherein each of the plurality of unit delay means, A delay circuit unit for delaying a clock input signal CK_I applied to a clock input terminal for a predetermined time and then outputting the output clock signal CK_O applied to the clock input terminal of a unit delay means; First signal generating means for generating a signal having a predetermined pulse width in response to the rising edge of the clock input signal CK_I applied to the clock input terminal; In response to the signal from the first signal generating means and the second control signal HS_C, the rising edge of the clock input signal CK_I sensed when the horizontal synchronization signal transitions low to a signal having a predetermined pulse width. Second signal generating means for outputting; Filtering means for removing pulses when the pulse width of the signal output from the second signal generating means is relatively small; SR which receives the output of the filtering means as a set terminal, receives the first control signal HS_B as a reset terminal, and sends out a first output DC applied to the first input DP of the next unit delay means. Latch; First logical AND means for receiving and ORing the first output DC output from the SR latch and the first input DP applied to the unit delay means; A first flip-flop sampling the output of the first AND product in response to the clock input signal CK_I and reset by the third control signal; A second flip-flop sampling the output of the first flip-flop; A logical sum means for receiving the output of the first flip-flop and the second input SP and performing logical sum on the output of the first flip-flop and then outputting the logical value to a second output SN connected to the second input SP of a unit delay unit; Second logical AND means for ANDing the output of the second flip-flop with the second input (SP); A third flip-flop sampling the output of the second AND product at the falling edge of the clock input signal in response to the clock input signal; Negative logical multiplication means for negative logic multiplying the output of the third flip-flop and the first control signal; And Output means for outputting the output clock signal CK_O to an input of the buffering means in response to the output of the negative logical means Device comprising a.