JP2011171974A - Cyclic type a/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cyclic type A/D converter achieving increase of the speed of an A/D conversion processing by shortening the A/D (an analog-digital) conversion processing time while reducing the circuit area of an incorporated IC (an integrated circuit). <P>SOLUTION: The cyclic type A/D converter converts an analog signal into a digital signal by successively repeating comparison operations towards lower bits from upper bits. The cyclic type A/D converter has an operation-clock generating means generating operation clocks on the basis of an input master clock so that operation cycles corresponding to each bit are reduced successively towards the lower bits from the upper bits. The cyclic type A/D converter also has an A/D conversion means successively repeating the comparison operations towards the lower bits from the upper bits by using the operation clocks generated by the operation-clock generating means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a cyclic A / D (analog-digital) converter, and more particularly to a cyclic A / D converter that shortens the A / D conversion processing time.

  In recent years, sensoring technology has progressed, and various sensoring technologies are also used in in-vehicle systems. In such an in-vehicle system, since a large number of sensing signals are required and the sensing signals are processed in a time-sharing manner, it is indispensable to increase the speed of A / D conversion processing for the sensing signals. Further, in an A / D converter incorporating an integrated circuit (IC), an input sensing signal is A / D converted by the IC. In this case, the IC incorporated in the A / D converter is required to be small and low cost.

  As a method for speeding up the A / D conversion process, there is a method of reducing the operation cycle by setting the unit of comparison operation in the A / D conversion process to 2 bits or more (for example, see Patent Document 1). However, this method requires a high-accuracy DAC (digital analog converter) circuit of 2 bits or more, and thus increases the circuit area of the A / D conversion circuit.

  Therefore, a cyclic A / D converter (1 bit / stage) is applied. In the cyclic A / D converter (1 bit / stage), the unit of the comparison operation in the A / D conversion process is 1 bit, and the comparison and the operation are executed using the same circuit. For this reason, the IC incorporated in the cyclic A / D converter does not require a high-precision DAC circuit, and the circuit area can be reduced.

  FIG. 5 is a diagram showing an A / D conversion processing time in a conventional cyclic A / D converter. In FIG. 5, in the first cycle to the Nth cycle (N is the number of bits), the comparison operation is repeated in order from the most significant bit in 1-bit units.

Specifically, in the conventional cyclic A / D converter, when the comparison operation is repeated in order from the most significant bit, the comparison operation processing time t1 required by the most significant bit is determined in view of the quantization tolerance. Is done. Further, for the first cycle to the Nth cycle corresponding to each bit, an N-bit comparison operation process is performed using a single-frequency operation clock. In other words, in the conventional cyclic A / D converter, the operation clock is generated in the operation cycle (frequency) corresponding to each bit in accordance with the comparison operation processing time of the most significant bit that maximizes the comparison operation processing time. Yes. Therefore, the A / D conversion processing time T in the conventional cyclic A / D converter is expressed by the following (Equation 1) using the comparison operation processing time t1 required by the most significant bit.
T = t1 × N (Equation 1)

Japanese Patent No. 3458812

  However, in the conventional cyclic A / D converter, the comparison operation processing time of each bit is the same as the comparison operation processing time of the most significant bit that maximizes the comparison operation processing time, and is optimal for each bit. The operation clock is not generated in a simple operation cycle. For this reason, the conventional cyclic A / D converter has a problem that the entire A / D conversion process cannot be speeded up.

  Note that, in the conventional cyclic A / D converter, if the acceleration processing is applied only to the comparison operation of the most significant bit where the comparison operation processing time is maximum, the entire A / D conversion processing can be accelerated. However, in this case, since a high-speed processing circuit used only for the most significant bit comparison operation processing is required, the IC incorporated in the A / D converter does not satisfy the demand for small size and low cost.

  Therefore, the present invention provides a cyclic A / D converter that realizes a high speed A / D conversion process by reducing the circuit area of an integrated IC and shortening the A / D conversion process time. It is to be.

In order to achieve the above object, a cyclic A / D converter according to the present invention repeats a comparison operation in order from an upper bit to a lower bit to convert an analog signal into a digital signal. A digital) converter for generating an operation clock based on an input master clock so that an operation cycle corresponding to each bit decreases in order from an upper bit to a lower bit; A / D conversion means for repeating the comparison operation in order from the upper bit to the lower bit using the operation clock generated by the clock generation means.
According to such a configuration, in order to apply a cyclic A / D converter (1 bit / stage) that performs comparison and calculation using the same circuit with a unit of comparison calculation in A / D conversion processing as 1 bit, A high-accuracy DAC circuit is not required, and the circuit area of the integrated IC can be reduced. At the same time, according to the cyclic A / D converter of the present invention, since the operation clock is generated in the optimum operation cycle corresponding to each bit, the A / D conversion processing time can be shortened, and the A / D conversion is performed. Speeding up of processing can be realized.

Further, the preferred operation clock generation means is characterized in that an operation cycle is determined according to an allowable error corresponding to each bit when the comparison operation is performed by the A / D conversion means.
According to such a configuration, since the calculation cycle is determined according to the allowable error corresponding to each bit, a highly accurate A / D conversion process can be realized.

The cyclic A / D converter according to the present invention further includes master clock determining means for determining a master clock based on the processing time of the least significant bit compared and calculated by the A / D converting means.
According to this configuration, since the master clock is determined based on the time required for the operation of the least significant bit, the operation clock can be generated in the optimal operation cycle corresponding to each bit.

Further, the preferred master clock determining means is characterized in that the operation cycle corresponding to the least significant bit is set as the cycle of the master clock.
According to such a configuration, the arithmetic cycle corresponding to the least significant bit is set as the master clock cycle, so that the A / D conversion processing time can be optimally shortened.

Furthermore, the operation cycle corresponding to each preferred bit is characterized in that the master clock cycle is added each time the bit is one higher.
According to such a configuration, the operation cycle corresponding to each bit is added by the period of the master clock every time the bit is one higher, so that the total operation time in the A / D conversion process can be further shortened. Can do.

  In addition, in order to achieve the above object, each process performed by each configuration of the cyclic A / D converter described above can be regarded as a cyclic A / D conversion method that provides a series of processing procedures. This method is provided in the form of a program for causing a computer to execute a series of processing procedures. This program may be installed in a computer in a form recorded on a computer-readable recording medium.

  As described above, according to the cyclic A / D converter of the present invention, the unit of the comparison operation in the A / D conversion process is 1 bit, and the cyclic A / D that performs comparison and calculation using the same circuit. Since the D converter (1 bit / stage) is applied, a high-accuracy DAC circuit is not required, and the circuit area of the IC to be incorporated can be reduced. At the same time, according to the cyclic A / D converter of the present invention, since the operation clock is generated in the optimum operation cycle corresponding to each bit, the A / D conversion processing time can be shortened, and the A / D conversion is performed. Speeding up of processing can be realized.

The figure which shows the cyclic | annular A / D converter 10 which concerns on one Embodiment of this invention. The figure which shows a mode that the cyclic | annular A / D conversion circuit 100 repeats a comparison operation in order from an upper bit to a lower bit, and converts an analog signal into a digital signal. The figure which shows the tolerance in a most significant bit about the A / D conversion process in the cyclic | annular A / D converter 10 The figure which shows the A / D conversion processing time in the cyclic | annular A / D converter 10 which concerns on one Embodiment of this invention. The figure which shows the A / D conversion processing time in the conventional cyclic | annular A / D converter

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a cyclic A / D converter 10 according to an embodiment of the present invention. In FIG. 1, the cyclic A / D converter 10 includes a cyclic A / D conversion circuit 100 and an arithmetic clock generation circuit 200. The cyclic A / D converter circuit 100 includes a first switch 101, a sampling hold (S / H) circuit 102, a comparator 103, a shift calculator 104, a second switch 105, and a multiplier 106. And an adder 107.

  First, the operation clock generation circuit 200 generates an operation clock based on the input master clock so that the operation cycle corresponding to each bit decreases in order from the upper bit to the lower bit. A detailed description of the operation clock generated by the operation clock generation circuit 200 will be described later.

  Then, the cyclic A / D conversion circuit 100 uses the operation clock generated by the operation clock generation circuit 200 to repeat the comparison operation in order from the upper bit to the lower bit to convert the analog signal into a digital signal.

  FIG. 2 is a diagram illustrating a state in which the cyclic A / D conversion circuit 100 repeats comparison operations in order from the upper bit to the lower bit to convert an analog signal into a digital signal.

  In the cyclic A / D conversion circuit 100, the input signal Vin is input to the S / H circuit 102 via the first switch 101.

  The S / H circuit 102 samples the input signal Vin as the sampling signal V1, and holds it for a certain time.

  The comparator 103 compares the sampling signal V1 with the reference voltage V0, and outputs the comparison result to the shift calculator 104 and the second switch 105. In the present embodiment, the sampling signal V1 is larger than the reference voltage V0. The reference voltage V0 is the midpoint of −Vref to + Vref within the A / D conversion range.

  The shift calculator 104 performs a shift operation based on the comparison result output from the comparator 103 and outputs the result. Here, since the sampling signal V1 is larger than the reference voltage V0, the shift calculator 104 outputs “1” as a result of the shift calculation.

  Based on the comparison result output from the comparator 103, the second switch 105 is switched to output either + Vref or -Vref with respect to the reference voltage Vref within the A / D conversion range. Here, since the sampling signal V1 is larger than the reference voltage V0, the second switch 105 is switched to output −Vref.

  The multiplier 106 doubles the sampling signal V1 sampled by the S / H circuit 102.

  The adder 107 adds -Vref output from the second switch 105 to the sampling signal V1 doubled by the multiplier 106, and outputs the addition result as the next sampling signal V2.

  The sampling signal V2 is input to the S / H circuit 102 via the first switch 101. After the input signal Vin is input to the S / H circuit 102 via the first switch 101, the addition result output from the adder 107 is input to the S / H circuit 102 via the first switch 101. As described above, the first switch 101 is switched.

  Next, the comparator 103 compares the sampling signal V2 with the reference voltage V0, and outputs the comparison result to the shift calculator 104 and the second switch 105. In the present embodiment, the sampling signal V2 is smaller than the reference voltage V0.

  The shift calculator 104 performs a shift operation based on the comparison result output from the comparator 103 and outputs the result. Here, since the sampling signal V2 is smaller than the reference voltage V0, the shift calculator 104 outputs “0” as a result of the shift calculation.

  Based on the comparison result output from the comparator 103, the second switch 105 is switched to output either + Vref or -Vref with respect to the reference voltage Vref within the A / D conversion range. Here, since the sampling signal V2 is smaller than the reference voltage V0, the second switch 105 is switched to output + Vref.

  The multiplier 106 doubles the sampling signal V2 output from the S / H circuit 102.

  The adder 107 adds + Vref output from the second switch 105 to the sampling signal V2 doubled by the multiplier 106, and outputs the addition result as the next sampling signal V3.

  The sampling signal V3 is input to the S / H circuit 102 via the first switch 101. The first switch 101 and the second switch 105 are switched by control by a control unit (not shown).

  Thus, the same comparison operation is repeated for the sampling signal V3 and the next sampling signal V4, and the cyclic A / D conversion circuit 100 A / D converts the input signal Vin into the output signal Vout “1001”. Yes.

FIG. 3 is a diagram showing an allowable error at the most significant bit in the A / D conversion process in the cyclic A / D converter 10. In FIG. 3, when the N-bit A / D conversion process is started, the quantization allowable error Verr is expressed by the following (Equation 2) using the reference voltage Vref in the A / D conversion range.
Verr = 2Vref / 2 ^{(N + 1) (} Expression 2)

When the time constant τ of the A / D conversion circuit is used, the relationship with the time t until reaching the allowable error is expressed by the following (Equation 3).
2Vref / 2 ^{(N + 1)} = << 2Vref × e (−t / τ) (Equation 3)

Furthermore, the following (Equation 4) and (Equation 5) are derived from (Equation 3).
t >> = (N + 1) τln (2) (Expression 4)
t ≈ 0.7 (N + 1) τ (Expression 5)
Note that ln (2) ≈0.7.

  As described above, the cyclic A / D conversion circuit 100 repeats the comparison operation in order from the upper bit to the lower bit while the multiplier 106 doubles the sampling signal. That is, since the amplitude of the sampling signal is doubled every cycle, the allowable error is also doubled every cycle. Therefore, the time t until the allowable error is reached decreases to 0.7 (N) τ, 0.7 (N−1) τ, 0.7 (N−2) τ,.

  Here, the operation clock generation circuit 200 generates an operation clock based on the master clock in accordance with the operation cycle in the cyclic A / D conversion circuit 100. Hereinafter, the operation clock generated by the operation clock generation circuit 200 will be described in detail.

  FIG. 4 is a diagram showing an A / D conversion processing time in the cyclic A / D converter 10 according to an embodiment of the present invention. As described with reference to FIG. 1 and FIG. 2, the cyclic A / D converter 10 moves from the upper bit to the lower bit in 1-bit units from the first cycle to the Nth cycle (N is the number of bits). The comparison operation is repeated in order. Here, it is assumed that the cyclic A / D converter 10 has an allowable error at the most significant bit shown in FIG. 3 for the A / D conversion processing.

  In FIG. 4, in the conventional cyclic A / D converter, the calculation time of the first cycle (most significant bit) is set to 0.7 (N + 1) τ from (Equation 5) described above, and the first cycle (maximum The master clock was determined in accordance with the calculation time of the upper bits). In other words, the conventional cyclic A / D converter uses a single-frequency operation clock from the first cycle (most significant bit) to the Nth cycle (lowest bit) corresponding to each bit, from the upper bit to the lower bit. The comparison operation was repeated in order toward the bit. For this reason, the A / D conversion processing time T in the conventional cyclic A / D converter is T = 0.7 (N + 1) τ × N.

  On the other hand, the cyclic A / D converter 10 according to an embodiment of the present invention does not use a single-frequency operation clock, but uses an operation clock corresponding to each bit to move from an upper bit to a lower bit. Repeat the comparison operation in order.

  Here, the arithmetic clock generation circuit 200 in the cyclic A / D converter 10 according to an embodiment of the present invention generates an arithmetic clock corresponding to each bit based on a master clock that is faster than the arithmetic clock. Determine the operation cycle to be performed.

  The master clock is sufficiently faster than the operation clock and may be set in advance or may be set by calculating the operation time of the Nth operation cycle (least significant bit). . Hereinafter, the relationship between the master clock and the operation clock corresponding to each bit will be described in detail.

  In FIG. 4, in the cyclic A / D converter 10 according to an embodiment of the present invention, the calculation time of the Nth cycle (least significant bit) is 0.7 × 2τ from (Equation 5) described above. That is, when the quantization tolerance in the least significant bit is taken into consideration, the time required for the operation in the Nth cycle (the least significant bit) is 0.7 × 2τ. The master clock is set to 0.7τ, and the time required for the calculation in the Nth cycle (least significant bit) may be 0.7τ logically. In the present embodiment, in order to correct the non-linear error in the A / D conversion process and ensure the required accuracy (linearity), the calculation time of the Nth cycle (least significant bit) is considered in consideration of the margin. Is set to 0.7 × 2τ.

  As described above, the arithmetic clock generation circuit 200 in the cyclic A / D converter 10 according to the embodiment of the present invention generates the arithmetic clock corresponding to each bit based on the master clock having a period of 0.7τ. The operation cycle to be performed is determined. Specifically, as shown in FIG. 4, the operation clock generation circuit 200 sets the operation time of the Nth cycle (least significant bit) to 0.7 × 2τ and the operation time of the (N−1) th cycle to 0. 0. 7 × 3τ, the calculation time of the (N−2) cycle is 0.7 × 4τ,..., The calculation time of the third cycle is 0.7 × (N−1) τ, and the calculation time of the second cycle is The operation time for the first cycle is determined to be 0.7 × (N + 1) τ, and the operation clock corresponding to each bit is generated.

  Then, the cyclic A / D converter circuit 100 in the cyclic A / D converter 10 according to the embodiment of the present invention uses the operation clock generated by the operation clock generation circuit 200 to change from the upper bit to the lower bit. The comparison operation is repeated in order. Therefore, the A / D conversion processing time T in the cyclic A / D converter 10 according to the embodiment of the present invention is T = 0.7 (N + 1) τ × (1 + N) / 2.

  That is, the cyclic A / D converter 10 according to an embodiment of the present invention generates an operation clock in accordance with the time required for the operation of each cycle (bit), and the cycle of each cycle is generated by the generated operation clock. The calculation time is optimized.

  Therefore, the cyclic A / D converter 10 according to the embodiment of the present invention generates an operation clock in an optimal operation cycle corresponding to each bit, and repeats the comparison operation in order from the upper bit to the lower bit. Therefore, compared with the conventional cyclic A / D converter in which the comparison operation is repeated in order from the upper bit to the lower bit using a single frequency operation clock, all operations in the first cycle to the Nth cycle are performed. Time T can be shortened.

  As described above, according to the cyclic A / D converter 10 according to the embodiment of the present invention, the unit of the comparison operation in the A / D conversion process is 1 bit, and the comparison and the operation are performed using the same circuit. Since the cyclic A / D converter (1 bit / stage) to be executed is applied, a high-accuracy DAC circuit is not required, and the circuit area of the integrated IC can be reduced. At the same time, according to the cyclic A / D converter 10 according to the embodiment of the present invention, the operation clock is generated in the optimum operation cycle (first to Nth cycles) corresponding to each bit. Conversion processing time can be shortened, and high speed A / D conversion processing can be realized.

  In addition, according to the cyclic A / D converter 10 according to the embodiment of the present invention, the operation cycle (first to first) corresponding to each bit is determined according to the allowable error corresponding to each bit illustrated in FIG. N cycles) can be determined, so that highly accurate A / D conversion processing can be realized.

  Further, according to the cyclic A / D converter 10 according to the embodiment of the present invention, the period (0.7τ) of the master clock is set based on the time required for the operation of the Nth cycle (least significant bit). Therefore, the operation clock can be generated in the optimum operation cycle (first to Nth cycles) corresponding to each bit.

  Further, according to the cyclic A / D converter 10 according to the embodiment of the present invention, since the operation cycle corresponding to the Nth cycle (least significant bit) is the period of the master clock, the A / D conversion processing time Can be shortened optimally.

  Further, according to the cyclic A / D converter 10 according to the embodiment of the present invention, the operation cycle corresponding to each bit is equal to the master clock period (0.7τ) every time the bit is one higher. ) Is added, the total calculation time T of the first to Nth cycles can be further shortened.

  In the cyclic A / D converter 10 according to the present embodiment, the cyclic A / D converter circuit 100 shown in FIG. 1 is used. However, the circuit is not limited to this and has other circuit configurations. A cyclic A / D conversion circuit may be used.

  The time constant τ of the A / D conversion circuit depends on the circuit configuration of the A / D conversion circuit. In other words, the time constant τ is determined in advance according to the A / D conversion circuit used in the cyclic A / D converter. Therefore, when the value of the number of bits N in the A / D conversion process is also set in advance, the master clock and the operation clock corresponding to each bit can be calculated in advance. Thereby, the arithmetic clock generation circuit may generate an arithmetic clock corresponding to each bit calculated in advance.

  In sensoring technology that requires a large number of sensing signals, it is useful for reducing the circuit area of an integrated IC and increasing the speed of A / D conversion processing.

DESCRIPTION OF SYMBOLS 10 Cyclic A / D converter 100 Cyclic A / D converter circuit 200 Operation clock generation circuit 101 1st switch 102 Sampling hold (S / H) circuit 103 Comparator 104 Shift computing unit 105 2nd switch 106 Multiplier 107 adder

Claims (6)

A cyclic A / D (analog-digital) converter that converts an analog signal into a digital signal by repeating comparison operations in order from the upper bit to the lower bit;
Arithmetic clock generating means for generating an arithmetic clock based on an input master clock so that the arithmetic cycle corresponding to each bit decreases in order from the upper bit to the lower bit;
A cyclic A / D converter comprising: an A / D converter that repeats a comparison operation in order from an upper bit to a lower bit using the operation clock generated by the operation clock generation unit.   2. The operation clock generation unit according to claim 1, wherein the operation clock generation unit determines the operation cycle in accordance with an allowable error corresponding to each bit when the A / D conversion unit performs comparison operation. Cyclic A / D converter.   3. The cyclic A / C according to claim 1, further comprising: a master clock determination unit that determines the master clock based on a processing time of a least significant bit that is compared and calculated by the A / D conversion unit. D converter.   The cyclic A / D converter according to claim 3, wherein the master clock determination unit sets an operation cycle corresponding to the least significant bit as a cycle of the master clock.   5. The cyclic A / D converter according to claim 4, wherein the operation cycle corresponding to each bit is incremented by a period of the master clock every time a bit becomes one higher. A computer for causing a cyclic A / D converter to execute a cyclic A / D (analog-digital) conversion method for converting an analog signal into a digital signal by repeating comparison operations in order from the upper bit to the lower bit. A readable program,
An operation clock generation step for generating an operation clock based on an input master clock so that the operation cycle corresponding to each bit decreases in order from the upper bit to the lower bit;
A program for causing the cyclic A / D converter to execute an A / D conversion step that repeats a comparison operation in order from an upper bit to a lower bit using the operation clock generated by the operation clock generation step .

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